Sensor pixel unit and electronic equipment

Abstract

The embodiment of the utility model discloses a sensor pixel unit and electronic equipment, and the sensor pixel unit comprises a photodiode, a first reset transistor, an auxiliary circuit, a positive feedback unit, a signal conversion module and a signal triggering module. One end of the photodiode is grounded, and the other end is connected with the drain end of the reset transistor, the auxiliary circuit and the positive feedback unit; the source end of the reset transistor is connected with an analog power supply signal, the drain end is connected with the other end of the photodiode, and the gate end receives an analog reset signal; one end of the positive feedback unit is connected with the other end of the photodiode, and the other end is connected with the signal conversion module as a first output end; one end of the auxiliary circuit is connected with the other end of the photodiode, and the other end serves as a second output end; one end of the signal conversion module is connected with the positive feedback unit, and the other end is connected with the signal trigger module; and the signal triggering module is connected with the signal conversion module.

Description

Technical Field

[0001] This disclosure relates to the field of sensor technology, and in particular to a sensor pixel unit and electronic device. Background Technology

[0002] Pulse sequence image sensors reflect light intensity by detecting the time required for photogenerated charge to accumulate to a certain threshold; the stronger the light, the shorter the time required for photogenerated charge to accumulate to the threshold. In actual imaging, the light intensity received by each pixel unit in the pixel array varies, and the time it takes for its photogenerated charge to reach the threshold also differs. For signal readout, if the pixel array signal is read synchronously at a fixed frame rate, some pixel units will inevitably reach the threshold early, while the signal cannot be output until all other pixel units have reached the threshold. Clearly, this readout method has low time efficiency and fails to reflect the light intensity corresponding to each pixel unit. Utility Model Content

[0003] This disclosure provides a sensor pixel unit and an electronic device.

[0004] One aspect of this disclosure provides a sensor pixel unit, including: a photodiode, a first reset transistor, an auxiliary circuit, a positive feedback unit, a signal conversion module, and a signal triggering module;

[0005] One end of the photodiode is grounded, and the other end is connected to the drain terminal of the reset transistor, the auxiliary circuit, and the positive feedback unit.

[0006] The source terminal of the reset transistor is connected to the analog power supply signal, the drain terminal is connected to the other end of the photodiode, and the gate terminal receives the analog reset signal.

[0007] One end of the positive feedback unit is connected to the other end of the photodiode, and the other end is connected to the signal conversion module as the first output terminal.

[0008] One end of the auxiliary circuit is connected to the other end of the photodiode, and the other end serves as the second output terminal.

[0009] One end of the signal conversion module is connected to the positive feedback unit, and the other end is connected to the signal triggering module;

[0010] The signal triggering module is connected to the signal conversion module.

[0011] Optionally, the positive feedback unit includes a first inverter and a pull-down transistor;

[0012] The pull-down transistor is connected in parallel with the input and output terminals of the first inverter through its drain and gate terminals, and the source terminal of the pull-down transistor is grounded.

[0013] The first inverter converts the input voltage signal into an analog power signal, and uses the output terminal of the first inverter as the first output terminal to input the analog power signal into the signal conversion module.

[0014] Optionally, the auxiliary circuit includes a source follower transistor and a readout transistor;

[0015] The source terminal of the source follower transistor is connected to the analog power supply signal, the gate terminal is connected to the other end of the photodiode, the drain terminal of the reset transistor and the positive feedback unit, and the drain terminal is connected to the drain terminal of the readout transistor.

[0016] The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the gate terminal receives the readout signal, and the source terminal serves as the second output terminal.

[0017] Optionally, the first reset transistor, the pull-down transistor, the source follower transistor, the readout transistor, and the two transistors included in the first inverter are high-voltage transistors.

[0018] Optionally, the signal conversion module includes: a second inverter composed of a first conversion transistor and a second conversion transistor;

[0019] The gate terminal of the first conversion transistor is connected to the gate terminal of the second conversion transistor as the input terminal of the second inverter, and the drain terminal of the first conversion transistor is connected to the source terminal of the second conversion transistor as the output terminal of the second inverter; the source terminal of the first conversion transistor is connected to the digital power supply signal, and the drain terminal of the second conversion transistor is grounded.

[0020] Optionally, the first switching transistor and the second switching transistor are high-voltage transistors.

[0021] Optionally, the signal triggering module includes: a pulse output transistor, an enable transistor, a request transistor, and a pulse latch unit;

[0022] The drain terminal of the pulse output transistor is connected to the signal conversion module, the gate terminal of the request transistor, and the pulse latch unit. The gate terminal is connected to the enable signal, and the source terminal serves as the third output terminal.

[0023] The drain terminal of the enable transistor is connected to the digital power signal, the source terminal is connected to the source terminal of the request transistor, and the gate terminal is connected to the pulse latch unit.

[0024] The source terminal of the request transistor is connected to the source terminal of the enable transistor, the gate terminal is connected to the signal conversion module, and the drain terminal serves as the fourth output terminal.

[0025] The pulse latch unit is connected to the signal conversion module and the gate terminal of the enable transistor.

[0026] Optionally, the pulse latch unit includes: a second reset transistor, a third inverter, a trigger-stop transistor, and a request-enable transistor;

[0027] The source terminal of the second reset transistor is connected to the digital power supply signal, the drain terminal is connected as a latch point to the source terminal of the trigger-stop transistor and the source terminal of the request-allow transistor, and the gate terminal receives the digital reset signal.

[0028] The request allows the source terminal of the transistor to be connected to the latch point, the drain terminal to be connected to the signal conversion module, and the gate terminal to receive the enable signal;

[0029] The input terminal of the third inverter is connected to the latch point, and the output terminal is connected to the gate terminal of the enable transistor.

[0030] The trigger-stop transistor is connected in parallel with the third inverter through its source and gate terminals, and its drain terminal is grounded.

[0031] Optionally, the pulse output transistor, enable transistor, request transistor, second reset transistor, trigger termination transistor, request enable transistor in the signal triggering module, and the transistors included in the third inverter are all low-voltage transistors.

[0032] In another aspect of the present disclosure, an electronic device is provided, including: a processor, and a memory communicatively connected to the processor, and further including the sensor pixel unit described in any of the above embodiments;

[0033] The memory stores computer-executed instructions;

[0034] The processor executes computer execution instructions stored in the memory to control the sensor pixel units.

[0035] Optionally, the electronic device may be included as any of the following: image data acquisition device, audio / video player, navigation device, entertainment device, communication device, roadside traffic facility, device in motor vehicle, industrial testing device, flight equipment, medical device, security device.

[0036] The sensor pixel unit, signal processing circuit, and electronic device provided in the above embodiments of this disclosure include: a photodiode, a first reset transistor, an auxiliary circuit, a positive feedback unit, a signal conversion module, and a signal triggering module; one end of the photodiode is grounded, and the other end is connected to the drain terminal of the reset transistor, the auxiliary circuit, and the positive feedback unit; the source terminal of the reset transistor is connected to an analog power supply signal, the drain terminal is connected to the other end of the photodiode, and the gate terminal receives an analog reset signal; one end of the positive feedback unit is connected to the other end of the photodiode, and the other end serves as a first output terminal connected to the signal conversion module; one end of the auxiliary circuit is connected to the other end of the photodiode, and the other end serves as a second output terminal; one end of the signal conversion module is connected to the positive feedback unit, and the other end is connected to the signal triggering module; the signal triggering module is connected to the signal conversion module. In this embodiment of the present disclosure, when the first analog signal reaches a preset threshold during the exposure cycle, a first digital signal is requested to be sent to achieve asynchronous reading of the pixel unit; and when the exposure cycle is reached, a second analog signal is output to achieve synchronous reading of the pixel unit; thus, a working mode combining synchronous and asynchronous reading of the pixel unit is achieved. While expressing the light intensity signal with strong light intensity through asynchronous reading, the output of the light intensity signal with weak light intensity is ensured during the exposure cycle through synchronous reading, thus combining the beneficial effects of synchronous and asynchronous reading.

[0037] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0038] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0039] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0040] Figure 1 This is a schematic diagram of the circuit structure of a sensor pixel unit provided in an exemplary embodiment of this disclosure;

[0041] Figure 2 This is a schematic diagram of the circuit structure of the optical signal processing module in a sensor pixel unit provided in another exemplary embodiment of this disclosure;

[0042] Figure 3 This is a schematic diagram of the circuit structure of the signal conversion module in a sensor pixel unit provided in yet another exemplary embodiment of this disclosure;

[0043] Figure 4 This is a schematic diagram of the circuit structure of the signal triggering module in a sensor pixel unit provided in an exemplary embodiment of the present disclosure;

[0044] Figure 5 This is a schematic diagram of the circuit structure of the signal triggering module in a sensor pixel unit provided in another exemplary embodiment of the present disclosure;

[0045] Figure 6 This is a schematic diagram of the circuit structure of a sensor pixel unit provided in an optional exemplary embodiment of this disclosure;

[0046] Figure 7 This is a schematic diagram of the circuit structure of a signal processing circuit provided in an exemplary embodiment of this disclosure;

[0047] Figure 8 This is a schematic diagram of the circuit structure of a signal processing circuit provided in another exemplary embodiment of this disclosure;

[0048] Figure 9 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed herein. Detailed Implementation

[0049] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0050] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0051] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0052] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0053] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0054] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0055] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0056] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0057] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0058] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0059] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0060] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0061] In developing this disclosure, the inventors discovered that synchronous reading of pixel units suffers from low time efficiency and fails to reflect the light intensity corresponding to each pixel unit. Asynchronous reading of pixel units, on the other hand, allows pixels to output signals when a threshold is reached, and then reset after outputting, directly proceeding to the next exposure. Asynchronous reading avoids the situation where pixels remain waiting after reaching the threshold, but for weaker light intensities, the triggering time for output is longer. In a pixel array, pixel units receiving strong light may have output signals many times, while pixel units receiving weak light may not output at all. This results in the image signal having abundant, even redundant, information in the strong light portion, while information in the weak light portion may be missing. Therefore, neither purely synchronous nor asynchronous output reading methods are perfect.

[0062] To address the technical problems of existing synchronous and asynchronous readout methods, this disclosure proposes the following sensor pixel unit.

[0063] Figure 1 This is a schematic diagram of the circuit structure of a sensor pixel unit provided in an exemplary embodiment of this disclosure. Figure 1 As shown, the sensor pixel unit (hereinafter referred to as the pixel unit) provided in this embodiment includes: an optical signal processing module 11, a signal conversion module 12, and a signal triggering module 13, which are composed of a photodiode 111, a first reset transistor 112, an auxiliary circuit 113, and a positive feedback unit 114.

[0064] One end of the photodiode 111 is grounded to GND, and the other end is connected to the drain terminal of the first reset transistor 112, the auxiliary circuit 113, and the positive feedback unit 114.

[0065] Photodiode 111 is used to receive light signals during the exposure time to generate a voltage signal Vpd. During the exposure cycle, in response to the voltage signal Vpd reaching a preset threshold, the voltage signal Vpd is output to the positive feedback unit 114. In response to the end of the exposure cycle, the voltage signal is output to the auxiliary circuit 113.

[0066] A photodiode is a photodetector that converts light into current or voltage signals depending on the application. The die typically uses a PN junction with photosensitive characteristics, making it highly sensitive to changes in light. It exhibits unidirectional conductivity, and its electrical properties change with varying light intensity. Therefore, the voltage or current in a circuit can be altered by utilizing the intensity of light.

[0067] The source terminal of the first reset transistor 112 is connected to the analog power supply signal AVDD, the drain terminal is connected to the other end of the photodiode 111, and the gate terminal receives the analog reset signal ARST.

[0068] The first reset transistor 112 is used to control the photodiode 111 to perform a reset according to the analog reset signal.

[0069] In this embodiment, the photodiode 111 is reset by turning the first reset transistor on or off. Optionally, the source terminal of the first reset transistor 112 is connected to the analog power supply signal AVDD, and the drain terminal is connected to the other end of the photodiode 112. The first reset transistor 112 is turned on or off according to the reset signal received at the gate terminal. When the first reset transistor 112 is turned on, the photodiode 111 is connected to the analog power supply signal AVDD, thereby resetting the photodiode 111.

[0070] Optionally, the first reset transistor is an N-type transistor, which turns on when the reset signal is high; alternatively, the first reset transistor is a P-type transistor, which turns on when the reset signal is low.

[0071] One end of the auxiliary circuit 113 is connected to the other end of the photodiode 111, and the other end serves as the second output terminal. When the exposure cycle is reached, the second output terminal is used to control the output of the second analog signal Vout according to the received voltage signal.

[0072] One end of the positive feedback unit 114 is connected to the other end of the photodiode 111, and the other end is connected to the signal conversion module as the first output terminal to convert the voltage signal into a first analog signal and output the first analog signal to the signal conversion module 12.

[0073] In this embodiment, in response to the voltage signal Vpd reaching a preset threshold, the voltage signal is input to the positive feedback unit 114. The positive feedback unit 114 converts the voltage signal into a first analog signal that is the same as the analog power supply signal. Furthermore, through the positive feedback provided by the positive feedback unit, the voltage signal input to the positive feedback unit can be quickly reduced to 0 level, so that the time when the voltage signal reaches the preset threshold can be more accurately located, thereby improving the accuracy of asynchronous reading.

[0074] The optical signal processing module 11 provided in this embodiment is located in the analog voltage domain and is used to receive optical signals to generate a voltage signal Vpd during the exposure time. In response to the voltage signal Vpd reaching a preset threshold, the first analog signal Vpd is sent to the signal conversion module 12 through the first output terminal; and when the exposure cycle is reached, the second analog signal Vout is output through the second output terminal.

[0075] Optionally, the voltage signal Vpd can be an analog voltage signal.

[0076] In some alternative embodiments, since the analog power supply voltage is typically much higher than the digital power supply voltage, in order for the components in the analog voltage domain to operate normally, the transistors included in the optical signal processing module and the signal conversion module may be high-voltage transistors; while the transistors in the digital voltage domain are low-voltage transistors. Low-voltage transistors have a smaller area, and by using low-voltage transistors, the area of ​​the pixel unit and the power consumption can be greatly reduced.

[0077] The main structure of the signal conversion module 11 in this embodiment may include a 3T structure (including 3 transistors) photosensitive unit and a positive feedback unit. The photosensitive unit outputs a first analog signal when the voltage signal Vpd generated based on the light signal reaches a preset threshold, enabling asynchronous reading of pixel units. This allows the light intensity of pixel units to be reflected by the duration of photogenerated charge accumulation under strong light conditions, avoiding situations where pixel units are still waiting after reaching the preset threshold. Simultaneously, for weak light conditions, the photosensitive unit provided in this embodiment outputs a second analog signal Vout when the exposure cycle is reached, enabling synchronous reading of pixel units and ensuring that signals with weak light intensity are output within one exposure cycle.

[0078] One end of the signal conversion module 12 is connected to the positive feedback unit 114, and the other end is connected to the signal trigger module 13. It is used to convert the first analog signal into a first digital signal and input the first digital signal into the signal trigger module 13.

[0079] In this embodiment, since there is a large difference between the voltage value in the analog voltage domain and the voltage value in the digital voltage domain, if the first analog signal is input into the signal triggering module 13, it may cause the output to fail. Therefore, this embodiment uses the signal conversion module 12 to convert the first analog signal into a first digital signal so that all signals processed in the signal triggering module 13 are digital signals.

[0080] The signal triggering module 13 is connected to the signal conversion module 12 and is used to send a read request signal and output a first digital signal according to the received permission signal.

[0081] In this embodiment, the output of the first digital signal is controlled by the signal triggering module based on the enable signal, thereby avoiding the problem of output errors caused by the simultaneous asynchronous output of multiple rows of pixel units in the pixel array of the sensor.

[0082] The sensor pixel unit, signal processing circuit, and electronic device provided in the above embodiments of this disclosure include: a photodiode, a first reset transistor, an auxiliary circuit, a positive feedback unit, a signal conversion module, and a signal triggering module; one end of the photodiode is grounded, and the other end is connected to the drain terminal of the reset transistor, the auxiliary circuit, and the positive feedback unit; the source terminal of the reset transistor is connected to an analog power supply signal, the drain terminal is connected to the other end of the photodiode, and the gate terminal receives an analog reset signal; one end of the positive feedback unit is connected to the other end of the photodiode, and the other end serves as a first output terminal connected to the signal conversion module; one end of the auxiliary circuit is connected to the other end of the photodiode, and the other end serves as a second output terminal; one end of the signal conversion module is connected to the positive feedback unit, and the other end is connected to the signal triggering module; the signal triggering module is connected to the signal conversion module. In this embodiment of the present disclosure, when the first analog signal reaches a preset threshold during the exposure cycle, a first digital signal is requested to be sent to achieve asynchronous reading of the pixel unit; and when the exposure cycle is reached, a second analog signal is output to achieve synchronous reading of the pixel unit; thus, a working mode combining synchronous and asynchronous reading of the pixel unit is achieved. While expressing the light intensity signal with strong light intensity through asynchronous reading, the output of the light intensity signal with weak light intensity is ensured during the exposure cycle through synchronous reading, thus combining the beneficial effects of synchronous and asynchronous reading.

[0083] Pulse sequence image sensors reflect the intensity of light signals (light intensity) by detecting the time required for photogenerated charges to accumulate to a certain threshold. The stronger the light signal, the shorter the time required for photogenerated charges to accumulate to the threshold. Within a certain frame period (exposure period), pixel units that reach the threshold ahead of time trigger asynchronous reading, while pixel units that have not reached the threshold after exposure are read synchronously. This approach balances the efficiency of light sensing and data transmission in both strong and weak light conditions. For asynchronous reading, the pixel unit only needs to output a 1-bit pulse signal representing the arrival of the threshold (corresponding to the first digital signal in this embodiment). For synchronous reading, the pixel unit needs to output an analog signal converted from all photogenerated charges accumulated during the exposure period (corresponding to the second analog signal in this embodiment). Generally, from a design simplicity perspective, all signals within the pixel period, including the output pulse signal and analog signal, operate in the analog voltage domain. A signal conversion module is then set around the pixel array to convert the analog voltage into a digital voltage. Furthermore, the power supply voltage in the analog voltage domain is usually much higher than that in the digital voltage domain. For a 1-bit pulse signal, the information can be fully expressed using a low-voltage digital voltage domain. Using an analog voltage for expression and transmission would instead lead to an increase in area and power consumption, as well as a decrease in speed. Therefore, in this embodiment, by adding a signal conversion module inside the pixel unit, the first analog signal asynchronously output by the optical signal processing module is converted into a first digital signal. This allows the pulse signal to be converted to the digital voltage domain in advance within the pixel unit, which can reduce the area and power consumption of the pixel unit and improve the transmission efficiency of the pulse signal.

[0084] Figure 2 This is a schematic diagram of the circuit structure of the optical signal processing module in a sensor pixel unit provided in another exemplary embodiment of this disclosure. Figure 2 As shown, the positive feedback unit 114 includes a first inverter 1141 and a pull-down transistor 1142.

[0085] The pull-down transistor 1142 is connected in parallel with the input and output terminals of the first inverter 1141 through its drain and gate terminals, and the source terminal of the pull-down transistor 1142 is grounded to GND.

[0086] In this embodiment, the drain terminal of the pull-down transistor 1142 receives a voltage signal. When the voltage signal reaches a preset threshold, it can be considered to be at a low level. This low-level signal is processed by the first inverter 1141 and converted into a high-level first analog signal. Since the first analog signal is connected to the gate terminal of the pull-down transistor 1142, the pull-down transistor 1142 is turned on, that is, the voltage signal is grounded, causing the voltage signal to drop to 0 level quickly. This allows for more accurate positioning of the time when the voltage signal drops to the preset threshold, thereby improving the sensitivity of the sensor using this pixel unit to strong light collection.

[0087] The first inverter 1141 converts the input voltage signal into an analog power signal, and uses the output terminal of the first inverter as the first output terminal to input the analog power signal into the signal conversion module 12.

[0088] Optionally, the first inverter 1141 includes two transistors, for example, a first positive feedback transistor and a second positive feedback transistor. The first positive feedback transistor is a P-type transistor. The gate terminals of the first and second positive feedback transistors are connected to serve as the input terminal of the first inverter. The drain terminal of the first positive feedback transistor is connected to the source terminal of the second positive feedback transistor to serve as the output terminal of the first inverter. The source terminal of the first positive feedback transistor is connected to the analog voltage signal. The second positive feedback transistor is an N-type transistor, and its drain is grounded. Therefore, when the voltage signal drops to a low level, the first positive feedback transistor is turned on. At this time, the analog voltage signal is output as the first analog signal to the signal conversion module.

[0089] like Figure 2 As shown, the auxiliary circuit 113 includes a source follower transistor 1131 and a readout transistor 1132;

[0090] The source terminal of the source follower transistor 1131 is connected to the analog power supply signal AVDD, the gate terminal is connected to the other end of the photodiode 111, the drain terminal of the first reset transistor 112 and the positive feedback unit 114, and the drain terminal is connected to the drain terminal of the readout transistor 1132.

[0091] When the voltage signal output by the photodiode is high, the source follower transistor 1131 is turned on, and generates a corresponding analog voltage signal following the change of the voltage signal. When the readout transistor is turned on, the analog voltage signal is output as the second analog signal Vout.

[0092] The drain terminal of the readout transistor 1132 is connected to the drain terminal of the source follower transistor 1131. The gate terminal receives the readout signal Read (a second analog signal is output when the exposure cycle is reached by controlling the timing of the readout signal), and the source terminal serves as the second output terminal.

[0093] Optionally, the source follower transistor 1131 and the readout transistor 1132 are typically N-type transistors that are turned on when the gate receives a high level.

[0094] In the embodiments provided in this disclosure, since the voltage values ​​in the analog voltage domain are typically significantly higher than those in the digital voltage domain, low-voltage transistors cannot withstand the voltages in the analog voltage domain, while high-voltage transistors have thicker gate oxide layers and can withstand higher analog domain voltages. Therefore, optionally, the first reset transistor, pull-down transistor, source follower transistor, readout transistor included in the analog voltage domain, and the two transistors (e.g., the first positive feedback transistor and the second positive feedback transistor) included in the first inverter are high-voltage transistors. Furthermore, because the gate oxide layer of high-voltage transistors is thicker, the area of ​​the high-voltage transistor is larger, and the current and power consumption are also larger. Therefore, low-voltage transistors are used in the signal triggering module to reduce the overall area occupied by the pixel unit.

[0095] Figure 3 This is a schematic diagram of the circuit structure of the signal conversion module in a sensor pixel unit provided in another exemplary embodiment of this disclosure. For example... Figure 3 As shown, the signal conversion module 12 provided in this embodiment includes a second inverter composed of a first conversion transistor 121 and a second conversion transistor 122.

[0096] The gate terminal of the first switching transistor 121 is connected to the gate terminal of the second switching transistor 122 as the input terminal of the second inverter, and the drain terminal of the first switching transistor 121 is connected to the source terminal of the second switching transistor 122 as the output terminal of the second inverter; the source terminal of the first switching transistor 121 is connected to the digital power signal DVDD, and the drain terminal of the second switching transistor 122 is grounded.

[0097] Optionally, the first conversion transistor is a P-type transistor, with its source terminal connected to the digital voltage signal DVDD; the second conversion transistor is an N-type transistor, with its drain grounded. Therefore, when the voltage signal generated by the photodiode drops to a low level, the optical signal processing module outputs a high-level first analog signal through its first output terminal. At this time, the second conversion transistor is turned on, and the converted first digital signal is a low-level digital signal. Conversely, when the voltage signal generated by the photodiode is high (e.g., an analog reset signal), the first analog signal is low, and the first conversion transistor is turned on, outputting the digital voltage signal DVDD (high level) to the signal trigger module. Thus, all signals input to the signal trigger module are digital signals, achieving analog-to-digital signal conversion.

[0098] Optionally, since the signal input to the signal conversion module is an analog signal, if a low-voltage transistor is used in the signal conversion module, the signal conversion module will not be able to operate normally. Therefore, in this embodiment, the first conversion transistor and the second conversion transistor are high-voltage transistors.

[0099] In some optional embodiments, within one exposure cycle, the voltage signal output by the photodiode starts to decrease from the reset signal. When it decreases to a preset threshold, the voltage signal is processed and converted from analog to digital by a first inverter and a second inverter connected in series to obtain a low-voltage first digital signal. The level of the first digital signal is consistent with that of the voltage signal. When the voltage signal is a high-level analog signal, the first digital signal is a high-level digital signal; when the voltage signal is a low-level analog signal, the first digital signal is a low-level digital signal.

[0100] Figure 4 This is a schematic diagram of the circuit structure of the signal triggering module in a sensor pixel unit provided in another exemplary embodiment of this disclosure. Figure 4 As shown, the signal triggering module 13 includes: a pulse output transistor 131, an enable transistor 132, a request transistor 133, and a pulse latch unit 134.

[0101] The drain terminal of the pulse output transistor 131 is connected to the signal conversion module 12, the gate terminal of the request transistor 133, and the pulse latch unit 134. The gate terminal is connected to the enable signal Ack, and the source terminal serves as the third output terminal. The first digital signal Vspi is output according to the control of the enable signal Ack.

[0102] Optionally, in this embodiment, the conduction status of the pulse output transistor 131 determines whether to output the first digital signal Vspi. Only when a high-level enable signal Ack is received is the pulse output transistor 131 turned on, connecting the third output terminal to the output terminal of the second inverter, thereby enabling the output of the first digital signal through the third output terminal. Before receiving the enable signal Ack, the pulse output transistor 131 is in a normally off state and cannot output the first digital signal.

[0103] The drain terminal of enable transistor 132 is connected to the digital power signal DVDD, the source terminal is connected to the source terminal of request transistor 133, and the gate terminal is connected to pulse latch unit 134. When the second digital signal latched by pulse latch unit 134 is high, enable transistor 132 is turned on.

[0104] The source terminal of the request transistor 133 is connected to the source terminal of the enable transistor 132, the gate terminal is connected to the signal conversion module 12, and the drain terminal serves as the fourth output terminal; in response to the first digital signal being low and the enable transistor 132 being turned on, the read request signal Req is output through the fourth output terminal.

[0105] In this embodiment, the enable transistor 132 and the request transistor 133 together form a connection path from the digital power signal DVDD to the fourth output terminal. A high-level read request signal Req is output from the fourth output terminal only when both the enable transistor 132 and the request transistor 133 are simultaneously turned on. Whether the enable transistor 132 is turned on is determined by the second digital signal latched by the pulse latch unit 134, while whether the request transistor 133 is turned on is determined by the first digital signal obtained by processing the voltage signal. Optionally, both the enable transistor 132 and the request transistor 133 are P-type transistors, meaning they are turned on when the signal input to the gate is low. The external circuit feeds back a high-level enable signal Ack based on the high-level read request signal Req. This enable signal Ack turns on the pulse output transistor 131, at which time the first digital signal Vspi is output through the third output terminal.

[0106] The pulse latch unit 134 is connected to the signal conversion module 12 and the enable transistor 132, and is used to latch the second digital signal according to the control of the digital reset signal. When the second digital signal is high, the enable transistor 132 is turned on; when an over-allowed signal is received within an exposure cycle, the enable transistor 132 is turned off.

[0107] This embodiment controls the output of only one first digital signal asynchronously within one exposure cycle through a pulse latch unit. Once an enable signal has been received within one exposure cycle, the enable transistor 132 is turned off by the pulse latch unit 134, meaning that a read request signal cannot be issued. The embodiment provided in this case controls the pixel unit to output only one first digital signal asynchronously within one exposure cycle through the control of the pulse latch unit, reducing the frequency difference between synchronous and asynchronous outputs in the pixel unit. This avoids the problem of information redundancy in the strong light part caused by too many asynchronous read output signals under strong light conditions.

[0108] Figure 5 This is a schematic diagram of the circuit structure of the signal triggering module in a sensor pixel unit provided in another exemplary embodiment of this disclosure. For example... Figure 5 As shown, the pulse latch unit 134 includes: a second reset transistor 1341, a third inverter 1342, a trigger-stop transistor 1343, and a request-enable transistor 1344;

[0109] The source terminal of the second reset transistor 1341 is connected to the digital power supply signal DVDD, the drain terminal is connected as a latch point to the source terminal of the trigger-stop transistor 1343 and the source terminal of the request-enable transistor 1344, and the gate terminal receives the digital reset signal DRST.

[0110] The request allows the source terminal of transistor 1344 to be connected to the latch point, the drain terminal to be connected to the signal conversion module 12, and the gate terminal to receive the enable signal Ack; the first digital signal is written to the latch point according to the control of the enable signal.

[0111] In response to a high-level enable signal received from an external circuit, the enable transistor 1344 is turned on. At this time, the first digital signal is written to the latch point. When the first digital signal is low, the second digital signal latched by the latch point is changed to a low voltage. After being processed by the third inverter, the enable transistor 132 is turned off, that is, the read request signal cannot be issued. This achieves the technical effect that asynchronous reading cannot be performed after receiving the enable signal.

[0112] The input terminal of the third inverter 1342 is connected to the latch point, and the output terminal is connected to the gate terminal of the enable transistor 132. It is used to invert the second digital signal latched by the latch point and input it to the gate terminal of the enable transistor 132 to control whether the enable transistor 132 is turned on.

[0113] The trigger-stop transistor 1343 is connected in parallel with the third inverter 1342 through its source and gate terminals, and its drain terminal is grounded. It is used to ground the latch point when the output of the third inverter 1342 is high.

[0114] When the trigger-stop transistor 1343 provided in this embodiment is turned on, it grounds the latch point, keeping the signal at the latch point at a low voltage. The low level of the latch point is processed by the third inverter to become a high level. This high-level signal input keeps the gate of the trigger-stop transistor 1343 on, forming a cycle in which the second digital signal of the latch point remains at a low level. Correspondingly, the enable transistor remains off. Before the second reset transistor 1341 (next exposure cycle) receives the next digital reset signal, the signal trigger module cannot issue a read request signal. That is, only one first data signal can be issued in one exposure cycle.

[0115] Optionally, the third inverter 1342 may include: a first latch transistor and a second latch transistor;

[0116] The gate of the first latch transistor is connected to the gate of the second latch transistor as the input of the third inverter. The source of the first latch transistor is connected to the drain of the second latch transistor as the output of the third inverter. The drain of the first latch transistor is connected to the digital power signal DVDD, and the source of the second latch transistor is grounded.

[0117] Optionally, the first latching transistor is a P-type transistor, and its drain is connected to the digital power signal DVDD; the second latching transistor is an N-type transistor, and its source is grounded. Therefore, when the second digital signal output at the latch point is low, the first latching transistor is turned on, the third inverter outputs a high-level digital power signal, and the enable transistor, being an N-type transistor, is turned off when its gate receives a high-level signal. Conversely, when the second digital signal output at the latch point is high, the second latching transistor is turned on, the third inverter outputs a low-level signal, and even if the gate of the enable transistor is grounded, the enable transistor is turned on.

[0118] In the embodiments provided in this disclosure, the high-voltage transistor has a thicker gate oxide layer, enabling it to withstand higher analog domain voltages. However, due to the thicker gate oxide layer, the high-voltage transistor has a larger area, and its current and power consumption are also higher. Therefore, to reduce the area and power consumption of the pixel unit, the pulse output transistor, enable transistor, request transistor, second reset transistor, trigger termination transistor, request enable transistor in the signal triggering module of this embodiment, as well as the two transistors (first latch transistor and second latch transistor) included in the third inverter, are all low-voltage transistors. Low-voltage transistors have a thinner gate oxide layer, can only withstand lower digital domain voltages, and have smaller area, current, and power consumption, as well as faster voltage switching speed. By using low-voltage transistors in the signal triggering module, the area and power consumption of the pixel unit are effectively reduced.

[0119] Figure 6 This is a schematic diagram of the circuit structure of a sensor pixel unit provided in an optional exemplary embodiment of this disclosure. The figure shows the specific structure of the pixel unit, including the optical signal processing module 11, the signal conversion module 12, and the signal triggering module 13.

[0120] The optical signal processing module 11 includes: a photodiode 111, a first reset transistor 112, a source follower transistor 1131 and a readout transistor 1132, as well as a first inverter 1141 (including a first positive feedback transistor and a second positive feedback transistor) and a pull-down transistor 1142.

[0121] The signal conversion module 12 includes a second inverter composed of a first conversion transistor 121 and a second conversion transistor 122.

[0122] The signal triggering module 13 includes: a pulse output transistor 131, an enable transistor 132, a request transistor 133, and a pulse latch unit 134. The pulse latch unit 134 includes: a second reset transistor 1341, a third inverter 1342 (combining a first latch transistor and a second latch transistor), a trigger termination transistor 1343, and a request enable transistor 1344.

[0123] The connection relationships of the various components in this embodiment can be referred to the description and accompanying drawings of the above embodiment.

[0124] Optionally, in one exposure cycle of a pixel unit: First, a reset phase is entered. During the reset phase, a low-level analog reset signal ARST and a digital reset signal DRST are provided to the pixel unit through an external circuit, turning on the first and second reset transistors. The voltage signal Vpd corresponding to the photodiode is reset to the analog power supply signal AVDD, and the second digital signal Req_EN corresponding to the latch point is reset to the digital power supply signal DVDD. After the reset is completed, the timing of the analog reset signal ARST and the digital reset signal DRST is pulled high (e.g., AVDD and DVDD), and the first and second reset transistors are turned off, entering the exposure phase.

[0125] During the exposure stage, the photodiode converts the light signal into photogenerated charge, and the voltage signal Vpd decreases as the photogenerated charge accumulates. The stronger the light signal received by the pixel unit, the faster the photogenerated charge accumulates. When the light intensity exceeds a certain range, Vpd will decrease to a specific threshold (preset threshold) before the end of exposure. When this specific threshold is reached, the first positive feedback transistor turns on, causing the voltage output of the first inverter to gradually rise, which in turn turns on the pull-down transistor. The pull-down transistor accelerates the decrease in voltage signal, which in turn promotes the conduction of the first positive feedback transistor, thus forming positive feedback and accelerating the pull-down of the voltage signal Vpd to 0 level, while the first analog signal output by the first inverter is pulled to AVDD. The high-level first analog signal is input to the signal conversion module, turning on the second conversion transistor 122, making the first digital signal output by the second inverter low level. This low-level first digital signal is then input to the request transistor, turning on the request transistor. Since the previous reset process has reset the second digital signal Req_EN to a high level, the enable transistor remains on. Therefore, when Vpd drops to the preset threshold, the pixel unit will pull the read request signal Req high to DVDD, sending this high-level read request signal Req to the external circuit. Because the actual read time of each pixel unit during asynchronous readout is uncertain, and multiple pixel units (a row of pixel units in the pixel array) share a single signal output line, the external circuit needs to confirm the read request signal of the pixel unit. The external circuit determines the current output priority and confirms the pixel unit corresponding to the highest priority read request signal. Therefore, after outputting the high-level Req signal, the pixel unit must wait for the external circuit to send a high-level enable signal Ack to the pixel unit before the pulse output transistor will turn on, thus outputting the first digital signal Req_N through the third output terminal. Simultaneously with signal output, the request enable transistor is also turned on due to the enable signal Ack rising to a high level. For the pixel unit that issued the request and received the enable signal, the turn-on request enable transistor pulls the second digital signal Req_EN low, thus turning off the enable transistor. Furthermore, since the second digital signal is low, it triggers the termination transistor to turn on, keeping the second digital signal latched at a low level. Afterward, the pixel unit cannot issue another request signal until the reset phase of the next exposure cycle arrives. When the exposure time ends, the pixel unit performs a synchronous readout. At this time, the external circuit provides the pixel unit with a high-level readout signal Read, turning on the readout transistor. The voltage signal Vpd corresponding to the photogenerated charge accumulated throughout the complete exposure cycle is read out through the source follower transistor and the readout transistor, and the second analog signal Vout is output through the second output terminal. After the synchronous readout ends, a complete exposure cycle is completed, and the cycle continues to the next exposure cycle for continuous imaging.

[0126] The sensor pixel units provided in any of the above embodiments can form a pixel array. In some optional examples, by combining auxiliary circuits with the functions of the pixel array, synchronous and asynchronous reading of the sensor pixel units can be achieved. For example, Figure 7 This is a schematic diagram of the circuit structure of a signal processing circuit provided in an exemplary embodiment of this disclosure. For example... Figure 7 As shown, the signal processing circuit provided in this embodiment includes: a pixel array 71 composed of n rows * m columns of sensor pixel units 711 (hereinafter referred to as pixel units) provided in any of the above embodiments, a row drive control module 72, a row arbitration module 73 and a column readout module 74; n and m are integers greater than or equal to 1.

[0127] The row drive control module 72 is used to provide analog reset signals, digital reset signals and readout signals to the sensor pixel units 711 in the pixel array 71 row by row.

[0128] In this embodiment, the row drive control module 72 provides each row of sensor pixel units 711 in the pixel array with an analog reset signal ARST, a digital reset signal DRST, and a readout signal Read, corresponding to the corresponding period, row by row, according to the exposure cycle. Typically, the analog reset signal ARST and the digital reset signal DRST are given a low level at the beginning of the exposure cycle (high level at other times), and the readout signal Read is given a high level at the end of the exposure cycle (low level at other times).

[0129] The pixel array 71 is used to perform a reset according to the analog reset signal and the digital reset signal. During the exposure cycle, in response to the first analog signal reaching a preset threshold, it sends a read request signal to the row arbitration module 73 and sends a first digital signal to the column readout module 74 under the control of the allow signal fed back by the row arbitration module 73. When the exposure cycle is reached, it sends a second analog signal to the column readout module under the control of the transfer signal and the readout signal.

[0130] The first digital signal is determined based on the first analog signal. Optionally, the first analog signal conversion module processes the signal to obtain the processed first digital signal.

[0131] Optionally, the sensor pixel units 711 in the pixel array output a first digital signal and a second analog signal row by row according to the control of the row drive control module 72.

[0132] The arbitration module 73 is used to receive the read request signal Req sent by at least one row of sensor pixel units 711 in the pixel array 71, and to send back the enable signal Ack to at least one row of sensor pixel units in the order of receiving the read request signal.

[0133] In this embodiment, the row arbitration module 73 receives a read request signal from the row sensor pixel unit 711 each time. When more than one read request signal is received, the multiple read request signals Req can be sorted according to the receiving time and processed in sequence, with the read request signal received first being processed first.

[0134] The column readout module 74 is used to receive a first digital signal and a second analog signal sent by at least one column of sensor pixel units 711.

[0135] Optionally, the column readout module receives the first digital signal and the second analog signal sent by the sensor pixel unit 711 column by column. In this embodiment, the column readout module achieves both synchronous and asynchronous reading of the sensor pixel units, thus realizing the beneficial effects of both synchronous and asynchronous reading.

[0136] The circuit structures of the row drive control module 72, row arbitration module 73 and column readout module 74 involved in this embodiment can all adopt common circuit structures in the prior art. This disclosure does not limit the specific circuit structures of the row drive control module 72, row arbitration module 73 and column readout module 74.

[0137] Figure 8 This is a schematic diagram of the circuit structure of a signal processing circuit provided in another exemplary embodiment of this disclosure. For example... Figure 8 As shown, the signal processing circuit provided in this embodiment further includes: a row address encoder 75 and a clock module 76;

[0138] When the row arbitration module 73 sends an enable signal to the row sensor pixel unit 711, the row address encoder 75 encodes the row information of the sensor pixel unit 711 that receives the enable signal into a row address (Row addr).

[0139] In this embodiment, the circuit structure of the row address encoder can be any existing circuit structure that can implement address encoding, and the encoding method can be any existing encoding method. The encoded row address represents the row where the pixel unit that outputs the first digital signal is located.

[0140] The clock module 76 is used to record the time information (Timestamp) of the row address generated by the row address encoder 75, and associate the time information with the row address.

[0141] In this embodiment, the clock module can be any existing module that can provide time information. The time information is associated with the row address, that is, each row address corresponds to unique time information, so as to distinguish different row addresses.

[0142] like Figure 8As shown, the column readout module 74 includes: m analog-to-digital converters 741, m column buffers 742, and column address encoders 743.

[0143] Each analog-to-digital converter 741 corresponds to a column of sensor pixel units 711, and each column buffer 742 corresponds to a column of sensor pixel units 711; each analog-to-digital converter 741 corresponds to a column buffer 742.

[0144] The column buffer 742 is used to store the first digital signal Vspi output by the sensor pixel unit 711 of the corresponding column and transmit the first digital signal to the column address encoder 743.

[0145] Since the first digital signal output by the sensor pixel unit 711 in this embodiment is read asynchronously and the output time is not when the exposure cycle is reached, and different sensor pixel units output the first digital signal at different times, the first digital signal is stored in the column buffer 742 after the first digital signal is received.

[0146] The column address encoder 743 is used to receive the first digital signal output by the column buffer 742, encode the column information corresponding to the first digital signal into a column address, and associate the column address with the row address based on time information to determine the sensor pixel unit corresponding to the first digital signal.

[0147] After receiving and storing the first digital signal, since the column readout module reads out one column of pixel units at a time, only the column address corresponding to the first digital signal can be determined when the first digital signal is obtained. Therefore, to determine the specific location of the pixel unit corresponding to the first digital signal and thus the illumination intensity of the pixel unit at that specific location, this embodiment associates the time information of the obtained first digital signal with the row address and its corresponding time information based on time. Row addresses and column addresses with the same time information (moment) are mapped to obtain the specific location of the pixel unit corresponding to the first digital signal of that time information (row address and column address determine a unique location). Based on the location and time corresponding to the first digital signal, the illumination intensity corresponding to each pixel unit in the pixel array can be determined. Optionally, the shorter the time information of the output first digital signal relative to the reset time interval, the greater the illumination intensity corresponding to that location.

[0148] The analog-to-digital converter 741 is used to receive the second analog signal Vout output by the sensor pixel unit of the corresponding column, perform differential operation on the two consecutively received second analog signals Vout, and perform analog-to-digital conversion on the result of the differential operation to obtain a third digital signal.

[0149] In this embodiment, the second analog signal is associated with the voltage signal output by the photodiode and is correlated with the voltage signal that reflects the accumulated photogenerated charge of the photodiode. It can be understood that the second analog signal is equal to the voltage signal, which can determine the voltage difference between before and after the photodiode receives light and generates photogenerated charge during the exposure cycle. In other words, it determines the amount of photogenerated charge generated by the photodiode based on the received light. Therefore, in this embodiment, differential operation and analog-to-digital conversion are performed on the two second analog signals in the analog-to-digital converter to determine the synchronously output third digital signal.

[0150] like Figure 8 As shown, the signal processing circuit provided in this embodiment also includes a conversion interface circuit 77.

[0151] The conversion interface circuit 77 is used to receive the signal output by the column readout module 74.

[0152] In this embodiment, after the signal processing circuit obtains the first digital signal and the third digital signal, in order to facilitate the processing and / or use of the first digital signal and the third digital signal by other devices or circuits, this embodiment receives the signal output by the column readout module through a conversion interface circuit and provides an interface to connect with external circuits or devices.

[0153] In the operation of the signal processing circuit provided in this embodiment, the circuit first enters a reset phase. A low-level analog reset signal ARST and a digital reset signal DRST are provided by the row drive control module. ARST controls the clearing of photogenerated charge on the photodiode in the pixel unit, and DRST resets the second digital signal Req_EN in the pulse latch unit of the pixel unit to a high level. After the reset is completed, the exposure phase begins, and the photodiode starts to be exposed, accumulating photogenerated charge. During the exposure cycle, different pixel units receive different light intensities. Pixel units receiving stronger light reach a preset threshold within the exposure cycle, and the voltage signal generated by the photodiode is low, triggering asynchronous output. The pixel unit triggering asynchronous output first enters a trigger request phase. A first analog signal is input to the signal conversion module, obtaining a processed first digital signal that turns on the request transistor. At this time, since the second digital signal is high, the enable transistor also turns on. Therefore, the drain of the request transistor pulls the read request signal Req of the corresponding row to a high level, sending the read request signal Req to the row arbitration circuit. The row arbitration module determines the priority of the row containing the currently requesting pixel unit and sends an allow signal (Ack) to the pixel unit in the row with the highest priority. Priority is determined by the arrival time of the read request signal (Req); signals arriving earlier are given the allow signal first. The first digital signal (Vspi) of the allowed output pixel unit in a given row is sent to the column buffer. The row address encoder, column address encoder, and clock module record and read the current time, the currently allowed row address, and the column addresses of all pixel units in that row that have reached a preset threshold, determining the specific address of the asynchronously read pixel unit. After the exposure time (exposure cycle) ends, the pixel unit enters the synchronous readout stage. First, the second photodiode is reset, and the second analog signal (Vout) is read out and sent to the analog-to-digital converter. After all signals are read out, one frame cycle is completed. This cycle is repeated to achieve continuous imaging.

[0154] The signal processing circuit provided in this disclosure can be integrated into one or more chips. In one optional example, the signal processing circuit is integrated into a single chip. This chip mainly includes a pixel array 71, a row drive control module 72, a row arbitration module 73, a row address encoder 75, a column readout module 74, a clock module 76, and a conversion interface circuit 77. The row drive control module 72, row arbitration module 73, row address encoder 75, column readout module 74, clock module 76, and conversion interface circuit 77 are all prior art; therefore, their detailed implementation methods are not described in detail in this embodiment, only their logical functions in this disclosure are described. The pixel array is composed of n rows and m columns of pixel units provided in the above embodiments. The row drive control module is used to output the signal timing of the analog reset signal ARST, digital reset signal DRST, and readout signal Read for all row pixel units. The row arbitration module is used to receive the read request signal Req output by all row pixel units and output an enable signal Ack for the row pixel unit with the highest current output priority. All row enable signals (Ack) are simultaneously output to the row address encoder. The row address encoder encodes the specific position of the currently enabled row pixel unit into a row address (Row addr) and outputs it, while simultaneously controlling the clock module to output the current time (Timestamp). The column readout module mainly includes m column-level analog-to-digital converters (ADCs), an mbit column buffer, and a column address encoder. When the Read signal of a row pixel unit is high (outputting the second analog signal), the row pixel unit outputs the second analog signal Vout to the corresponding column's ADC for analog-to-digital conversion. When a row pixel unit receives an enable signal (high level), the first digital signal Vspi (pulse signal) of that row pixel unit is input to the corresponding column buffer. The column address encoder encodes the position of the first digital signal in the column buffer and outputs it to the conversion interface circuit. The ADC outputs the result to the conversion interface circuit after each analog-to-digital conversion. For weak light signals, the digital signal converted from the photogenerated charge signal accumulated within an exposure cycle can reflect the specific light intensity; for strong light signals, the moment when the photogenerated charge signal accumulates to a threshold can reflect the specific light intensity.

[0155] In addition, this disclosure also provides an electronic device, including:

[0156] Memory, used to store computer programs;

[0157] A processor is configured to execute a computer program stored in the memory, and when the computer program is executed, to implement the sensor pixel unit or signal processing circuit described in any of the above embodiments of the present disclosure.

[0158] The electronic devices provided in this disclosure can be included in any of the following: image data acquisition devices, audio / video players, navigation devices, entertainment devices, communication devices, roadside traffic facilities, devices in motor vehicles, industrial testing equipment, flight equipment, medical devices, security equipment, etc.

[0159] The electronic equipment provided in this disclosure can be applied to any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial testing equipment, flight equipment, medical equipment, security equipment, etc.

[0160] Figure 9 This is a schematic diagram illustrating the structure of an application embodiment of the electronic device disclosed herein. Below, reference is made to… Figure 9 This describes an electronic device according to embodiments of the present disclosure. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0161] like Figure 9 As shown, the electronic device includes one or more processors and memory.

[0162] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0163] The memory can store one or more computer program products, and the memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage medium, and the processor can run the computer program products to implement the sensor pixel units or signal processing circuits of the various embodiments of this disclosure described above, and / or other desired functions.

[0164] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0165] In addition, the input device may also include, for example, a keyboard, a mouse, etc.

[0166] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0167] Of course, for the sake of simplicity, Figure 9 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0168] In addition to the methods and devices described above, embodiments of this disclosure may also be computer program products, including computer program instructions that, when executed by a processor, cause the processor to perform sensor pixel units or signal processing circuits according to various embodiments of this disclosure as described in the foregoing portion of this specification.

[0169] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0170] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to execute sensor pixel units or signal processing circuits according to various embodiments of this disclosure as described in the foregoing portion of this specification.

[0171] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0172] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0173] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0174] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0175] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0176] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0177] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0178] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A sensor pixel unit, characterized in that, include: Photodiode, first reset transistor, auxiliary circuit, positive feedback unit, signal conversion module, and signal triggering module; One end of the photodiode is grounded, and the other end is connected to the drain terminal of the reset transistor, the auxiliary circuit, and the positive feedback unit. The source terminal of the reset transistor is connected to the analog power supply signal, the drain terminal is connected to the other end of the photodiode, and the gate terminal receives the analog reset signal. One end of the positive feedback unit is connected to the other end of the photodiode, and the other end is connected to the signal conversion module as the first output terminal. One end of the auxiliary circuit is connected to the other end of the photodiode, and the other end serves as the second output terminal. One end of the signal conversion module is connected to the positive feedback unit, and the other end is connected to the signal triggering module; The signal triggering module is connected to the signal conversion module.

2. The pixel unit according to claim 1, characterized in that, The positive feedback unit includes a first inverter and a pull-down transistor; The pull-down transistor is connected in parallel with the input and output terminals of the first inverter through its drain and gate terminals, and the source terminal of the pull-down transistor is grounded. The first inverter converts the input voltage signal into an analog power signal, and uses the output terminal of the first inverter as the first output terminal to input the analog power signal into the signal conversion module.

3. The pixel unit according to claim 2, characterized in that, The auxiliary circuit includes a source follower transistor and a readout transistor; The source terminal of the source follower transistor is connected to the analog power supply signal, the gate terminal is connected to the other end of the photodiode, the drain terminal of the reset transistor and the positive feedback unit, and the drain terminal is connected to the drain terminal of the readout transistor. The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the gate terminal receives the readout signal, and the source terminal serves as the second output terminal.

4. The pixel unit according to claim 3, characterized in that, The first reset transistor, the pull-down transistor, the source follower transistor, the readout transistor, and the two transistors included in the first inverter are high-voltage transistors.

5. The pixel unit according to any one of claims 1-4, characterized in that, The signal conversion module includes: a second inverter composed of a first conversion transistor and a second conversion transistor; The gate terminal of the first conversion transistor is connected to the gate terminal of the second conversion transistor as the input terminal of the second inverter, and the drain terminal of the first conversion transistor is connected to the source terminal of the second conversion transistor as the output terminal of the second inverter; the source terminal of the first conversion transistor is connected to the digital power supply signal, and the drain terminal of the second conversion transistor is grounded.

6. The pixel unit according to claim 5, characterized in that, The first switching transistor and the second switching transistor are high-voltage transistors.

7. The pixel unit according to any one of claims 1-4, characterized in that, The signal triggering module includes: a pulse output transistor, an enable transistor, a request transistor, and a pulse latch unit; The drain terminal of the pulse output transistor is connected to the signal conversion module, the gate terminal of the request transistor, and the pulse latch unit. The gate terminal is connected to the enable signal, and the source terminal serves as the third output terminal. The drain terminal of the enable transistor is connected to the digital power signal, the source terminal is connected to the source terminal of the request transistor, and the gate terminal is connected to the pulse latch unit. The source terminal of the request transistor is connected to the source terminal of the enable transistor, the gate terminal is connected to the signal conversion module, and the drain terminal serves as the fourth output terminal. The pulse latch unit is connected to the signal conversion module and the gate terminal of the enable transistor.

8. The pixel unit according to claim 7, characterized in that, The pulse latch unit includes: a second reset transistor, a third inverter, a trigger-stop transistor, and a request-enable transistor; The source terminal of the second reset transistor is connected to the digital power supply signal, the drain terminal is connected as a latch point to the source terminal of the trigger-stop transistor and the source terminal of the request-allow transistor, and the gate terminal receives the digital reset signal. The request allows the source terminal of the transistor to be connected to the latch point, the drain terminal to be connected to the signal conversion module, and the gate terminal to receive the enable signal; The input terminal of the third inverter is connected to the latch point, and the output terminal is connected to the gate terminal of the enable transistor. The trigger-stop transistor is connected in parallel with the third inverter through its source and gate terminals, and its drain terminal is grounded.

9. The pixel unit according to claim 8, characterized in that, The pulse output transistor, enable transistor, request transistor, second reset transistor, trigger termination transistor, request enable transistor in the signal triggering module, and the transistors included in the third inverter are all low-voltage transistors.

10. An electronic device, characterized in that, Includes: a processor, and a memory communicatively connected to the processor, and further includes the sensor pixel unit according to any one of claims 1-9; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to control the sensor pixel units.

11. The device according to claim 10, characterized in that, The electronic device is included in any of the following: image data acquisition device, audio / video player, navigation device, entertainment device, communication device, roadside traffic facility, device in motor vehicle, industrial testing device, flight equipment, medical device, security device.

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