Chip stacking packaging structure and packaging product
By creating grooves on the substrate and redistributing I/O terminals using a redistribution layer, combined with TSV through-hole technology, the problem of excessively large package size was solved, enabling a compact and thin design for chip stacking.
Patent Information
- Application Number
- CN202423192048.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2034-12-23
AI Technical Summary
In existing wire bonding stacking structures, as the number of chips increases, the package size becomes larger, making it difficult to achieve thinning and miniaturization of multiple chips.
The design employs a recessed structure and a redistribution layer. By creating recesses on the substrate to mount the chip and redistributing the I/O terminals using the redistribution layer, the package height is reduced. Combined with TSV through-hole technology, vertical interconnection is achieved, eliminating the need for wire bonding space.
It achieves a compact structure of multiple chips, reduces the overall package height, supports miniaturization and thin design, and can reduce chip thickness by 75%, resulting in a significant reduction in package size.
Smart Images
Figure CN223624976U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a chip stacking packaging structure and packaging product. Background Technology
[0002] As electronic products become increasingly integrated, the requirements for package size also become more stringent, necessitating a trend towards miniaturization and thinning of the overall packaging structure. This is especially true for memory chips, where stacking capacities inevitably occupies additional package volume.
[0003] In current wire bonding stacking structures, sufficient space needs to be reserved for wire bonding for each additional chip added in the height direction. As the number of stacked chips increases and the height increases, the wiring becomes more complex, requiring more space to accommodate the wires, resulting in a larger overall package size. Furthermore, to ensure effective electrical isolation and interconnection, appropriate safety spacing must be maintained between pads of adjacent chips and between leads, which also increases the package size.
[0004] Therefore, how to achieve a thinner and smaller stacked structure of multiple chips is a technical problem that the industry urgently needs to solve. Utility Model Content
[0005] The purpose of this invention is to provide a chip stacking packaging structure and packaging product that can reduce the overall packaging height and packaging volume, which is conducive to achieving miniaturized packaging.
[0006] In a first aspect, this utility model provides a chip stacking packaging structure, comprising:
[0007] The substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction, the first surface having a groove; the bottom of the groove having a first pad.
[0008] A stacked chip, comprising a plurality of chips stacked sequentially along the thickness direction, wherein the surface of the stacked chip is provided with connection bumps, and each chip is electrically connected to the connection bumps;
[0009] The stacked chip is disposed in the groove, with the side of the stacked chip having the connecting bump facing the bottom of the groove, and the connecting bump being electrically connected to the first pad;
[0010] A redistribution layer is disposed on the second surface and is electrically connected to the first pad.
[0011] An insulating layer that covers the redistribution layer;
[0012] The second pad is electrically connected to the redistribution layer on the side away from the first pad, and the second pad is exposed from the insulating layer.
[0013] In an optional implementation, one side of the first pad is connected to the connection bump, and the other side is connected to the redistribution layer.
[0014] In an optional embodiment, the insulating layer has an opening that exposes the redistribution layer, and the second pad is disposed in the opening.
[0015] In an optional implementation, a first conductive post connected to the redistribution layer is further included, the first conductive post extending to the first surface; the first conductive post is electrically connected to the stacked chip.
[0016] In an optional embodiment, the stacked chip has a third pad on the side away from the connection bump, and the third pad is electrically connected to the first conductive post.
[0017] In an optional embodiment, a conductive lead is further included, wherein a fourth pad is formed at one end of the first conductive post extending to the first surface, and the two ends of the conductive lead are respectively connected to the third pad and the fourth pad.
[0018] In an optional embodiment, the stacked chips include a first chip, a second chip, and a second conductive post electrically connecting the first chip and the second chip, the second conductive post being electrically connected to the connection bump.
[0019] In an optional embodiment, the thickness of the chip stacked package structure is H, where H = H1 + H2 - D; and H1 is the thickness of the substrate, H2 is the thickness of the stacked chip, and D is the depth of the groove.
[0020] In an optional embodiment, a molding compound is further included, disposed on the first surface, to encapsulate the stacked chips.
[0021] Secondly, this utility model provides a packaging product, including the chip stacking packaging structure described in any of the foregoing embodiments.
[0022] The beneficial effects of the chip stacking packaging structure and packaging product provided by this utility model include:
[0023] The chip stacking packaging structure provided by this utility model involves multiple chips being stacked sequentially and electrically connected, and then disposed as a whole within a groove in the substrate. This results in a compact structure with a low overall package height, facilitating miniaturization and thinner designs. Furthermore, by electrically connecting a redistribution layer to the first pad within the groove, and redistributing the I / O terminals of the redistribution layer to form a second pad, the thickness of the substrate bottom is reduced to a minimum, further decreasing the overall package height.
[0024] The packaging product provided by this utility model includes the above-mentioned chip stacking packaging structure, which has a compact structure and low overall packaging height. Attached Figure Description
[0025] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0026] Figure 1 A schematic diagram of a chip stacking packaging structure provided in an embodiment of this utility model;
[0027] Figure 2 A schematic diagram of a chip stacking packaging structure in which a redistribution layer and an insulating layer are formed on a substrate, as provided in an embodiment of the present invention;
[0028] Figure 3 A schematic diagram of a stacked chip in a chip stacking packaging structure provided in an embodiment of this utility model;
[0029] Figure 4 This is another schematic diagram of the chip stacking packaging structure provided in an embodiment of the present utility model.
[0030] Icons: 100 - Chip stacked package structure; 110 - Substrate; 111 - First surface; 112 - Second surface; 113 - Groove; 114 - First pad; 120 - Stacked chips; 121 - Connecting bump; 131 - First chip; 132 - Second chip; 133 - Second conductive pillar; 134 - Third pad; 140 - Redistribution layer; 141 - First conductive pillar; 142 - Fourth pad; 143 - Conductive lead; 150 - Insulating layer; 151 - Second pad; 153 - Solder ball; 160 - Molded package. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0032] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0033] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0034] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this utility model is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0035] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0036] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0037] The following detailed description, in conjunction with the accompanying drawings, outlines some embodiments of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0038] Combination Figure 1 and Figure 2The present invention provides a chip stacking packaging structure 100, which first stacks multiple chips sequentially and electrically connects them to form a single stacked chip 120, and then mounts the stacked chip 120 into the groove 113 of the substrate 110, which can significantly reduce the overall packaging height and achieve miniaturized and thin packaging.
[0039] The chip stacked package structure 100 includes a substrate 110, a stacked chip 120, a redistribution layer 140, an insulating layer 150, and a second pad 151. The substrate 110 includes a first surface 111 and a second surface 112 disposed opposite each other along its thickness direction. A groove 113 is formed on the first surface 111; a first pad 114 is provided at the bottom of the groove 113. The stacked chip 120 includes a plurality of chips stacked sequentially along its thickness direction. Connecting bumps 121 are provided on the surface of the stacked chip 120, and each chip is electrically connected to the connecting bumps 121. The stacked chip 120 is disposed within the groove 113, with the side of the stacked chip 120 having the connecting bumps 121 facing the bottom of the groove 113. The connecting bumps 121 and the first pad 114 are electrically connected. The redistribution layer 140 is disposed on the second surface 112 and is electrically connected to the first pad 114; the insulating layer 150 covers the redistribution layer 140. The second pad 151 is electrically connected to the side of the redistribution layer 140 away from the first pad 114, and the second pad 151 is exposed from the insulating layer 150. Since a recess 113 is formed in the substrate 110 for mounting the stacked chips 120, the overall package height can be reduced. Furthermore, by sequentially stacking and electrically connecting multiple chips to form the stacked chips 120, and then mounting the stacked chips 120 as a whole, the overall height can be reduced and mounting efficiency improved. Secondly, by designing the redistribution layer 140 to be electrically connected to the first pad 114 within the recess 113, the redistribution layer 140 redistributes the I / O terminals to form the second pad 151. This reduces the thickness of the bottom of the substrate 110 to its thinnest point, decreasing the overall package height and facilitating miniaturization and thinner design.
[0040] In this embodiment, the stacked chip 120 consists of multiple chips stacked sequentially, with adjacent chips vertically interconnected using TSV (Through Silicon Via) technology. This configuration allows for thinner individual chips and a significantly reduced overall stacking height. For example, a traditional single chip is approximately 100µm thick, while in this embodiment, a single chip vertically interconnected using TSV technology is approximately 25µm thick, representing a thickness reduction of about 75%. Furthermore, the use of TSV for vertical interconnection eliminates the need for wire bonding between adjacent chips and eliminates the need for staggered stacking, thus reducing package size both vertically and horizontally. Moreover, the stacked chip 120 formed by multiple chips vertically interconnected using TSV in this embodiment is not limited by the number of chips stacked; two, three, four, five, six, ten, or more chips can be stacked.
[0041] Combination Figure 3 Optionally, this embodiment describes a structure of two stacked chips. The stacked chip 120 includes a first chip 131, a second chip 132, and a second conductive post 133 electrically connecting the first chip 131 and the second chip 132. The second conductive post 133 is electrically connected to a connecting bump 121. The second conductive post 133 passes through the first chip 131 and the second chip 132, and the connecting bump 121 is located on the side of the first chip 131 away from the second chip 132. Using the second conductive post 133 to achieve the electrical connection between the first chip 131 and the second chip 132 results in a short transmission path, low loss, and high transmission efficiency. The connecting bump 121 is electrically connected to a first pad 114 in the groove 113, achieving the electrical connection between the stacked chip 120 and the substrate 110.
[0042] Optionally, one side of the first pad 114 is connected to the connecting bump 121, and the other side is connected to the redistribution layer 140. It can be understood that when fabricating the redistribution layer 140, the back side of the substrate 110 (i.e., the second surface 112) can be ground until the first pad 114 within the groove 113 is exposed. Then, metal wires are electroplated to form the redistribution layer 140. This allows the redistribution layer 140 to be electrically connected to the first pad 114 within the groove 113 of the substrate 110. This maximizes the reduction of the substrate 110's thickness, thereby lowering the overall package height.
[0043] Optionally, the insulating layer 150 has an opening exposing the redistribution layer 140, and the second pad 151 is disposed in the opening. The insulating layer 150 can be made of PI insulating material to protect the redistribution layer 140. In this embodiment, by setting the redistribution layer 140, the I / O terminals of the substrate 110 are redistributed, making the distribution of the second pad 151 more flexible.
[0044] It should be noted that the routing method of the redistribution layer 140 is very flexible and can be arranged flexibly according to the actual situation. The redistribution layer 140 allows the I / O terminals of the substrate 110 to be distributed only on the second surface 112, forming the second pad 151, or distributed on the first surface 111 of the substrate 110, such as the fourth pad 142. Alternatively, I / O terminal pads can be formed on both the first surface 111 and the second surface 112; no specific limitation is made here.
[0045] Combination Figure 4 Optionally, in some embodiments, the chip stacked package structure 100 further includes a first conductive post 141 connected to the redistribution layer 140, the first conductive post 141 extending to a first surface 111 of the substrate 110; the first conductive post 141 is electrically connected to the stacked chip 120. Optionally, a third pad 134 is provided on the side of the stacked chip 120 away from the connection bump 121, the third pad 134 being electrically connected to the first conductive post 141.
[0046] Optionally, the chip stacked package structure 100 further includes a conductive lead 143. A fourth pad 142 is formed at one end of the first conductive post 141 extending to the first surface 111. The two ends of the conductive lead 143 are respectively connected to the third pad 134 and the fourth pad 142. That is, one end of the conductive lead 143 is soldered to the third pad 134, and the other end is soldered to the fourth pad 142, thereby realizing the electrical connection between the stacked chip 120 and the substrate 110.
[0047] It can be understood that the thickness of the chip stacked package structure 100 is H, where H = H1 + H2 - D; where H1 is the thickness of the substrate 110, H2 is the thickness of the stacked chip 120, and D is the depth of the groove 113.
[0048] Optionally, the depth of the groove 113 can be flexibly set according to actual conditions. The depth of the groove 113 can be less than, equal to, or greater than the thickness of the stacked chips 120. For example, the depth of the groove 113 is equal to the thickness of the first chip 131. Or, the depth of the groove 113 is equal to the sum of the thicknesses of the first chip 131 and the second chip 132; or, the depth of the groove 113 is less than the thickness of the first chip 131; or, the depth of the groove 113 is greater than the thickness of the first chip 131 and less than the sum of the thicknesses of the first chip 131 and the second chip 132. No specific limitation is made here.
[0049] It should be understood that the cross-sectional shape of the groove 113 may include, but is not limited to, a circle, rectangle, triangle, ellipse, or any other shape. The cross-sectional area of the groove 113 may be approximately equal to the cross-sectional area of the first chip 131. Alternatively, the cross-sectional area of the groove 113 may be larger than the cross-sectional area of the first chip 131. In this embodiment, the dimensions of the first chip 131 and the second chip 132 are approximately equal. Of course, in other embodiments, the type, quantity, and size of the first chip 131 and the second chip 132 are not limited and can be flexibly packaged.
[0050] It should be noted that if the cross-sectional area of the groove 113 is larger than the cross-sectional area of the first chip 131, or larger than the cross-sectional area of the stacked chip 120, a fifth pad can be formed on the bottom or wall of the groove 113. The third pad 134 on the stacked chip 120 and the fifth pad are electrically connected by wire bonding.
[0051] Optionally, the chip stacking package structure 100 also includes a molding compound 160, which is disposed on the first surface 111 to cover the stacked chip 120 and to protect the stacked chip 120 and the conductive leads 143 connected thereto.
[0052] The chip stacking package structure 100 provided in this embodiment of the present invention has a packaging method roughly as follows:
[0053] A substrate 110 with a recess 113 is provided, wherein a first pad 114 is provided at the bottom of the recess 113 of the substrate 110. Multiple chips are vertically interconnected using a TSV (Through-Slip Via) process to form a single stacked chip 120, and connection bumps 121 are formed on the surface of the stacked chip 120. The positions of the connection bumps 121 correspond to the positions of the first pad 114. The stacked chip 120 is mounted within the recess 113, and the connection bumps 121 and the first pad 114 are soldered.
[0054] A molding process is used to form a molding compound 160 on the first surface 111 to encapsulate the stacked chip 120 and protect the stacked chip 120.
[0055] After the molding compound 160 has cured, the back side (second surface 112) of the substrate 110 is thinned by grinding until the first pad 114 is exposed. A redistribution layer 140 is formed on the second surface 112 using a series of processes including resist coating, photolithography, development, and electroplating. The redistribution layer 140 is electrically connected to the first pad 114. An insulating layer 150 is then formed on the surface of the redistribution layer 140. An opening is formed on the insulating layer 150 and metal is electroplated to form a second pad 151. The second pad 151 is electrically connected to the redistribution layer 140. The second pad 151 is used to form solder balls 153 for electrical connection with other external components such as circuit boards.
[0056] This utility model embodiment also provides a packaged product, including the aforementioned chip stacked package structure 100. The packaged product also includes a circuit board, solder balls 153 on a substrate 110, and circuit board soldering.
[0057] In summary, the chip stacking packaging structure 100 and the packaged product provided by this utility model have the following beneficial effects, including:
[0058] The chip stacking package structure 100 provided in this embodiment of the present invention comprises multiple chips stacked sequentially and electrically interconnected, and then disposed as a whole within a groove 113 of a substrate 110. The structure is compact, with a low overall package height, which is beneficial for miniaturization and thinning design. The number of stacked chips is unlimited. The use of multi-chip TSV vertical interconnection not only significantly reduces the thickness of individual chips but also eliminates the need for wire bonding space, greatly reducing the horizontal and vertical dimensions of the package structure. Furthermore, the redistribution layer 140 is electrically connected to the first pad 114 within the groove 113, and the redistribution layer 140 redistributes the I / O terminals to form a second pad 151. This minimizes the thickness of the bottom of the substrate 110, reducing the overall package height and facilitating miniaturization and thinning of the package.
[0059] The packaging product provided in this embodiment includes the chip stacking packaging structure 100 described above. It has a compact structure and a low overall packaging height, which is beneficial for achieving miniaturized and thin packaging.
[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of this utility model.
Claims
1. A chip stacking packaging structure, characterized in that, include: The substrate (110) includes a first surface (111) and a second surface (112) disposed opposite to each other along its thickness direction. The first surface (111) has a groove (113) formed therein. The bottom of the groove (113) is provided with a first pad (114). A stacked chip (120) includes a plurality of chips stacked sequentially along the thickness direction. The surface of the stacked chip (120) is provided with connection bumps (121), and each chip is electrically connected to the connection bumps (121). The stacked chip (120) is disposed in the groove (113), and the side of the stacked chip (120) having the connecting bump (121) faces the bottom of the groove (113). The connecting bump (121) is electrically connected to the first pad (114). A redistribution layer (140) is disposed on the second surface (112) and is electrically connected to the first pad (114). An insulating layer (150) covers the redistribution layer (140); The second pad (151) is electrically connected to the side of the redistribution layer (140) away from the first pad (114), and the second pad (151) is exposed from the insulating layer (150).
2. The chip stacking packaging structure according to claim 1, characterized in that, One side of the first pad (114) is connected to the connection bump (121), and the other side is connected to the redistribution layer (140).
3. The chip stacking packaging structure according to claim 1, characterized in that, The insulating layer (150) has an opening that exposes the redistribution layer (140), and the second pad (151) is disposed in the opening.
4. The chip stacking packaging structure according to claim 1, characterized in that, It also includes a first conductive post (141) connected to the redistribution layer (140), the first conductive post (141) extending to the first surface (111); the first conductive post (141) is electrically connected to the stacked chip (120).
5. The chip stacking packaging structure according to claim 4, characterized in that, The stacked chip (120) has a third pad (134) on the side away from the connection bump (121), and the third pad (134) is electrically connected to the first conductive post (141).
6. The chip stacking packaging structure according to claim 5, characterized in that, It also includes a conductive lead (143), and a fourth pad (142) is formed at one end of the first conductive post (141) extending to the first surface (111). The two ends of the conductive lead (143) are respectively connected to the third pad (134) and the fourth pad (142).
7. The chip stacking packaging structure according to claim 1, characterized in that, The stacked chip (120) includes a first chip (131), a second chip (132), and a second conductive post (133) electrically connecting the first chip (131) and the second chip (132), wherein the second conductive post (133) is electrically connected to the connection bump (121).
8. The chip stacking packaging structure according to claim 1, characterized in that, The thickness of the chip stacked packaging structure is H, where H = H1 + H2 - D; where H1 is the thickness of the substrate (110), H2 is the thickness of the stacked chip (120), and D is the depth of the groove (113).
9. The chip stacking package structure according to any one of claims 1 to 8, characterized in that, It also includes a molding compound (160) disposed on the first surface (111) to cover the stacked chip (120).
10. A packaged product, characterized in that, Includes the chip stacking package structure according to any one of claims 1 to 9.