Battery charging driving circuit and battery management chip

Abstract

The utility model provides a battery charging drive circuit and a battery management chip, and relates to the technical field of battery protection, the battery charging drive circuit comprises a zero-volt charging drive switch connected between a power supply end and a charging control end of the battery management chip, and the zero-volt charging drive switch is used for conducting when a battery is in a zero-volt state and is connected with a charger; the normal charging driving switch is controlled by the charging driving signal and is connected between the power supply end and the charging control end; the overcharge protection driving switch is controlled by the overcharge protection driving signal; the voltage division circuit and the overcharge protection driving switch are connected in series and then are connected between the power supply end and the charging negative voltage access end of the battery management chip; the drain electrode of the pull-down MOS tube is used for connecting a charging control end, and the grid electrode and the source electrode are connected through a second resistor in the voltage division circuit. The circuit has the comprehensive advantages of chip area, power consumption, cost and efficiency.

Description

Technical Field

[0001] This utility model relates to the field of battery protection technology, specifically to a battery charging drive circuit and a battery management chip. Background Technology

[0002] In battery management chip applications, the chip controls charging and discharging by monitoring the battery voltage connected between the power supply terminal (VDD) and the battery negative input terminal (VSS), and the voltage between the charging negative voltage input terminal (VM) and VSS. Battery management chip charging applications include... Figure 1 As shown, the source of the switching transistor M2 is connected to the negative voltage input terminal of the chip, and the gate is connected to the charging control terminal (CO) of the chip. Whether the battery is charged or not is controlled by the chip to control the level of the CO voltage relative to the VM voltage, thereby controlling the switching transistor M2 to turn on and off. The diode inside the switching transistor M1, controlled by the discharge control terminal (DO), forms a charging circuit, thereby controlling whether the battery can be charged.

[0003] Traditional battery management chips only have basic normal charging and overcharge protection functions. As battery power consumption increases, when the battery level is insufficient to support the normal operation of most internal circuits or drops to 0V, such battery management chips cannot continue to drive the switching transistor M2 to start charging. To solve this problem, existing technologies typically choose to configure a zero-volt charging drive circuit on the PCB board, which leads to a larger PCB area and increased cost.

[0004] Although some related technologies propose integrating the zero-volt charging drive circuit into the battery management chip, the zero-volt charging drive switch that controls the CO voltage to rise and the pull-down MOSFET that controls the CO voltage to fall are generally interconnected at their gates, forming an inverter structure, such as... Figure 2 As shown, the zero-volt charging drive switch is a PMOS transistor, and the pull-down MOS transistor is an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are connected as the signal input terminal IN, and their drains are connected as the output terminal connected to the charging control terminal. When the voltage at the input terminal IN is logic low, the PMOS transistor is turned on, and the NMOS transistor is not turned on, causing the CO voltage to be pulled up to the VDD voltage, controlling the switch M2 to turn on; when the voltage at the input terminal IN is logic high, the PMOS transistor is not turned on, and the NMOS transistor is turned on, causing the CO voltage to be pulled down to the VM voltage, controlling the switch M2 to turn off.

[0005] Figure 2 The driving circuit shown not only requires the use of high-voltage thick-gate oxide PMOSFETs and isolated high-voltage thick-gate oxide NMOSFETs, resulting in problems such as large chip area and high cost, but also excessive power consumption and low charging efficiency. Utility Model Content

[0006] This invention provides a battery charging drive circuit and a battery management chip to overcome the above-mentioned technical problems.

[0007] To address the aforementioned problems, this utility model discloses a battery charging drive circuit integrated into a battery management chip, comprising:

[0008] A zero-volt charging drive switch is connected between the power supply terminal and the charging control terminal of the battery management chip. The zero-volt charging drive switch is used to turn on when the battery is in a zero-volt state and a charger is connected.

[0009] A normal charging drive switch controlled by a charging drive signal is connected between the power supply terminal and the charging control terminal.

[0010] Overcharge protection drive switch controlled by overcharge protection drive signal; and

[0011] The voltage divider circuit and the pull-down MOSFET are configured such that the voltage divider circuit is connected in series with the overcharge protection drive switch and is connected between the power supply terminal and the charging negative voltage input terminal of the battery management chip; the drain of the pull-down MOSFET is used to connect to the charging control terminal, and the gate and source are connected through the second resistor in the voltage divider circuit.

[0012] In one implementation, a clamping protection circuit is also included, which is connected between the gate and source of the pull-down MOSFET.

[0013] In one implementation, the pull-down MOSFET is a low-voltage MOSFET.

[0014] Furthermore, it also includes: a zero-volt charging detection module,

[0015] The zero-volt charging detection module is connected to the power supply terminal, the charging negative voltage input terminal, and the battery negative input terminal of the battery management chip, respectively. It detects whether the battery is in a zero-volt state and is connected to a charger based on the voltage signals of the power supply terminal, the battery negative input terminal, and the charging negative voltage input terminal, and outputs the detection result signal.

[0016] The zero-volt charging drive switch turns on and off based on the detection result signal.

[0017] Furthermore, the zero-volt charging detection module includes: an inverter structure 1 formed by a first PMOS transistor and a first NMOS transistor sharing a common gate, and a second structure including a fourth resistor and a clamping protection circuit;

[0018] The inverter structure one is connected in series with the fourth resistor and then connected between the power supply terminal and the charging negative voltage input terminal. The input terminal of the inverter structure one is used to connect to the voltage signal of the negative input terminal of the battery, and the output terminal is used to generate the detection result signal.

[0019] Clamping protection circuit two is connected between the power supply terminal and the output terminal of inverter structure one.

[0020] In one implementation, the first NMOS transistor is a low-voltage MOS transistor.

[0021] One implementation also includes: inverter structure two;

[0022] The inverter structure 2 is connected between the power supply terminal and the negative input terminal of the battery management chip. The input terminal receives an overcharge protection drive signal, and the output terminal outputs a charging drive signal.

[0023] In one implementation, one end of the zero-volt charging drive switch is connected to the power supply terminal, and the second end is connected to the charging control terminal through a fifth resistor.

[0024] In one implementation, one end of the normal charging drive switch is connected to the power supply terminal, and the second end is connected to the charging control terminal through a sixth resistor.

[0025] This utility model also discloses a battery management chip, including the battery charging drive circuit as described in this utility model.

[0026] This utility model has the following advantages:

[0027] The battery charging drive circuit provided by this utility model enables the battery management chip to not only realize the normal charging function and overcharge protection function when the battery has power, but also realize the zero-volt charging function when the battery is in a zero-volt state. It can effectively improve or completely solve the technical problems of large chip area, high cost, high power consumption and low charging efficiency in the prior art, and has the comprehensive advantages of chip area, power consumption, cost and efficiency. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model.

[0029] Figure 1 This is a schematic diagram of a common battery management chip's charging application;

[0030] Figure 2 This is a schematic diagram of the existing charging control terminal voltage control structure;

[0031] Figure 3 This is a schematic diagram of the principle of a battery charging drive circuit according to this utility model;

[0032] Figure 4 This is a schematic diagram of the structure of a battery charging drive circuit according to this utility model;

[0033] Figure 5This is a schematic diagram of a battery management chip according to the present invention. Detailed Implementation

[0034] The technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments.

[0035] In the following description, the terms "second," "first," and "XX-a," "XX-b," etc., are used for descriptive convenience to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0036] In this invention, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0037] In this invention, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0038] This invention provides a battery charging drive circuit integrated into a battery management chip. Specifically, the battery can be a lithium battery.

[0039] refer to Figure 3 The battery charging drive circuit includes:

[0040] A zero-volt charging drive switch is connected between the power supply terminal (referred to as VDD in some later descriptions) and the charging control terminal (referred to as CO in some later descriptions) of the battery management chip. The zero-volt charging drive switch is used to turn on when the battery is in a zero-volt state and a charger is connected.

[0041] A normal charging drive switch controlled by a charging drive signal is connected between the power supply terminal VDD and the charging control terminal CO.

[0042] Overcharge protection drive switch controlled by overcharge protection drive signal; and

[0043] The voltage divider circuit and the pull-down MOSFET are connected in series with the overcharge protection drive switch and then connected between the power supply terminal VDD and the charging negative voltage input terminal of the battery management chip (in some descriptions below, the charging negative voltage input terminal is simply referred to as VM); the drain of the pull-down MOSFET is used to connect to the charging control terminal CO, and the gate and source are connected through the second resistor in the voltage divider circuit.

[0044] This invention provides a battery charging drive circuit that not only enables normal charging and overcharge protection when the battery has charge, but also allows for zero-volt charging when the battery is at zero volts. The battery charging drive circuit is integrated into the battery management chip, which effectively reduces the PCB area compared to existing zero-volt charging drive circuits mounted on a PCB board.

[0045] Normal charging refers to charging when the battery voltage is sufficient for most circuits within the battery management chip to operate normally. It allows the charging control terminal CO of the battery management chip to control the charging control FET in the external charging / discharging circuit (as shown in the attached diagram) when the VDD voltage is below the charging overvoltage threshold or the charging current is below the charging overcurrent threshold. Figure 1 The switching transistor M2 in the battery is turned on to charge normally; when the VDD voltage reaches the charging overvoltage threshold or the charging current reaches the charging overcurrent threshold, the CO is controlled to turn off the charging control FET, thereby disconnecting the charging and protecting the battery.

[0046] In this invention, a normal charging drive switch is connected between VDD and CO, and the switching on and off of the normal charging drive switch is controlled by a charging drive signal. When the normal charging drive switch is on, the CO voltage is pulled high by the VDD voltage. For example, when the CO voltage is pulled high enough to equal the VDD voltage, the charging control FET turns on for normal charging.

[0047] Zero-volt charging refers to the ability of a battery management chip to charge a battery when its voltage drops to zero volts due to self-discharge. If a charger is used to charge the battery at zero volts, and the voltage between VDD and VM in the chip circuit exceeds the zero-volt charging threshold, the charging control terminal CO will connect to VDD. If this voltage is sufficient to enable the external charging control FET (such as...) Figure 1 If the switching transistor M2 in the circuit is turned on, then the discharge control FET (such as...) will be activated. Figure 1 The internal diode of the switching transistor M1 can form a charging circuit, which increases the battery voltage. When the battery voltage increases to the point that the VDD voltage exceeds the charging overvoltage threshold, it will return to the normal state. At the same time, the discharge control terminal DO outputs a high level, which turns on the external discharge control FET.

[0048] In this invention, a zero-volt charging drive switch is connected between VDD and CO. The zero-volt charging drive switch is used to turn on when the battery is in a zero-volt state and a charger is connected, thereby connecting CO and VDD and enabling zero-volt charging of the battery. It is worth noting that "zero-volt state" should not be simply interpreted as the battery voltage being 0V. In some applications, there are requirements based on the charger's charging voltage, which needs to be greater than a set zero-volt charging threshold voltage. In this case, the battery's "zero-volt state" should be understood as a state where the battery voltage is close to 0V, and in this state, the battery voltage is greater than the set zero-volt charging threshold voltage. In short, the zero-volt state can be understood as the battery voltage being zero volts or the charge being insufficient to support the normal operation of most circuits within the chip.

[0049] In practical implementation, the control terminal of the zero-volt charging drive switch can be controlled by a detection result signal that indicates whether the battery is in a zero-volt state and a charger is connected. That is, the zero-volt charging drive switch can be turned on and off based on this detection result signal. The level of the detection result signal can be used to characterize either the battery being in a zero-volt state and connected to a charger, or other states. When the battery is in a zero-volt state and a charger is connected, the detection result signal becomes an active level, causing the zero-volt charging drive switch to turn on; in other states, the detection result signal becomes an inactive level, and the zero-volt charging drive switch is off. For example, when the battery is in a zero-volt state and a charger is connected, the level of the detection result signal becomes low, and the zero-volt charging drive switch turns on; when the battery power is sufficient to support the normal operation of most internal circuits of the chip, or when the battery is in a zero-volt state but not connected to a charger, the detection result signal is high, and the zero-volt charging drive switch is off.

[0050] In this invention, the overcharge protection drive function is implemented by the coordinated operation of an overcharge protection drive switch, a voltage divider circuit, and a pull-down MOSFET. Specifically, the overcharge protection drive switch and the voltage divider circuit are connected in series between VDD and VM. The overcharge protection drive switch is controlled by an overcharge protection drive signal. When the overcharge protection drive switch is turned on based on this overcharge protection drive signal, different nodes on the voltage divider circuit can divide the voltage difference between VDD and VM. Since the drain of the pull-down MOSFET is used to connect to the charging control terminal, and the gate and source are connected through the second resistor in the voltage divider circuit, that is, the gate and source are respectively connected to different nodes in the voltage divider circuit, so that there is a voltage difference between the gate and source of the pull-down MOSFET, thereby turning on (i.e., conducting) the pull-down MOSFET. In specific applications, the gate voltage and source voltage of the pull-down MOSFET can be controlled separately by adjusting or designing the resistance ratios in the voltage divider circuit to ensure that the pull-down MOSFET is turned on.

[0051] When the pull-down MOSFET is turned on, it can pull the CO voltage low based on the VM voltage, ensuring that the difference between the CO voltage and the VM voltage is less than the turn-on threshold (also known as the turn-on threshold) of the charging control FET. For example, if the pull-down MOSFET pulls the CO voltage down to the VM voltage, meaning the CO voltage equals the VM voltage, then at this time... Figure 1 The gate voltage of the switch M2 is the VM voltage. Since the source voltage of the switch M2 is also the VM voltage, the VGS of the switch M2 is equal to 0. The switch M2 cannot be turned on, interrupting the charging path between the charger and the battery.

[0052] Those skilled in the art will understand that the voltage divider circuit referred to in the various embodiments of this utility model is a resistor voltage divider circuit, which is generally composed of multiple resistors connected in series. Different implementations are possible for the voltage divider circuit:

[0053] In one implementation (not shown in the figure), the voltage divider circuit also includes a first resistor connected in series with the second resistor. The first resistor is connected to VDD via a charge protection drive switch, and the second resistor is connected to VM.

[0054] In another implementation (not shown in the figure), the voltage divider circuit also includes a third resistor connected in series with the second resistor. The second resistor is connected to VDD via a charge protection drive switch, and the third resistor is connected to VM.

[0055] For reference Figure 3 In the implementation shown, the voltage divider circuit also includes a first resistor R1 and a third resistor R3. The first resistor R1, the second resistor R2, and the third resistor R3 are connected in series. The first resistor R1 is connected to VDD through a charging protection drive switch, and the third resistor R3 is connected to VM.

[0056] The first resistor R1, the second resistor R2, and the third resistor R3 in this utility model are schematic representations of resistor positions and do not represent that there is only one resistor in reality. In practice, one or more of the first resistor R1, the second resistor R2, and the third resistor R3 can also be implemented by a resistor string (i.e., multiple resistors). Figure 3 In the implementation shown, resistor R3 can prevent the source and drain of the pull-down MOSFET from being broken down, thus protecting the pull-down MOSFET.

[0057] Unlike existing technologies, this invention achieves a non-inverter structure where the gates of the pull-up device (normal charging drive switch, zero-volt charging drive switch) that pulls up the CO voltage and the pull-down transistor (pull-down MOS transistor) that pulls down the CO voltage are not connected together. As charging progresses, the VDD voltage gradually rises. Before reaching the charging protection threshold (charging overvoltage threshold or charging overcurrent threshold), the pull-up device remains on, and the pull-down transistor remains off, thus eliminating the path from VDD to VM. In other words, the battery charging drive circuit provided by this invention ensures that, whether the battery is in normal charging or zero-volt charging, there is no situation where the pull-up and pull-down devices are simultaneously on, creating a current path from VDD to VM. This eliminates additional power consumption and improves charging efficiency for both normal and zero-volt charging.

[0058] This invention utilizes a voltage divider circuit to resistively divide the voltage difference between VDD and VM, thereby ensuring that the gate voltage and / or source voltage of the pull-down MOSFET is a voltage divider of the voltage difference between VDD and VM, thus reducing the gate-source voltage V of the pull-down MOSFET. GS Within a certain range, as long as this range is less than the gate-source breakdown voltage of the low-voltage MOSFET, the pull-down MOSFET can be implemented using a regular low-voltage MOSFET. This circuit structure reduces the Vd requirement for the pull-down MOSFET. GS The voltage withstand capability requirement means that a high-voltage, thick-gate oxide MOSFET is not always necessary to withstand the high voltage from VDD to VM. This invention provides an additional option when selecting a pull-down MOSFET, eliminating the reliance on high-voltage, thick-gate oxide MOSFETs. In practical applications, when using a low-voltage MOSFET as the CO voltage pull-down device, compared to traditional drive circuits using high-voltage, thick-gate oxide MOSFETs, this invention can reduce area, reduce mask layers, and thus reduce chip cost.

[0059] In other words, the battery charging drive circuit provided by this utility model can effectively improve or completely solve the technical problems of large chip area, high cost, excessive power consumption and low charging efficiency in the prior art, and has the comprehensive advantages of chip area, power consumption, cost and efficiency.

[0060] Continue to refer to Figure 3 Furthermore, the battery charging drive circuit of this embodiment may also include a clamping protection circuit, which is connected between the gate and source of the pull-down MOSFET. Through the design of the clamping protection circuit, the gate-source voltage of the pull-down MOSFET can be turned on when it exceeds the trigger threshold of the clamping protection circuit, thereby clamping and fixing the gate-source voltage of the pull-down MOSFET and ensuring that the gate and source of the pull-down MOSFET implemented with a low-voltage MOSFET will not be damaged when the difference between VDD and VM is too large.

[0061] In a preferred embodiment of the battery charging drive circuit of this utility model, the pull-down MOSFET is a low-voltage MOSFET.

[0062] refer to Figure 4 The battery charging drive circuit of this utility model also includes a zero-volt charging detection module.

[0063] The zero-volt charging detection module is connected to the power supply terminal, the charging negative voltage input terminal, and the battery negative input terminal of the battery management chip (hereinafter referred to as VSS in some descriptions). It detects whether the battery is in a zero-volt state and a charger is connected based on the voltage signals of the power supply terminal VDD, the battery negative input terminal VSS, and the charging negative voltage input terminal VM, and outputs the detection result signal. The zero-volt charging drive switch is turned on and off based on the detection result signal.

[0064] In short, the zero-volt charging detection module can control the validity of the generated detection result signal based on the voltage signals of VDD, VSS, and VM, thereby controlling the on and off of the zero-volt charging drive switch. When the battery power is sufficient to support the normal operation of most internal circuits of the chip, VDD is positive, and the voltages of VSS and VM are zero volts. At this time, the detection result signal can be controlled to a high level based on the VDD voltage. When the battery is at zero volts and a charger is connected, the voltages of VDD and VSS are both zero volts, while VM exhibits a negative voltage relative to VSS. At this time, the detection result signal can be controlled to a low level based on the VM voltage. When the battery is at zero volts and no charger is connected, the entire internal circuitry of the chip does not operate.

[0065] Based on the above working principle, the zero-volt charging detection module can be implemented using an inverter structure. The voltage signal VSS is the input signal of this inverter structure, and the output of the inverter structure is used to output the detection result signal. For specific structure details, please refer to [link / reference needed]. Figure 4 The zero-volt charging detection module includes: an inverter structure I formed by a common gate of a first PMOS transistor PM1 and a first NMOS transistor NM1, and a clamping protection circuit II including a fourth resistor R4; the inverter structure I and the fourth resistor R4 are connected in series between the power supply terminal VDD and the charging negative voltage input terminal VM; the input terminal of the inverter structure I is connected to the voltage signal of the battery negative terminal VSS through a resistor R7, and the output terminal is used to generate a detection result signal; the clamping protection circuit II is connected between the power supply terminal VDD and the output terminal of the inverter structure I.

[0066] Based on the different driving capabilities of the first PMOS transistor PM1 and the first NMOS transistor NM1 in the inverter structure, the detection result signal can be controlled to be low or high. Specifically, when the battery power is sufficient to support the normal operation of most internal circuits of the chip, VDD is positive, and the voltages of VSS and VM are zero volts. At this time, the first PMOS transistor PM1 is turned on, the first NMOS transistor NM1 is turned off, and the detection result signal is pulled high by the VDD voltage, resulting in a high-level output. When the battery is at zero volts and a charger is connected, the voltages of VDD and VSS are both zero volts, while the VM voltage is negative. At this time, the first PMOS transistor PM1 is turned off, the first NMOS transistor NM1 is turned on, and the detection result signal is pulled low by the VM voltage, resulting in a low-level output. When the battery is at zero volts and no charger is connected, the entire internal circuitry of the chip is inactive.

[0067] It is worth emphasizing that if only an inverter structure is used to implement the zero-volt charging detection module, the large voltage difference between VM and VSS necessitates a high-voltage, thick-gate oxide MOSFET (NM1) to meet circuit requirements. However, using a thick-gate oxide MOSFET increases its area and the number of mask layers, thus increasing wafer costs. Therefore, as... Figure 4 As shown, the zero-volt charging detection module of this embodiment includes not only an inverter structure but also a fourth resistor R4 and a clamping protection circuit. Through the combined action of the fourth resistor R4 and the clamping protection circuit, the first NMOS transistor NM1 can be implemented using a common low-voltage MOS transistor, providing more options compared to existing technologies. Of course, preferably, the first NMOS transistor is a low-voltage MOS transistor.

[0068] The working principle of the fourth resistor R4 and the second clamping protection circuit is explained below:

[0069] When the battery is at zero volts and a charger is connected, the VM voltage is negative, and the first NMOS transistor NM1 is turned on. At this time, the detection result signal is pulled to the source voltage of the first NMOS transistor NM1, which is also negative, and the level of the detection result signal becomes low.

[0070] If the VM voltage is very negative, and the voltage difference between it and VSS becomes large, the voltage of the detection result signal is also pulled very negative. The clamping protection circuit two will clamp the voltage difference between VDD and the detection result signal to a fixed value. At this time, a current I flows through the clamping protection circuit two, and flows through the first NMOS transistor NM1 to R4 and finally to VM. Since the drain of the first NMOS transistor NM1 is the output terminal of the detection result signal, it can be considered that the maximum voltage difference between the drain of the first NMOS transistor NM1 (i.e., the output terminal of inverter structure one) and VDD is clamped and fixed. Since the first NMOS transistor NM1 must be working in the linear region when VM is very negative, its source and drain voltages are basically equal. Therefore, it can be considered that the source voltage of the first NMOS transistor NM1 and the VDD voltage are also clamped and fixed. When the battery is at zero volts and a charger is connected, the voltages of VSS and VDD are both zero volts. The gate voltage of the first NMOS transistor NM1 is also fixed based on the VSS voltage, which is equivalent to the difference between the gate voltage and the source voltage of the first NMOS transistor NM1 being clamped and fixed. In other words, once the voltage difference between VM and VSS reaches the point where the clamping protection circuit 2 can work, the gate-source voltage of the first NMOS transistor NM1 is also clamped, which allows the first NMOS transistor NM1 to be implemented using a low-voltage NMOS transistor.

[0071] In this circuit, the source voltage of the first NMOS transistor NM1 is equal to the VM voltage plus I*R4. Since the gate-source voltage of the first NMOS transistor NM1 is also clamped, the source voltage and VDD voltage are also clamped and fixed. When its gate voltage is 0V, the source voltage is also a fixed value. In different charging applications, the voltage of the connected charger varies, and the negative VM voltage also varies. When the VM voltage decreases with the application, although the current I increases accordingly, the final negative increase in VM voltage due to the application falls across R4, ensuring that the gate-source of the first NMOS transistor NM1, implemented using a low-voltage NMOS transistor, will not be broken down. Simultaneously, due to the action of the second clamping protection circuit, the source-drain voltage of the first PMOS transistor PM1 and the gate-source voltage of the zero-volt charging drive switch implemented through the MOS transistor are also clamped. Therefore, the second clamping protection circuit also protects the first PMOS transistor PM1 and the zero-volt charging drive switch.

[0072] Obviously, based on Figure 4 The design of the zero-volt charge-disable detection module shown not only allows the first NMOS transistor NM1 to be implemented using a common low-voltage MOS transistor, enabling the entire circuit to achieve a lower level of mask and smaller area, thus reducing wafer costs, but also makes the battery management chip provided by this solution more versatile and applicable to chargers with different voltage specifications.

[0073] In this utility model, both clamping protection circuit one and clamping protection circuit two can be implemented based on some existing clamping protection circuits, and this utility model does not limit them.

[0074] It is worth noting that although low voltage and high voltage are relative concepts, there is a strong consensus among those skilled in the art regarding the distinction between high-voltage and low-voltage MOSFETs: high-voltage MOSFETs typically have higher voltage withstand capability but higher on-resistance, slower switching speed, and larger area with more layers; low-voltage MOSFETs, on the other hand, have lower on-resistance, faster switching speed, fewer layers, and smaller area, but limited voltage withstand capability. Structurally, high-voltage MOSFETs typically have a thicker oxide layer and a longer channel, i.e., a thicker gate to withstand higher voltage stress. Furthermore, the material selection for high-voltage MOSFETs is more stringent to ensure stability and reliability at high voltages. Low-voltage MOSFETs, in contrast, have a relatively simpler structure, a thinner oxide layer, and a shorter channel, typically a thin gate, which helps to improve switching speed and reduce power consumption. Therefore, the distinction between low-voltage and high-voltage MOSFETs is very clear in the art. In this invention, it can be considered that the low-voltage MOSFET has a lower voltage withstand capability than the high-voltage MOSFET in one or more of the following voltage withstand parameters: DS (drain-source), DB (drain-bulk), and GS (gate-source).

[0075] In various embodiments of this utility model, the zero-volt charging drive switch, overcharge protection drive switch, and normal charging drive switch are all implemented using MOSFETs, specifically PMOS transistors. The pull-down MOSFET can be implemented using an NMOS transistor. Figure 4 The zero-volt charging drive switch is represented by PMOS transistor PM4, the overcharge protection drive switch by PMOS transistor PM2, the normal charging drive switch by PMOS transistor PM3, and the pull-down MOSFET by NM4. The detection result signal is represented by Ctrl1, the overcharge protection drive signal by Ctrl2, and the charging drive signal by Ctrl3.

[0076] Unlike existing technologies that require complex circuit design to generate the charging drive signal ctrl3, this invention provides a simple solution for generating the charging drive signal. (Continue to refer to...) Figure 4 The battery charging drive circuit also includes an inverter structure two, which is connected between VDD and the battery negative terminal VSS. The input terminal receives the overcharge protection drive signal ctrl2, and the output terminal outputs the charging drive signal ctrl3.

[0077] In this utility model, reference Figure 4 The battery charging drive circuit may also include a fifth resistor R5 and a sixth resistor R6.

[0078] In this circuit, one end of the zero-volt charging drive switch is connected to the power supply terminal VDD, and the second end is connected to the charging control terminal CO through the fifth resistor R5. For the zero-volt charging drive switch, the fifth resistor R5 can limit the current, so that during the zero-volt charging process, it can protect the source and drain of the zero-volt charging drive switch and the charging control terminal CO, and also provide ESD (Electro-Static Discharge) protection.

[0079] In this circuit, one end of the normal charging drive switch is connected to the power supply terminal VDD, and the second end is connected to the charging control terminal CO through the sixth resistor R6. For the normal charging drive switch, the sixth resistor R6 can limit the current, so that during the normal charging process, it can protect the source and drain of the normal charging drive switch and the charging control terminal CO, and also provide ESD (Electro-Static Discharge) protection.

[0080] This utility model also provides a battery management chip, see reference. Figure 5 The chip includes a power supply terminal VDD, a battery negative input terminal VSS, a charging negative voltage access terminal VM, a charging control terminal CO, and the battery charging drive circuit of this invention. The battery charging drive circuit is connected to the power supply terminal VDD, the battery negative input terminal VSS, the charging negative voltage access terminal VM, and the charging control terminal CO, respectively. For the specific connection method and the relevant structure and working principle of the battery charging drive circuit, please refer to the previous text, which will not be elaborated here.

[0081] Compared to traditional battery management chips, the battery management chip of this invention not only enables normal charging and overcharge protection when the battery has charge, but also zero-volt charging when the battery is at zero volts. Based on this invention's technical solution, whether the battery is in normal charging or zero-volt charging, there will be no simultaneous conduction of pull-up and pull-down devices, thus avoiding a current path between VDD and VM. This eliminates additional power consumption and improves charging efficiency for both normal and zero-volt charging. Furthermore, compared to existing technologies, this invention offers more choice in selecting the pull-down MOSFET, eliminating reliance on high-voltage, thick-gate oxide MOSFETs. When using low-voltage MOSFETs as CO voltage pull-down devices in practical applications, compared to traditional drive circuits using high-voltage, thick-gate oxide MOSFETs, this invention can reduce area and mask layers, thereby reducing chip cost.

[0082] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0083] The technical solution provided by this utility model has been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The descriptions of the above embodiments are only for the purpose of helping to understand this utility model, and the content of this specification should not be construed as a limitation of this utility model. Furthermore, for those skilled in the art, there will be different forms of changes in the specific implementation methods and application scope based on this utility model. It is neither necessary nor possible to exhaustively list all implementation methods here, but obvious changes or modifications derived therefrom are still within the protection scope of this utility model.

Claims

1. A battery charging drive circuit, characterized in that, Integrated into the battery management chip, including: A zero-volt charging drive switch is connected between the power supply terminal and the charging control terminal of the battery management chip. The zero-volt charging drive switch is used to turn on when the battery is in a zero-volt state and a charger is connected. A normal charging drive switch controlled by a charging drive signal, wherein the normal charging drive switch is connected between the power supply terminal and the charging control terminal; Overcharge protection drive switch controlled by overcharge protection drive signal; and The voltage divider circuit and the pull-down MOSFET are configured such that the voltage divider circuit is connected in series with the overcharge protection drive switch and is connected between the power supply terminal and the charging negative voltage input terminal of the battery management chip; the drain of the pull-down MOSFET is connected to the charging control terminal, and the gate and source are connected through the second resistor in the voltage divider circuit.

2. The battery charging drive circuit according to claim 1, characterized in that, It also includes a clamping protection circuit, which is connected between the gate and source of the pull-down MOS transistor.

3. The battery charging drive circuit according to claim 1 or 2, characterized in that, The pull-down MOSFET is a low-voltage MOSFET.

4. The battery charging drive circuit according to claim 1, characterized in that, Also includes: Zero-volt charging detection module, The zero-volt charging detection module is connected to the power supply terminal, the charging negative voltage input terminal, and the battery negative input terminal of the battery management chip, respectively, to detect whether the battery is in a zero-volt state and connected to a charger based on the voltage signals of the power supply terminal, the battery negative input terminal, and the charging negative voltage input terminal, and outputs the detection result signal. The zero-volt charging drive switch turns on and off based on the detection result signal.

5. The battery charging drive circuit according to claim 4, characterized in that, The zero-volt charging detection module includes: an inverter structure 1 formed by a first PMOS transistor and a first NMOS transistor sharing a common gate, and a clamping protection circuit 2 including a fourth resistor; The inverter structure one is connected in series with the fourth resistor and then connected between the power supply terminal and the charging negative voltage input terminal. The input terminal of the inverter structure one is used to connect to the voltage signal of the negative terminal input of the battery, and the output terminal is used to generate the detection result signal. The second clamping protection circuit is connected between the power supply terminal and the output terminal of the first inverter structure.

6. The battery charging drive circuit according to claim 5, characterized in that, The first NMOS transistor is a low-voltage MOS transistor.

7. The battery charging drive circuit according to claim 1, characterized in that, It also includes: inverter structure two; The inverter structure two is connected between the power supply terminal and the negative battery input terminal of the battery management chip. The overcharge protection drive signal is input at the input terminal, and the charging drive signal is output at the output terminal.

8. The battery charging drive circuit according to claim 1, characterized in that, in, One end of the zero-volt charging drive switch is connected to the power supply terminal, and the second end is connected to the charging control terminal through a fifth resistor.

9. The battery charging drive circuit according to claim 1, characterized in that, in, One end of the normal charging drive switch is connected to the power supply terminal, and the second end is connected to the charging control terminal through a sixth resistor.

10. A battery management chip, characterized in that, Includes the battery charging drive circuit as described in any one of claims 1-9.

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