Target detection circuit and field programmable gate array chip

Abstract

The utility model relates to the technical field of target detection, in particular to a target detection circuit and a field programmable gate array chip. The circuit comprises a cache module and a detection module, wherein the detection module comprises a first detection unit, a second detection unit and an output unit; the first detection unit outputs a first detection result to the output unit according to Doppler dimension data; the second detection unit outputs a second detection result to the output unit by detecting distance dimension data input by the cache module; and the output unit outputs a target detection result according to the first detection result and the second detection result. In this way, Doppler dimension detection is completed while data are cached once, and distance dimension detection is completed when cached data are read, so that resource consumption is reduced, and delay of read-write operation is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to target detection technical field, concretely relates to a target detection circuit and field programmable gate array chip. BACKGROUND

[0002] CFAR (Constant False Alarm Rate) is an adaptive detection algorithm commonly used in radar systems, aiming to achieve stable target detection under noise, clutter and interference background. The core of CFAR algorithm is to keep the system false alarm probability (Pfa) constant, that is, to maintain the robustness of detection in changing background environment, thereby reducing the possibility of false alarm.

[0003] The inventors found in the process of implementing the embodiments of the utility model that the existing scheme of implementing CFAR algorithm on field programmable gate array (FPGA) has relatively large resource consumption and certain calculation delay in the processing process. UTILIT Y MODEL CONTENT

[0004] The embodiments of the utility model mainly solve the technical problems of large resource consumption and calculation delay of existing FPGA in implementing CFAR algorithm, have the characteristics of more saving in logical resource consumption, smaller delay in processing and more convenient in finding the optimal CFAR structure in the debugging stage.

[0005] To solve the above technical problems, one technical scheme adopted by the embodiments of the utility model is to provide a target detection circuit, which comprises: a cache module and a detection module, the cache module is connected with the detection module; the detection module comprises a first detection unit, a second detection unit and an output unit, the output unit is connected with the first detection unit and the second detection unit respectively, and the cache module is connected with the second detection unit; the cache module receives radar echo data, the radar echo data comprises Doppler dimension data and distance dimension data, at the same time, the first detection unit receives the Doppler dimension data; the first detection unit outputs a first detection result to the output unit according to the Doppler dimension data; the second detection unit outputs a second detection result to the output unit by detecting the distance dimension data input by the cache module; and the output unit outputs a target detection result according to the first detection result and the second detection result.

[0006] In some embodiments, the target detection circuit further comprises a data input module, which is connected with the buffer module and the first detection unit respectively, and the data input module inputs the radar echo data to the buffer module, and meanwhile, the data input module inputs the Doppler dimension data to the first detection unit.

[0007] In some embodiments, the first detection unit comprises a storage subunit and a first algorithm subunit, the storage subunit is connected with the first algorithm subunit, and the storage subunit buffers the first detection result output by the first algorithm subunit; the second detection unit comprises a second algorithm subunit, the storage subunit outputs the first detection result to the output unit, and meanwhile, the second algorithm subunit outputs the second detection result to the output unit.

[0008] In some embodiments, the first algorithm subunit comprises a first calculation subunit and a first selection subunit, the first calculation subunit comprises a first critical average circuit and a first maximum value order circuit, the first selection subunit is a first selection switch circuit, and the first selection switch circuit is connected with the first critical average circuit and the first maximum value order circuit respectively; the first selection switch circuit is used for selecting to connect the storage subunit to the first critical average circuit or the first maximum value order circuit, so that the first critical average circuit or the first maximum value order circuit takes the detection result of the Doppler dimension data as the first detection result and outputs to the storage subunit.

[0009] In some embodiments, the second algorithm subunit comprises a second calculation subunit and a second selection subunit, the second calculation subunit comprises a second critical average circuit, a second maximum value order circuit and a minimum value order circuit, the second selection subunit is a second selection switch circuit, the second selection switch circuit is connected with the second critical average circuit, the second maximum value order circuit and the minimum value order circuit respectively, and the second selection switch circuit is used for selecting the second critical average circuit or the second maximum value order circuit or the minimum value order circuit, so that the selected second critical average circuit or the second maximum value order circuit or the minimum value order circuit takes the detection result of the distance dimension as the second detection result and outputs to the output unit.

[0010] In some embodiments, the first critical average circuit and the second critical average circuit each include a first reference unit, a second reference unit, a first protection unit, a second protection unit, a third detection unit, a first processing unit, and a first decision unit, the first processing unit performs average value calculation on the first reference unit and the second reference unit, outputs an average value to the first decision unit, the first decision unit detects the average value and a value of the third detection unit, and outputs a critical average circuit detection result to the first selection switch circuit or the second selection switch circuit.

[0011] In some embodiments, the first maximum value ordered circuit and the second maximum value ordered circuit each include a third reference unit, a fourth reference unit, a third protection unit, a fourth protection unit, a fourth detection unit, a second processing unit, and a second decision unit, the second processing unit performs maximum value calculation on the third reference unit and the fourth reference unit, outputs a maximum value to the second decision unit, the second decision unit detects the maximum value and a value of the fourth detection unit, and outputs a maximum value ordered circuit detection result to the first selection switch circuit and the second selection switch circuit.

[0012] In some embodiments, the minimum value ordered circuit includes a fifth reference unit, a sixth reference unit, a fifth protection unit, a sixth protection unit, a fifth detection unit, a third processing unit, and a third decision unit, the third processing unit performs minimum value calculation on the fifth reference unit and the sixth reference unit, outputs a minimum value to the third decision unit, the third decision unit detects the minimum value and a value of the fifth detection unit, and outputs a minimum value ordered circuit detection result to the second selection switch circuit.

[0013] In some embodiments, the bus interface between the cache module and the detection module is an AXI-Stream interface.

[0014] To solve the above technical problems, another technical scheme adopted by the embodiment of the utility model is to provide a field programmable gate array chip, the chip is provided with the target detection circuit.

[0015] The utility model discloses a target detection circuit and field programmable gate array chip which are different from the related art. The circuit comprises a cache module and a detection module, the cache module is connected with the detection module, the detection module comprises a first detection unit, a second detection unit and an output unit, the output unit is connected with the first detection unit and the second detection unit respectively, and the cache module is connected with the second detection unit. The cache module receives radar echo data, the radar echo data comprises Doppler dimension data and distance dimension data, simultaneously, the first detection unit receives the Doppler dimension data. The first detection unit outputs a first detection result to the output unit according to the Doppler dimension data. The second detection unit outputs a second detection result to the output unit by detecting the distance dimension data input by the cache module. The output unit outputs a target detection result according to the first detection result and the second detection result. Based on this, the data is stored in the cache module in the Doppler dimension direction and is input into the first detection unit simultaneously for Doppler dimension target detection, and the distance dimension data input by the cache module is received by the second detection unit for distance dimension target detection. In this way, one dimension detection can be completed while the data is cached during the detection process, and another dimension detection can be completed by reading the cached data, thereby reducing the delay of one read-write operation in terms of delay. In addition, the cache operation of the entire target detection process can be completed by only one cache module, thereby saving storage resources. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a schematic diagram of a target detection circuit provided by the utility model embodiment;

[0017] Figure 2 is a schematic diagram of a first detection unit provided by the utility model embodiment;

[0018] Figure 3 is a schematic diagram of a second detection unit provided by the utility model embodiment;

[0019] Figure 4 is a schematic diagram of a calculation process of a first calculation subunit provided by the utility model embodiment. DETAILED DESCRIPTION

[0020] For the convenience of understanding the utility model, the utility model is explained in more detail below in combination with the drawings and specific embodiments. It should be noted that when one element is described as being "connected" to another element, it can be directly connected to the other element or one or more intervening elements can be present therebetween. Similarly, when one module / unit is described as being "connected" to another module / unit, it can be directly connected to the other module / unit or one or more intervening modules / units can be present therebetween. In addition, the terms "first", "second", etc. are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0021] Unless otherwise defined, all technical and scientific terms used in the specification are the same as the meanings commonly understood by those skilled in the art to which the utility model belongs. The terms used in the specification of the utility model are only for the purpose of describing the specific embodiments and are not used to limit the utility model.

[0022] Please refer to Figure 1 The utility model embodiment provides a kind of target detection circuit, which comprises cache module 10 and detection module 20, cache module 10 is connected with detection module 20.

[0023] Detection module 20 includes first detection unit 21, second detection unit 22 and output unit 23, output unit 23 is connected with first detection unit 21, second detection unit 22 respectively, and cache module 10 is connected with second detection unit 22.

[0024] In some embodiments, the target detection circuit further includes a data input module 30 (not shown in the figure), which is connected to the cache module 10 and the first detection unit 21 respectively. The data input module 30 inputs radar echo data to the cache module 10, and at the same time, the data input module 30 inputs Doppler dimension data to the first detection unit 21.

[0025] For the above-mentioned data input module 30, in this embodiment, the data input module 30 inputs radar echo data to the cache module 10, and at the same time, the data input module 30 inputs Doppler dimension data to the first detection unit 21. It can be understood that the radar system first performs ADC sampling of the signal to generate echo data in Doppler dimension and distance dimension. These data are usually frequency spectrum results after FFT processing, reflecting the speed information and distance information of the target. These echo data in Doppler dimension and distance dimension are written to the on-chip RAM through the cache module 10. At the same time, these echo data in Doppler dimension are also input to the first detection unit 21 for subsequent target detection.

[0026] For the above-mentioned cache module 10, the cache module 10 can be an RDMap cache module (Range-Doppler Map Cache), which refers to a module for storing and managing radar echo data, which is usually responsible for caching processing results in the range-doppler domain, providing data support for subsequent target detection algorithms. The structure of the RDMap cache module usually includes: an array of storage units: using BRAM or URAM (FPGA on-chip storage resources), supporting multiple modules to read and write data simultaneously, each storage unit corresponding to the signal strength of a range-doppler unit; address management module: managing the read-write address of the sliding window in the cache, ensuring that the detection module can accurately access the data in each window; FIFO cache (First-In-First-Out): used for temporary storage and forwarding of data, especially when data needs to be transferred between multiple processing stages of the radar (such as data after FFT processing); control logic: managing data access order through a state machine, ensuring data consistency and avoiding conflicts, supporting asynchronous reading and writing to adapt to different processing frequencies of radar signals. In this embodiment, the cache module 10 receives the Doppler dimension data and the range dimension data input by the data input module 30, and outputs the range dimension data to the second detection unit 22. It can be understood that the radar echo data input by the data input module 30 is written into the on-chip RAM through the cache module in a continuous AXI-Stream interface. When all the Doppler dimension and range dimension echo data are written into the RAM, the cache module 10 will mark the completion of the cache and prepare for the next data reading operation. After the data cache is completed, the system will read the stored data from the RAM in the range dimension direction. This means that when performing CFAR detection in the range dimension, the system needs to perform noise estimation and target detection based on the stored data. During the reading process, the cache module 10 will again use the AXI-Stream interface to output the data from the RAM in the form of the range dimension direction. When using the AXI-Stream interface to output data, the cache module 10 will issue a control signal to indicate when to start reading and sending data. This way ensures the real-time and smoothness of the data, so that the subsequent detection module 20 can quickly receive data and process it. That is, through the AXI-Stream interface, data can be seamlessly transferred to the second detection unit 22, supporting real-time Doppler dimension and range dimension target detection.

[0027] For the detection module 20 described above, in the embodiment, the detection module 20 comprises a first detection unit 21, a second detection unit 22 and an output unit 23, the output unit 23 is connected with the first detection unit 21 and the second detection unit 22 respectively, the data input module 30 is connected with the first detection unit 21, and the cache module 10 is connected with the second detection unit 22. It can be understood that the first detection unit 21 directly receives the Doppler dimension data in the radar echo data from the data input module 30, and performs a preliminary detection task (detection in the Doppler dimension). The second detection unit 22 receives the distance dimension data from the cache module 10 and performs detection and analysis in the distance dimension. The output unit 23 integrates the detection results from the first detection unit 21 and the second detection unit 22 to generate a target detection result. The target detection result comprises an identification of the detection result, a state indication or an alarm signal. The working process of the detection module 20 is as follows: first, the data input module 30 receives and processes the input signal and transmits it to the first detection unit 21 for detection in the Doppler dimension. At the same time, the data input module 30 stores the data in the Doppler dimension direction in the cache module 10, so that the data will not be lost in the case of high load or high data flow. Secondly, the first detection unit 21 and the second detection unit 22 can work in parallel, the first detection unit 21 processes real-time data, and the second detection unit 22 analyzes the data in the cache, thereby improving the detection efficiency and accuracy of the system. Finally, the output unit 23 of the detection module 20 integrates the results of the two detection units to generate a final detection report or a state signal, which is provided to an external system or a user.

[0028] In addition, the data input mode of the cache module 10 is to write the radar echo data in the Doppler dimension (first dimension) direction into the on-chip RAM, and then read out the data from the RAM in the distance dimension (second dimension) direction after the data caching is completed. It should be noted that the first dimension direction can also be the distance dimension direction, and the second dimension direction can also be the Doppler dimension direction, which is not limited.

[0029] For the first detection unit 21 described above, in the embodiment, please refer to Figure 2 , Figure 2 is a schematic view of the first detection unit 21 provided by the embodiment of the utility model, the first detection unit 21 includes a storage subunit 212 and a first algorithm subunit 211, the storage subunit 212 is connected with the first algorithm subunit 211, and the storage subunit 212 caches the first detection result output by the first algorithm subunit 211.

[0030] The first algorithm subunit 211 includes a first calculation subunit 2111 and a first selection subunit 2112. The first calculation subunit 2111 includes a first critical average circuit and a first maximum value ordered circuit. The first selection subunit 2112 is a first selection switch circuit. The first selection switch circuit is connected with the first critical average circuit and the first maximum value ordered circuit. The first selection switch circuit is used to select the storage subunit 212 to be connected to the first critical average circuit or the first maximum value ordered circuit, so that the detection result of the Doppler dimension data by the first critical average circuit or the first maximum value ordered circuit is taken as the first detection result and output to the storage subunit 212.

[0031] It can be understood that the first calculation subunit 2111 includes a first critical average circuit (CA circuit) and a first maximum value ordered circuit (GO circuit). The CA circuit implements a constant false alarm rate (CA-CFAR) detection algorithm. It determines whether a target signal exists by calculating the background noise and setting a corresponding threshold value. The CA circuit is usually suitable for a uniform background comparison and can effectively process target detection in a low signal-to-noise ratio environment. The GO circuit implements a gradual increase threshold (GO-CFAR) detection algorithm. Unlike CA-CFAR, GO-CFAR dynamically adjusts the threshold value according to the change of the background, and is suitable for environments with strong clutter or large changes. This adaptive ability makes GO-CFAR have better detection performance in complex scenes. The first selection subunit 2112 is a first selection switch circuit (MUX circuit). The multiplexer (MUX) allows the system to select between the CA circuit and the GO circuit. According to the actual application requirements and the characteristics of the input data, the MUX selects the appropriate algorithm for data processing. This flexibility enables the system to quickly adapt to different environmental conditions and improve the accuracy of detection. The storage subunit 212 (RAM subunit) is used to store intermediate calculation results or historical data, providing a reference for subsequent detection. The use of RAM can reduce repeated calculations and improve processing efficiency.

[0032] The working flow of the first detection unit 21 is as follows: data input: the first detection unit 21 receives echo data of Doppler dimension from the data input module 30 and transmits the same to the first calculation subunit 2111 for processing. Selection algorithm: during the processing, the first selection subunit 2112 (MUX circuit) selects to use the CA circuit or the GO circuit for target detection according to the current environmental condition and the input data characteristics, and the selection can be based on previous detection results or system settings. Calculation and storage: no matter which algorithm is selected, the detection result can be stored to the storage subunit 212 for subsequent further analysis or used for comparison of historical data. Result output: the final detection result (first detection result) will be output by the first detection unit 21 for use of subsequent modules, for example, output to the output unit 23 of integrated results. It can be understood that the first detection unit 21 constructs a high-efficiency and flexible target detection module by combining the CA circuit, the GO circuit and the RAM subunit. The design not only improves the accuracy of detection, but also enhances the adaptability and processing capacity of the system, and provides a solid foundation for the performance of the entire target detection circuit.

[0033] For the second detection unit 22 described above, in the embodiment, please combine Figure 3 , Figure 3 is a schematic view of the second detection unit 22 provided by the embodiment of the utility model, the second detection unit 22 includes the second algorithm subunit 221, the second algorithm subunit 221 includes the second calculation subunit 2211 and the second selection subunit 2212, the second calculation subunit 2211 includes the second critical average circuit, the second maximum value ordered circuit and the minimum value ordered circuit, the second selection subunit 2212 is the second selection switch circuit, the second selection switch circuit is connected with the second critical average circuit, the second maximum value ordered circuit and the minimum value ordered circuit respectively, and the second selection switch circuit is used to select the second critical average circuit or the second maximum value ordered circuit or the minimum value ordered circuit, so that the selected second critical average circuit or the second maximum value ordered circuit or the minimum value ordered circuit takes the detection result of distance dimension as the second detection result and is output to the output unit 23.

[0034] It can be understood that the second calculation subunit 2211 includes a second critical average circuit (CA circuit), a second maximum ordered circuit (GO circuit), and a minimum ordered circuit (SO circuit). Among them, the CA circuit: realizes constant false alarm rate (Cell Averaging CFAR, CA-CFAR) detection, which is suitable for scenes with relatively uniform background, and can effectively process target signals in low signal-to-noise ratio environments; GO circuit: realizes gradual threshold (Greatest Of CFAR, GO-CFAR) detection, dynamically adjusts the threshold to cope with complex background noise, and GO-CFAR performs well in scenes with strong clutter or changes; SO circuit: SO-CFAR (Smallest Of CFAR) uses the minimum value in the surrounding cells as the noise background estimate, which is very effective when the target is small and there is no strong echo nearby, but it may not perform well for high background noise. The second selection subunit 222 is a second selection switch circuit (MUX circuit), which connects the CA circuit, the GO circuit and the SO circuit. According to the difference of input data and environmental conditions, the MUX circuit allows the system to select the most suitable detection algorithm to achieve the best target detection effect.

[0035] The workflow of the second detection unit 22 is as follows: data input: the second detection unit 22 receives the radar echo data in the range dimension (second dimension) direction input by the cache module 10. Selection algorithm: the second selection subunit 2212 (MUX circuit) selects to use the CA circuit, the GO circuit or the SO circuit for further target detection according to the characteristics of the current input data and the environmental conditions. Such flexible selection can optimize the detection performance according to real-time conditions. Depth calculation: the selected circuit will perform depth calculation on the input data to determine the existence and characteristics of the target signal. Each algorithm has its applicable scene, and the system enhances the reliability and accuracy of detection by integrating the advantages of different algorithms. Output result: the final detection result (second detection result) will be passed to the output unit 23, so that the output unit 23 combines the results of the first detection unit 21 to generate target detection results for subsequent processing or display. It can be understood that the second detection unit 22 integrates CA, GO and SO circuits to realize diversified target detection functions. The design of this module not only enhances the detection capability of the system in various environments, but also provides strong support for the overall performance. This flexible and efficient structure makes the target detection circuit perform well in complex signal processing. It should be noted that the storage subunit 212 outputs the first detection result to the output unit 23, and the second algorithm subunit 221 outputs the second detection result to the output unit 23. It can be understood that the first detection result and the second detection result are output in parallel to the output unit 23 for target detection by the output unit 23.

[0036] In some embodiments, the first critical average circuit and the second critical average circuit each include a first reference unit, a second reference unit, a first protection unit, a second protection unit, a third detection unit, a first processing unit, and a first decision unit, the first processing unit performs average value calculation on the first reference unit and the second reference unit, outputs the average value to the first decision unit, the first decision unit detects the average value and a value of the third detection unit, and outputs a critical average circuit detection result to the first selection switch circuit or the second selection switch circuit.

[0037] In some embodiments, the first maximum value ordered circuit and the second maximum value ordered circuit each include a third reference unit, a fourth reference unit, a third protection unit, a fourth protection unit, a fourth detection unit, a second processing unit, and a second decision unit, the second processing unit performs maximum value calculation on the third reference unit and the fourth reference unit, outputs the maximum value to the second decision unit, the second decision unit detects the maximum value and a value of the fourth detection unit, and outputs a maximum value ordered circuit detection result to the first selection switch circuit or the second selection switch circuit.

[0038] In some embodiments, the minimum value ordered circuit (SO circuit) includes a fifth reference unit, a sixth reference unit, a fifth protection unit, a sixth protection unit, a fifth detection unit, a third processing unit, and a third decision unit, the third processing unit performs minimum value calculation on the fifth reference unit and the sixth reference unit, outputs the minimum value to the third decision unit, the third decision unit detects the minimum value and a value of the fifth detection unit, and outputs a minimum value ordered circuit detection result to the second selection switch circuit.

[0039] It should be noted that the CA circuit and the GO circuit in the first calculation subunit 2111 and the CA circuit and the GO circuit in the second calculation subunit 2211 are the same and can be directly reused. The first selection subunit 2112 and the second selection subunit 2212 are also the same and can be directly reused. The reference units, the protection units, the detection units, and the decision units in the CA circuit, the GO circuit, and the SO circuit are the same modules and can be reused, and only the processing units are different.

[0040] For the specific calculation process of the CA circuit, the GO circuit, and the SO circuit, the CA circuit of the first calculation subunit is taken as an example, please refer to Figure 4 , Figure 4 is a schematic diagram of the calculation process of the first calculation subunit according to an embodiment of the present application. As a whole, the CA-CFAR is realized by using a pipeline type sliding window processing method, Figure 4The frame structure shown clearly shows the division of different units and the data flow process. The processing core of the CA-CFAR includes five parts: reference unit: for providing background noise data, such as the X2 to X5 area (first reference unit) and the X11 to X14 area (second reference unit) in the figure are the left and right reference areas. Protection unit: protect the position of the target signal from being disturbed by the reference background, such as the X6 to X7 area (first protection unit) and the X9 to X10 area (second protection unit) in the figure are the protection units. Detection unit: the target signal to be detected, X8 in the figure is the detection unit (third detection unit). Processing unit (first processing unit): average value calculation is performed on the reference unit, and the calculated average value is output to the decision unit (first decision unit). Decision unit: compare the average value and the value of the detection unit to obtain the critical average circuit detection result, and output the critical average circuit detection result to the first selection switch circuit, so that the first selection switch circuit outputs the detection result to the output unit. The principle of the sliding window is that as the data input moves, the window slides on the data stream, and each time a group of reference, protection and detection units are selected for processing, and each movement of the sliding window corresponds to a complete detection process.

[0041] It should be noted that, Figure 4 The detection unit of the CA-CFAR circuit can be one of the third detection unit, the fourth detection unit and the fifth detection unit described above. It can be understood that the detection unit in the CA, GO and SO circuit is not equivalent to the first detection unit and the second detection unit mentioned in the Figure 1

[0042] The operation process of the CA-CFAR circuit is to compare the mean or extreme value of the detection unit X8 and the background reference data to determine whether it is an effective target signal. Based on the mean values of the left and right reference units X2 to X5 and X11 to X14, the critical average circuit detection result Y1 is calculated, and the formula is:

[0043] Y1=X8-T*((mean(sum(x2~x5))+mean(sum(x11~x14))) / 2)

[0044] Where Y1 is the critical average circuit detection result, T is the threshold weighting coefficient, and the sensitivity of the detection can be controlled by adjusting T. The mean value calculation of the reference unit is completed by the adder, and the delay in the detection process depends on the delay of the adder and the multiplier. This process can be configured by the host computer software to configure the number of reference units (such as 2, 4, 6, 8, 16, etc.) and the size of T value.

[0045] In addition, for the operation process of the GO-CFAR circuit, in this embodiment, the background noise of the reference unit is no longer taken as the mean value, but as the maximum value, and the maximum value ordered circuit detection result Y2 is calculated. The formula is:​

[0046] Y2 = X8 - T * (max(x2-x5, x11-x14))

[0047] It can be understood that the GO-CFAR is suitable for the environment with strong background noise, and the maximum value can effectively avoid the influence of noise on detection.

[0048] For the operation process of the SO-CFAR circuit, in the embodiment, the SO-CFAR takes the minimum value of the background noise to calculate the threshold, is suitable for the strong clutter environment, and calculates the minimum value of the ordered circuit detection result Y3. The formula is:

[0049] Y3 = X8 - T * (min(x2-x5, x11-x14))

[0050] It can be understood that the algorithm process of the SO-CFAR is similar to that of the GO-CFAR, but the emphasis is different, and the processing of smaller noise is more fine.

[0051] In addition, in the GO-CFAR and the SO-CFAR, the embodiment also provides a full sorting algorithm to quickly find the maximum or minimum value of the reference cell. It can be understood that by constructing a 4x4 two-dimensional matrix, the size relationship between the four values is compared. By crossing the values in the two-dimensional matrix, the position of the maximum value or the minimum value can be quickly determined. That is, the full sorting algorithm can complete the search of the maximum / minimum value in multiple clock cycles, and this method greatly improves the execution speed of the algorithm. It should be noted that the number of values to be compared in the embodiment is not limited, and can be set according to the actual situation. It should be noted that in the embodiment, the CA, GO, SO and MUX circuits are general circuit modules, and have good universality and portability.

[0052] In some embodiments, the cache module 10 and the detection module 20 are connected through a bus interface, which is an AXI-Stream interface. It can be understood that the AXI-Stream interface is part of the AMBA 3.0 / 4.0 bus protocol, which is designed for high-speed data stream processing. It provides a point-to-point communication mechanism, allowing devices to transmit data in a pipelined manner, which is very suitable for large-scale parallel computing applications in signal processing systems, especially widely used in FPGAs. In the present embodiment, the AXI-Stream interface allows designers to implement modular designs in FPGAs, and the data input, cache and processing modules communicate with each other through the AXI-Stream interface. This modular design is easy to maintain and upgrade, and designers can expand system functions according to needs without changing the entire system communication mechanism. In addition, in FPGAs, hardware resources are limited, and the efficient communication mode of AXI-Stream allows multiple modules to process data in a pipelined manner, improving the utilization of hardware resources and reducing the need for additional storage and transmission resources. Finally, as part of the AMBA standard protocol, AXI-Stream has high compatibility. Its standardized design allows seamless integration of modules within the FPGA, supporting data transmission between IP cores from different vendors.

[0053] In some embodiments, the detection module 20 further comprises a control unit 24 (not shown in the figure), which is connected to the first detection unit 21 and the second detection unit 22.

[0054] The control unit 24 is responsible for managing and coordinating the work of the first detection unit 21 and the second detection unit 22, while providing adjustable parameters to enhance the flexibility and adaptability of the algorithm. The specific functions are as follows: management of control signals: by generating control signals, the work order and data flow of the first detection unit 21 and the second detection unit 22 are coordinated. For example, in the CFAR detection of Doppler dimension and distance dimension, the control unit 24 manages the transmission order of data, ensures the correct timing when data flows from the AXI-Stream interface to each detection unit, and avoids data conflicts or delays. Configurable parameter management: allows users to modify important parameters in the detection algorithm through the host computer or software interface, such as threshold values, reference cell numbers, and guard cell numbers in CA, GO, and SO algorithms. For example, users can adjust the number of reference cells in the CA circuit to optimize detection performance. The control unit 24 will dynamically adjust the calculation logic in the first and second detection units according to the configuration input. Real-time adjustment and optimization: during target detection, environmental conditions may change, such as noise level, interference source intensity, etc. The control unit 24 can adjust the parameters of the algorithm in real time according to external sensors or environmental feedback, thereby optimizing the detection performance of the system. For example, when detecting an increase in environmental noise, the threshold weighting coefficient T can be dynamically adjusted by the control unit to reduce the false alarm rate. Module start-stop control: the control unit 24 is also responsible for starting and stopping each detection module according to the system state. For example, if the data in a certain dimension does not need to be processed, the corresponding calculation unit can be turned off to save FPGA resources. This fine control capability can improve the power efficiency of the system and reduce unnecessary resource consumption.

[0055] It should be noted that the target detection circuit provided by the embodiments of the present application solves the problems of large resource consumption and calculation delay in the existing FPGA implementation of the CFAR algorithm. The working principle is as follows: first, the radar echo data is written into the on-chip RAM of the cache module 10 in the Doppler dimension direction (first dimension) through the data input module 30. At the same time, the CFAR detection in the Doppler dimension is performed in parallel. At this time, the radar echo data in the Doppler dimension is transmitted to the first computing subunit 2111 of the first detection unit 21 for CFAR detection in the Doppler dimension. That is, the radar echo data in the Doppler dimension enters the CA or GO sliding window detection circuit, and the MUX (multiplexer) is responsible for selecting the detection results of CA or GO for output. In addition, the CFAR detection results in the Doppler dimension are first cached in the storage subunit 212 inside the first detection unit 21 before being output. Secondly, when the CFAR detection in the Doppler dimension is completed, the data is read out from the RAM of the cache module 10 according to the distance dimension direction. This step is similar to the processing in the Doppler dimension, but the data processing flow is different. The CFAR detection in the distance dimension uses CA, GO and SO algorithms, and uses the MUX selector to determine which algorithm's output data stream enters the output module. It should be noted that the data processing in the distance dimension no longer needs to be cached twice, but directly outputs the detection results to the output module of the next stage. This direct output design greatly saves the on-chip storage resources and reduces the delay of data transmission and caching. Finally, the detection results in the Doppler dimension and the distance dimension are finally collected in the output unit 23. The output unit 23 is responsible for making a final target judgment according to the CFAR detection results, whether there is a target signal, etc., and outputting the final target detection results.

[0056] Through the above manner, the target detection circuit provided by the embodiment of the utility model can realize the following seven aspects of effects, as follows: the first aspect, the CA, GO, SO and MUX circuit in the whole CFAR detection are all general modules, whether it is Doppler dimension or distance dimension data processing, all can reuse these circuits. This design avoids specially designing independent circuit for different dimension detection, greatly reduces the resource occupation on FPGA. The second aspect, the first detection unit 21 internally reuses the RAM (namely storage subunit 212) of the cache module 10, which means that it is not necessary to additionally design RAM for CFAR processing for secondary caching, which is also an important means of saving on-chip storage resources. The on-chip storage resources of FPGA are usually limited, especially when large-scale parallel processing, the resource demand of RAM is very high, through the reuse design, the utilization efficiency of resources is greatly improved. The third aspect, the distance dimension CFAR detection does not need to cache data again, but directly reads data from the RAM of the cache module 10 and processes. In comparison, if the data needs to be cached to the RAM in the detection module 20 for processing, it not only increases the occupation of storage resources, but also introduces unnecessary delay. The fourth aspect, the whole target detection circuit adopts the architecture of stream processing, and the data flows into each processing module in the continuous AXI-Stream mode. The AXI-Stream protocol guarantees the continuity of data transmission, without waiting for response or interruption, greatly reducing the delay of data transmission. In data processing, the data processing of Doppler dimension and distance dimension is carried out synchronously, and this parallel processing mode also reduces the delay of the whole system. The fifth aspect, the reduction of delay is mainly reflected in the optimization of the caching mechanism. In the data processing process of Doppler dimension, the data is cached only once in the cache module 10, and the data is directly read from the cache in the distance dimension processing, avoiding the process of writing data into the internal RAM of the detection module 20. This design reduces an additional read-write operation, and each read-write operation will introduce additional delay. Therefore, the processing speed of the whole system is significantly improved. The sixth aspect, the CA, GO, SO and other algorithms have been designed in parallel, especially in GO and SO, the parallel sorting circuit is used. The sorting algorithm quickly finds the maximum or minimum value through the parallel matrix mode, greatly reducing the clock period during calculation. In the traditional serial sorting algorithm, the clock period for finding the maximum or minimum value is long, but through the parallel design, these operations can be completed within a few clock periods, thereby further reducing the calculation delay. The seventh aspect, the cached radar echo data (RDMAP) can also be used for other algorithm calculation modules (other calculation modules on the FPGA chip), thereby achieving the reuse of FPGA storage resources, having the effect of saving resources.

[0057] It can be understood that through reasonable module reuse, pipeline design and streaming data processing mode, the entire CFAR FPGA implementation architecture greatly saves on-chip resources, especially the occupation of RAM storage space. At the same time, the number of data read-write operations is reduced and the calculation algorithm is optimized, which significantly reduces the calculation delay of the system. This architecture is very suitable for application in a target detection system, especially in a large-scale parallel processing application scenario, and has a high performance advantage and scalability.

[0058] The embodiment of the utility model further provides a field programmable gate array chip, the field programmable gate array chip is equipped with above-mentioned target detection circuit, for the specific structure and function of target detection circuit can refer to above-mentioned embodiment, this place does not repeat again.

[0059] It should be noted that the specification and drawings of the utility model give a preferred embodiment of the utility model, however, the utility model can be realized through many different forms, and is not limited to the embodiments described in the specification, these embodiments are not as additional limitation to the content of the utility model, the purpose of providing these embodiments is to make the understanding of the disclosure of the utility model more thorough and comprehensive. And, the above technical features continue to combine, form various embodiments not listed above, all are regarded as the range of the utility model specification; further, for those skilled in the art, can be improved or transformed according to the above description, and all these improvements and transformations should belong to the protection scope of the utility model claims.

Claims

1. A target detection circuit, characterized by, The circuit comprises a cache module and a detection module, the cache module being connected with the detection module; The detection module comprises a first detection unit, a second detection unit and an output unit, the output unit being connected with the first detection unit and the second detection unit respectively, and the cache module being connected with the second detection unit; The cache module receives radar echo data, the radar echo data comprising Doppler dimension data and distance dimension data, and at the same time, the first detection unit receives the Doppler dimension data; The first detection unit outputs a first detection result to the output unit according to the Doppler dimension data; The second detection unit outputs a second detection result to the output unit by detecting the distance dimension data input by the cache module; The output unit outputs a target detection result according to the first detection result and the second detection result.

2. The target detection circuit of claim 1, wherein, The target detection circuit further comprises a data input module, the data input module being connected with the cache module and the first detection unit respectively, the data input module inputting the radar echo data to the cache module, and at the same time, the data input module inputting the Doppler dimension data to the first detection unit.

3. The target detection circuit of claim 1, wherein, The first detection unit comprises a storage subunit and a first algorithm subunit, the storage subunit being connected with the first algorithm subunit, and the storage subunit caching the first detection result output by the first algorithm subunit; The second detection unit comprises a second algorithm subunit, the storage subunit outputting the first detection result to the output unit, and at the same time, the second algorithm subunit outputting the second detection result to the output unit.

4. The target detection circuit of claim 3, wherein, The first algorithm subunit comprises a first calculation subunit and a first selection subunit, the first calculation subunit comprising a first critical average circuit and a first maximum value ordered circuit, the first selection subunit being a first selection switch circuit, the first selection switch circuit being connected with the first critical average circuit and the first maximum value ordered circuit respectively; the first selection switch circuit is used for selecting to connect the storage subunit to the first critical average circuit or the first maximum value ordered circuit, so that the first critical average circuit or the first maximum value ordered circuit takes the detection result of the Doppler dimension data as the first detection result and outputs to the storage subunit.

5. The target detection circuit of claim 4, wherein, The second algorithm subunit comprises a second calculation subunit and a second selection subunit, the second calculation subunit comprises a second critical average circuit, a second maximum value ordered circuit and a minimum value ordered circuit, the second selection subunit is a second selection switch circuit, the second selection switch circuit is connected with the second critical average circuit, the second maximum value ordered circuit and the minimum value ordered circuit respectively, and the second selection switch circuit is used for selecting the second critical average circuit or the second maximum value ordered circuit or the minimum value ordered circuit, so that the second critical average circuit or the second maximum value ordered circuit or the minimum value ordered circuit selected is used as the second detection result of the distance dimension, and is output to the output unit.

6. The target detection circuit of claim 5, wherein, The first critical average circuit and the second critical average circuit each comprise a first reference unit, a second reference unit, a first protection unit, a second protection unit, a third detection unit, a first processing unit and a first decision unit, the first processing unit performs average value calculation on the first reference unit and the second reference unit, outputs an average value to the first decision unit, the first decision unit detects the average value and a value of the third detection unit, and outputs a critical average circuit detection result to the first selection switch circuit or the second selection switch circuit.

7. The target detection circuit of claim 5, wherein, The first maximum value ordered circuit and the second maximum value ordered circuit each comprise a third reference unit, a fourth reference unit, a third protection unit, a fourth protection unit, a fourth detection unit, a second processing unit and a second decision unit, the second processing unit performs maximum value calculation on the third reference unit and the fourth reference unit, outputs a maximum value to the second decision unit, the second decision unit detects the maximum value and a value of the fourth detection unit, and outputs a maximum value ordered circuit detection result to the first selection switch circuit or the second selection switch circuit.

8. The target detection circuit of claim 5, wherein, The minimum value ordered circuit comprises a fifth reference unit, a sixth reference unit, a fifth protection unit, a sixth protection unit, a fifth detection unit, a third processing unit and a third decision unit, the third processing unit performs minimum value calculation on the fifth reference unit and the sixth reference unit, outputs a minimum value to the third decision unit, the third decision unit detects the minimum value and a value of the fifth detection unit, and outputs a minimum value ordered circuit detection result to the second selection switch circuit.

9. The target detection circuit of claim 1, wherein, The cache module and the detection module are connected through a bus interface, and the bus interface is an AXI-Stream interface.

10. A field programmable gate array chip, characterized by The chip is provided with the target detection circuit in any one of claims 1 to 9.

Images