Universal flash memory circuit and universal flash memory

Abstract

The utility model discloses a universal flash memory storage circuit and a universal flash memory, and relates to the technical field of embedded semiconductor storage. Comprising a first power supply network, a second power supply network, a third power supply network, a voltage reduction module, a main control unit and a flash memory unit, the main control unit is used for bridging an upper computer and the flash memory unit, and the main control unit is used for controlling and managing erasing, writing and reading operations of the flash memory unit; the flash memory unit is used for storing user data; the input end of the step-down module is connected to the first power supply network or / and the second power supply network, the output end of the step-down module is connected to the flash memory unit, the main control unit and the third power supply network, and the voltage of the output end of the step-down module is smaller than that of the input end of the step-down module; through the above design, compatible use of a plurality of UFS power supply networks is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of embedded semiconductor storage, and in particular to a universal flash memory storage circuit and a universal flash memory. BACKGROUND

[0002] Since the industry standard of the universal flash memory storage (UFS) embedded chip, its market share has been increasing year by year due to its high-speed serial interface and high-speed anti-interference characteristics, and it has gradually become the mainstream embedded memory of consumer mobile terminals and car media. However, due to the early convention of the UFS packaging industry, some UFS products are incompatible in packaging between generations. This problem is reduced in the latest UFS 4.0 and UFS 3.X, but there is still a situation that UFS 3.X cannot be used compatibly in packaging with the mainstream product UFS 2.X.

[0003] Taking the UFS product specification of the BGA153 packaging of some manufacturers as an example: UFS 2.X includes two power input networks of a first power network (VCC) and a second power network (VCCQ2), the VCC voltage range is greater than 2.7V and less than 3.6V, and the VCCQ2 voltage range is greater than 1.7V and less than 1.95V; UFS 3.X includes two power input networks of the first power network VCC and the third power network (VCCQ), the VCC voltage range is greater than 2.4V and less than 2.7V, and the VCCQ2 voltage range is greater than 1.14V and less than 1.26V; there is a situation that the VCC network is the same voltage and the VCCQ2 and VCC networks are different between UFS 2.X and UFS 3.X. Due to the above reasons, the traditional UFS 2.X and UFS 3.X cannot be used compatibly, which is easy to cause waste of matching for UFS upstream and downstream application businesses.

[0004] Therefore, it is necessary to design a memory compatible with multiple generations of UFS industry standards to shorten the industry research and development material cycle. CONTENT OF THE INVENTION

[0005] The purpose of the present application is to provide a universal flash memory storage circuit and a universal flash memory that are compatible with multiple power networks.

[0006] The application discloses a general flash memory circuit, which is adapted to a UFS protocol and has the characteristics that it comprises a first power supply network, a second power supply network, a third power supply network, a voltage reduction module, a master control unit and a flash memory unit; the master control unit is used for bridging a host computer and the flash memory unit and is used for controlling and managing the erasing, writing and reading operations of the flash memory unit; the flash memory unit is used for storing user data; the input end of the voltage reduction module is connected to the first power supply network or / and the second power supply network; the output end of the voltage reduction module is respectively connected to the flash memory unit, the master control unit and the third power supply network; and the voltage of the output end of the voltage reduction module is less than the voltage of the input end of the voltage reduction module.

[0007] Optionally, the voltage reduction module comprises a first voltage reduction module and a second voltage reduction module; the flash memory unit comprises a flash memory unit power supply interface and a flash memory unit input and output signal power supply interface; the first power supply network is connected to the input end of the first voltage reduction module and the input end of the second voltage reduction module respectively; the output end of the first voltage reduction module is connected to the flash memory unit power supply interface; and the output end of the second voltage reduction module is connected to the master control unit power supply interface and the flash memory unit input and output signal power supply interface.

[0008] Optionally, the voltage reduction module comprises a first voltage reduction module and a second voltage reduction module; the flash memory unit comprises a flash memory unit power supply interface and a flash memory unit input and output signal power supply interface; the input end of the first voltage reduction module is connected to the first power supply network; the output end of the first voltage reduction module is connected to the flash memory unit power supply interface; the input end of the second voltage reduction module is connected to the second power supply network; and the output end of the second voltage reduction module is connected to the master control unit power supply interface, the flash memory unit input and output signal power supply interface and the third power supply network module.

[0009] Optionally, the voltage reduction module comprises a first voltage reduction module and a second voltage reduction module; the flash memory unit comprises a flash memory unit power supply interface and a flash memory unit input and output signal power supply interface; the input end of the first voltage reduction module is connected to the first power supply network; the input end of the second voltage reduction module is connected to the second power supply network; the output end of the first voltage reduction module is connected to the flash memory unit input and output signal power supply interface; and the output end of the second voltage reduction module is respectively connected to the third power supply network and the master control unit power supply interface.

[0010] Optionally, the power supply network of the interface of the host computer comprises the first power supply network and the second power supply network.

[0011] Optionally, the power supply network of the interface of the host computer comprises the first power supply network interface and the third power supply network interface.

[0012] Optionally, the power supply voltage range of the flash memory unit power supply interface is greater than 2.4V and less than 3.6V, and the power supply voltage range of the flash memory unit input / output signal power supply interface is greater than 1.7V and less than 1.95V; the input end of the first voltage reduction module and the output end of the first voltage reduction module are formed by using gold wire binding or 0-ohm resistor surface mount shorting on the general flash memory; the second voltage reduction module is a low dropout linear regulator with an output voltage of 1.8V.

[0013] Optionally, the power supply voltage range of the flash memory unit power supply interface is greater than 2.4V and less than 2.7V, and the power supply voltage range of the flash memory unit input / output signal power supply interface is greater than 1.14V and less than 1.26V; the first voltage reduction module is a low dropout linear regulator with an output voltage of 2.5V; and the second voltage reduction module is a low dropout linear regulator with an output voltage of 1.2V.

[0014] Optionally, the power supply voltage range of the flash memory unit power supply interface is greater than 2.4V and less than 3.6V, and the power supply voltage range of the flash memory unit input / output signal power supply interface is greater than 1.7V and less than 1.95V; the first voltage reduction module is a low dropout linear regulator with an output voltage of 1.8V; and the second voltage reduction module is a low dropout linear regulator with an output voltage of 1.2V.

[0015] The application also discloses a general flash memory storage circuit.

[0016] Compared with the conventional UFS2.X and UFS3.X which cannot be used compatibly and easily cause a waste of matching solutions for UFS upstream and downstream application businesses, the general flash memory storage circuit comprises a first power supply network, a second power supply network, a third power supply network, a voltage reduction module, a master control unit and a flash memory unit, the master control unit is used for bridging a host computer and the flash memory unit, the master control unit is used for controlling and managing the erasing, writing and reading operations of the flash memory unit; the flash memory unit is used for storing user data; the input end of the voltage reduction module is connected to the first power supply network or / and the second power supply network, and the output end of the voltage reduction module is connected to the flash memory unit, the master control unit and the third power supply network respectively, wherein the voltage of the output end of the voltage reduction module is less than the voltage of the input end of the voltage reduction module, so that after power-on, the UFS interface can supply power to the flash memory unit and the master control unit through the first power supply network, the second power supply network and the voltage reduction module, can supply power to the flash memory unit through the first power supply network and the voltage reduction module, and the third power supply network can directly supply power to the flash memory unit and the master control unit, therefore, the master control unit can complete the switching of the communication state by identifying and switching the state machine through communication with the host computer, so as to realize the compatible design of UFS2.X and UFS3.X. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the accompanying drawings are only some embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without creative labor based on the accompanying drawings. In the drawings:

[0018] Figure 1 is a block diagram structure schematic diagram of the universal flash memory provided by the present application;

[0019] Figure 2 is a connection structure schematic diagram of the universal flash memory circuit provided by the first embodiment of the present application;

[0020] Figure 3 is a connection structure schematic diagram of the universal flash memory circuit provided by the second embodiment of the present application;

[0021] Figure 4 is a connection structure schematic diagram of the universal flash memory circuit provided by the third embodiment of the present application.

[0022] Wherein: 10, universal flash memory; 100, universal flash memory circuit; 110, first power network; 120, second power network; 130, third power network; 140, voltage reduction module; 141, first voltage reduction module; 142, second voltage reduction module; 150, master control unit; 160, flash memory unit; 161, flash memory unit power supply interface; 162, flash memory unit input and output signal power supply interface. DETAILED DESCRIPTION

[0023] It should be understood that the terms, specific structures and functional details disclosed herein are only for the purpose of describing specific embodiments, and are representative, but the present application can be embodied in many alternative forms, and should not be interpreted as being limited to the embodiments described herein.

[0024] In the description of the present application, the terms "first", "second" are only for the purpose of description, and should not be understood as indicating relative importance, or implying the number of the indicated technical features. Therefore, unless otherwise specified, the features limited by "first", "second" can explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. The term "includes" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof can exist or be added. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] Figure 1The block diagram of the general-purpose flash memory provided in this application is as follows: Figure 1 As shown, this application discloses a general-purpose flash memory 10, including a general-purpose flash memory circuit 100 adapted to the UFS protocol. The general-purpose flash memory circuit 100 includes a first power network 110, a second power network 120, a third power network 130, a step-down module 140, a main control unit 150, and flash memory cells 160 disposed on a general-purpose flash memory 200. The main control unit 150 is used to bridge a host computer (not shown in the figure) and the flash memory cells 160. The main control unit 150 is used to control and manage the erase, write, and read operations of the flash memory cells 160. The flash memory cells 160 are used to store user data. The input terminal of the step-down module 140 is connected to the first power network 110 and / or the second power network 120. The output terminal of the step-down module 140 is connected to the flash memory cells 160, the main control unit 150, and the third power network 130, respectively. The voltage at the output terminal of the step-down module 140 is less than the voltage at the input terminal of the step-down module 140.

[0026] Compared to traditional solutions where UFS 2.X and UFS 3.X are incompatible and easily lead to wasted resources for upstream and downstream UFS application providers, the universal flash memory storage circuit 100 of this application includes a first power network 110, a second power network 120, a third power network 130, a step-down module 140, a main control unit 150, and a flash memory unit 160. The main control unit 150 is used to bridge the host computer and the flash memory unit 160, and controls and manages the erase, write, and read operations of the flash memory unit 160; the flash memory unit 160 stores user data; the input terminal of the step-down module 140 is connected to the first power network 110 and / or the second power network 120, and the output terminal of the step-down module 140 is connected to... The flash memory unit 160, the main control unit 150, and the third power network 130 are described. The output voltage of the step-down module 140 is lower than the input voltage of the step-down module 140. Thus, after power-on, the UFS interface can supply power to the flash memory unit 160 and the main control unit 150 via the first power network 110 and the second power network 120 through the step-down module 140. It can also supply power to the flash memory unit 160 via the first power network 110 and the step-down module 140. The third power network 130 directly supplies power to the flash memory unit 160 and the main control unit 150. Therefore, the main control unit 150 communicates with the host computer, identifies and switches state machines to complete the communication state switching, thereby achieving a compatible design between UFS 2.X and UFS 3.X.

[0027] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] First embodiment:

[0029] VCC, VCCQ2, VCCQ, flash memory cell power supply interface 161 (referred to as FVCC), flash memory cell input and output signal power supply interface 162 (referred to as FVCCQ), and other power supply networks and high-speed signal lines. These signal network parts can be in the form of copper foil, strip line or via on the semiconductor package carrier board (not shown in the figure). The master control unit 150 is a flash control semiconductor die (referred to as Controller Die) supporting UFS2.X and UFS3.X specification protocols. The flash memory cell 160 is a master-controlled NAND flash die. Generally, a UFS contains one Controller Die and multiple NAND Flash Dies of the same type. LDO1 and LDO2 can be integrated on the Controller Die or be independent low-dropout linear regulator dies (referred to as LDO Die).

[0030] The above-mentioned die and other electronic materials are mounted on the top surface of the semiconductor package carrier board, and are electrically connected to the semiconductor package carrier board through the bonding process (referred to as Bonding). After the completion of Bonding, the molding process (referred to as molding) is performed to seal and shape the electronic materials. Subsequently, the solder balls are welded on the bottom surface of the semiconductor package carrier board through the ball planting process, and the packaging process of the general flash memory storage is completed. For the packaged UFS, the electrical connection with the host computer can be realized through the connector or the surface mounting process.

[0031] Figure 2 is the connection structure diagram of the general flash memory storage circuit provided by the first embodiment of the present application, like Figure 2As shown, the voltage reduction module 140 includes a first voltage reduction module 141 and a second voltage reduction module 142, the first voltage reduction module 141 can be selected as a low dropout linear regulator with an output voltage of 2.5V, and the second voltage reduction module 142 can be selected as a low dropout linear regulator with an output voltage of 1.2V, the flash memory unit 160 includes a flash memory unit power supply interface 161 and a flash memory unit input / output signal power supply interface 162, the power supply voltage range of the flash memory unit power supply interface 161 is greater than 2.4V and less than 2.7V, and the power supply voltage range of the flash memory unit input / output signal power supply interface 162 is greater than 1.14V and less than 1.26V, the first power supply network is connected to the input end of the first voltage reduction module 141 and the input end of the second voltage reduction module 142 respectively, the output end of the first voltage reduction module 141 is connected to the flash memory unit power supply interface 161, and the output end of the second voltage reduction module 142 is connected to the power supply interface of the host control unit 150 and the flash memory unit input / output signal power supply interface 162, wherein the power supply network of the interface of the host computer can only include the first power supply network 110 and the second power supply network 120, and the host computer interface can be powered by a ball grid array (BGA) to the UFS, and the ball grid array can be BGA 153, of course, the ball grid array can also be other types of packaging, as long as it is suitable for use in the flash memory circuit.

[0032] At this time, the VCC voltage range of the general flash memory 10 is greater than 2.4V and less than 3.6V, and the VCCQ2 and VCCQ networks are not defined, after power-on, the UFS interface supplies power to the FVCC of the flash memory unit 160 through VCC via LDO1, supplies power to the FVCCQ of the flash memory unit 160 and the host control unit 150 through VCC via LDO2, and the host control unit 150 completes the switching of the communication state by recognizing and switching the state machine through communication with the host computer. Among them, the FVCC specification power supply voltage range for the flash memory unit 160 is less than the VCC voltage range supplied by the host computer to the memory through the BGA. If VCC=FVCC, LDO1 is not necessary, at this time, FVCC can be connected to VCC.

[0033] Specifically, the main control unit 150 is firmware programmable, with one parameter indicating the highest communication rate level supported by the general-purpose memory. After communicating with the main control unit 150, the host computer obtains this communication rate parameter. The host computer can select instructions based on this parameter, and the main control unit 150 enters the corresponding communication rate, thus fulfilling the need for host computers with different communication rates to exchange data with the general-purpose memory, thereby achieving a compatible design between UFS 2.X and UFS 3.X. For example, the UFS 2.2 protocol supports up to HS-GEAR3, with an interface rate of up to 5830Mbps, while UFS 3.1 supports HS-GEAR3 and up to HS-GEAR4, with an interface rate of up to 11660Mbps. In terms of communication protocols, UFS is compatible with higher versions to lower versions, so this design allows higher versions of UFS to support host computer applications with lower version UFS interfaces.

[0034] Second embodiment:

[0035] Figure 3 This is a schematic diagram of the connection structure of the general flash memory storage circuit provided in the second embodiment of this application, as shown below. Figure 3 As shown, as a second embodiment of this application, this embodiment differs from the first embodiment in that the power supply voltage range of the flash memory cell power supply interface 161 is greater than 2.4V and less than 2.7V, and the power supply voltage range of the flash memory cell input / output signal power supply interface 162 is greater than 1.14V and less than 1.26V; the first step-down module 141 is a low-dropout linear regulator with an output voltage of 2.5V; the second step-down module 142 is a low-dropout linear regulator with an output voltage of 1.2V; the input terminal of the first step-down module 141 is connected to the first power network 110, and the output terminal of the first step-down module 141 is connected to the flash memory cell power supply interface 161; the input terminal of the second step-down module 142 is connected to the second power network 120, and the output terminal of the second step-down module 142 is connected to the power supply interface of the main control unit 150, the flash memory cell input / output signal power supply interface 162, and the third power network 130 module.

[0036] At this time, the general flash memory 10 defines a VCC voltage range greater than 2.4V and less than 2.7V, a VCCQ2 voltage range greater than 1.14V and less than 1.26V, LDO1=2.5V, and LD02=1.2V. In the host interface of UFS2.X, the host interface includes a first power network 110 and a second power network 120. After power-on, the host interface supplies power to the FVCC of the flash memory unit 160 through VCC via LDO1, and supplies power to the FVCCQ of the flash memory unit 160 and the host control unit 150 through VCCQ2 via LDO2. The host control unit 150 identifies and switches the state machine through communication with the host to complete the switching of the communication state for UFS2.X high-speed communication. In the host interface of UFS3.X, the host interface can only include a first power network 110 VCC and a third power network 130 VCCQ. After power-on, the host interface supplies power to the FVCC of the flash memory unit 160 through VCC via LDO1, and supplies power to the FVCCQ of the flash memory unit 160 and the host control unit 150 directly through VCCQ. The host control unit 150 identifies and switches the state machine through communication with the host to complete the switching of the communication state for UFS3.X high-speed communication, thereby realizing the compatible design of UFS2.X and UFS3.X.

[0037] Third embodiment:

[0038] Figure 4 is a connection structure schematic diagram of the general flash memory circuit provided by the third embodiment of the present application, as shown in Figure 4 As the second embodiment of the present application, the embodiment is different from the first and second embodiments in that the power supply voltage range of the flash memory unit power supply interface 161 is greater than 2.4V and less than 3.6V, and the power supply voltage range of the flash memory unit input and output signal power supply interface 162 is greater than 1.7V and less than 1.95V; the first voltage reduction module 141 is a low dropout linear regulator with an output voltage of 1.8V; the second voltage reduction module 142 is a low dropout linear regulator with an output voltage of 1.2V, the input end of the first voltage reduction module 141 is connected to the first power network 110, the input end of the second voltage reduction module 142 is connected to the second power network 120, the output end of the first voltage reduction module 141 is connected to the flash memory unit input and output signal power supply interface 162, and the output end of the second voltage reduction module 142 is connected to the third power network 130 and the host control unit 150 for power supply, respectively.

[0039] At this time, the general flash memory 10 defines a VCC voltage range greater than 2.4V and less than 3.6V, a VCCQ2 voltage range greater than 1.7V and less than 1.95V, LDO1=1.8V, and LD02=1.2V. In the host interface of UFS2.X, after power-on, the interface directly supplies power to the flash memory unit 160FVCC through VCC, VCC supplies power to the flash memory unit 160FVCCQ through LDO1, VCCQ2 supplies power to the control unit 150 through LDO2, and the control unit 150 identifies and switches the state machine through communication with the host to complete the switching of the communication state for UFS2.X high-speed communication; in the host interface of UFS3.X, after power-on, the interface directly supplies power to the flash memory unit 160FVCC through VCC, VCC supplies power to the flash memory unit 160FVCCQ through LDO1, VCCQ directly supplies power to the control unit 150, and the control unit 150 identifies and switches the state machine through communication with the host to complete the switching of the communication state for UFS3.X high-speed communication, thereby realizing the compatible design of UFS2.X and UFS3.X.

[0040] Wherein, if VCC=FVCCQ, LDO1 is not necessary, at this time, FVCCQ can be connected with VCC.

[0041] Of course, the above voltage range of VCC, the voltage range of VCCQ2, and the voltage of LDO1 and LDO2 are only limited to the embodiments, and corresponding voltage values can also be selected as needed to realize the design required by compatibility, which is not limited herein.

[0042] It should be noted that the inventive concept of the present application can form a very large number of embodiments, but the length of the application file is limited and cannot be listed one by one, therefore, on the premise of not conflicting, the above-described embodiments or technical features can be combined to form new embodiments, and the combination of each embodiment or technical feature will enhance the original technical effect.

[0043] The above is a further detailed description of the present application in combination with specific optional embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be regarded as falling within the protection scope of the present application.

Claims

1. A universal flash memory storage circuit adapted to a UFS protocol, characterized in that, The application relates to a flash memory unit and a power supply network thereof.

2. The universal flash memory storage circuit of claim 1, wherein, The flash memory unit comprises a flash memory unit power supply interface and a flash memory unit input / output signal power supply interface; the input end of the first voltage reduction module is connected with the first power supply network; the output end of the first voltage reduction module is connected with the flash memory unit power supply interface; the input end of the second voltage reduction module is connected with the second power supply network; and the output end of the second voltage reduction module is connected with the master control unit power supply interface, the flash memory unit input / output signal power supply interface and the third power supply network module.

3. The universal flash memory storage circuit of claim 1, wherein, The flash memory unit comprises a flash memory unit power supply interface and a flash memory unit input / output signal power supply interface; the input end of the first voltage reduction module is connected with the first power supply network; the output end of the first voltage reduction module is connected with the flash memory unit power supply interface; the input end of the second voltage reduction module is connected with the second power supply network; and the output end of the second voltage reduction module is connected with the master control unit power supply interface, the flash memory unit input / output signal power supply interface and the third power supply network module.

4. The universal flash memory storage circuit of claim 1, wherein, The flash memory unit comprises a flash memory unit power supply interface and a flash memory unit input / output signal power supply interface; the input end of the first voltage reduction module is connected with the first power supply network; the output end of the first voltage reduction module is connected with the flash memory unit power supply interface; the input end of the second voltage reduction module is connected with the second power supply network; and the output end of the second voltage reduction module is connected with the master control unit power supply interface, the flash memory unit input / output signal power supply interface and the third power supply network module.

5. The universal flash memory storage circuit according to claim 2 or 3 or 4, characterized in that, The power supply network of the interface of the host computer comprises the first power supply network and the second power supply network.

6. The universal flash memory storage circuit according to claim 2 or 3 or 4, wherein, The power supply network of the interface of the host computer comprises the first power supply network interface and the third power supply network interface.

7. The universal flash memory storage circuit of claim 2, wherein, The power supply voltage range of the flash memory unit power supply interface is greater than 2.4V and smaller than 3.6V, and the power supply voltage range of the flash memory unit input / output signal power supply interface is greater than 1.7V and smaller than 1.95V; the input end of the first voltage reduction module and the output end of the first voltage reduction module are formed by gold wire binding or 0 ohm resistance surface mount shorting on a general flash memory; and the second voltage reduction module is a low-dropout linear voltage regulator with an output voltage of 1.8V.

8. The universal flash memory storage circuit of claim 3, wherein, The power supply voltage range of the flash memory unit power supply interface is greater than 2.4V and less than 2.7V, and the power supply voltage range of the flash memory unit input / output signal power supply interface is greater than 1.14V and less than 1.26V; the first voltage reduction module is a low dropout linear regulator with an output voltage of 2.5V; and the second voltage reduction module is a low dropout linear regulator with an output voltage of 1.2V.

9. The universal flash memory storage circuit of claim 4, wherein, The power supply voltage range of the flash memory unit power supply interface is greater than 2.4V and less than 3.6V, and the power supply voltage range of the flash memory unit input / output signal power supply interface is greater than 1.7V and less than 1.95V; the first voltage reduction module is a low dropout linear regulator with an output voltage of 1.8V; and the second voltage reduction module is a low dropout linear regulator with an output voltage of 1.2V.

10. A universal flash memory, characterized by, The universal flash memory storage circuit as claimed in any one of claims 1-9 is adopted.

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