VCSEL chip

Abstract

The utility model provides a VCSEL chip, and relates to the technical field of semiconductors, the VCSEL chip comprises a substrate, an N-type distributed Bragg reflector, a multi-quantum well layer, a P-type distributed Bragg reflector, a contact layer, a thin film oxide layer and a metal contact layer which are stacked from bottom to top, the metal contact layer comprises a P metal contact region, the P metal contact region is an annular region, and the P metal contact region is provided with an annular region. Current is injected into a light-emitting hole in the center of the annular region through the periphery of the annular region; the metal contact layer further comprises an N metal contact area, and the N metal contact area encloses the P metal contact area. Through the annular P metal contact area, current is injected from the peripheral direction of the annular P metal contact area, compared with single-direction current injection in the prior art, the current path is improved, the more stable current injection characteristic is achieved, heat accumulation caused by single-direction current injection is improved, stray capacitance of an electrode and a metal contact layer area is reduced, and the reliability of the device is improved. The etching platform is reduced, the oxidation area is reduced, the device reliability is increased, and the device characteristics are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a VCSEL chip. BACKGROUND

[0002] For high-speed VCSEL (Vertica l-Cavity Surface-Emitt i ng Laser), the biggest problem is the current injection caused by parasitic capacitance, and the parasitic capacitance is generally generated at the electrode and metal contact layer, p-n junction, and active region. The parasitic capacitance generated by the electrode and the contact surface has the most severe impact, affecting the reliability of the device. CONTENT

[0003] The embodiment of the present application aims to provide a VCSEL chip which can reduce the parasitic capacitance of the electrode and metal contact layer area and improve the reliability of the device.

[0004] In one aspect of the embodiment of the present application, a VCSEL chip is provided, comprising: a substrate, an N-type distributed Bragg reflector, a multi-quantum well layer, a P-type distributed Bragg reflector, a contact layer, a thin film oxide layer and a metal contact layer which are stacked from bottom to top, the metal contact layer comprises a P-metal contact area, the P-metal contact area is an annular area, and current is injected into the light emitting hole in the center of the annular area through the periphery of the annular area; the metal contact layer further comprises an N-metal contact area, and the N-metal contact area encloses the P-metal contact area.

[0005] Optionally, the P-metal contact area comprises a first P-metal contact area and a second P-metal contact area, both the first P-metal contact area and the second P-metal contact area are annular areas, and the first P-metal contact area is arranged in the second P-metal contact area.

[0006] Optionally, a P-electrode is formed outside the P-metal contact area, the P-electrode is an annular electrode, and a plurality of annularly distributed channels are formed between the P-electrode and the P-metal contact area for injecting current.

[0007] Optionally, the N-metal contact area comprises a first N-metal contact area and a second N-metal contact area, the first N-metal contact area and the second N-metal contact area are oppositely arranged to form an enclosed area, and the P-metal contact area is located in the enclosed area.

[0008] Optionally, the first N-metal contact area and the second N-metal contact area are connected by an N-electrode.

[0009] Optionally, the P metal contact region is connected with the P type distributed Bragg reflector, and the N metal contact region is connected with the N type distributed Bragg reflector.

[0010] Optionally, the metal contact layer comprises a buffer layer, a transition layer and a metal layer stacked from bottom to top.

[0011] Optionally, the buffer layer, the transition layer and the metal layer are titanium layer, platinum layer and gold layer respectively.

[0012] The VCSEL chip provided by the embodiment of the present application, the P metal contact region forms a ring-shaped region, and the center of the ring-shaped region is the light emitting hole. By setting the ring-shaped P metal contact region, the current can be injected from the four directions of the ring-shaped P metal contact region. Compared with the single direction current injection in the prior art, the current injection in the four directions can improve the current path, achieve more stable current injection characteristics, improve the heat accumulation caused by the single direction current injection, reduce the parasitic capacitance of the electrode and the metal contact layer region, reduce the etching platform, further reduce the oxidation area, increase the reliability of the device, and improve the characteristics of the device. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0014] Figure 1 is a schematic diagram of the VCSEL chip structure provided by the embodiment of the present application;

[0015] Figure 2 is a schematic diagram of the metal contact layer structure of the VCSEL chip provided by the embodiment of the present application;

[0016] Figure 3 is a top view of Figure 1 ;

[0017] Figure 4 is a current injection diagram of Figure 3 .

[0018] Icon: 10 - substrate; 11 - N-type distributed Bragg reflector; 12 - multiple quantum well layer; 13 - P-type distributed Bragg reflector; 14 - contact layer; 15 - thin-film oxide layer; 16 - metal contact layer; 161 - buffer layer; 162 - transition layer; 163 - metal layer; 16P.1 - first P-metal contact region; 16P.2 - second P-metal contact region; 16P.3 - P-electrode; 16N.1 - first N-metal contact region; 16N.2 - second N-metal contact region; 16N.3 - N-electrode; 16a - channel; 16b - light exit hole; S - recombination region. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0020] In the description of the present application, it should be noted that the positions or location relationships indicated by the terms "inner", "outer" and the like are based on the positions or location relationships shown in the drawings, or the positions or location relationships in which the products of the present application are usually placed, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular position, be constructed and operated in a particular position, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" and the like are only used for differentiation in description and cannot be understood as indicating or implying relative importance.

[0021] It should also be noted that, unless otherwise explicitly specified and limited, the terms "provided", "connected" should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be directly connected, or indirectly connected through an intermediate medium; can be connected inside two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0022] Please refer to Figure 1 and Figure 3 It is shown that the present application provides a VCSEL chip, which comprises: a substrate 10, an N-type distributed Bragg reflector 11, a multiple quantum well layer 12, a P-type distributed Bragg reflector 13, a contact layer 14, a thin-film oxide layer 15 and a metal contact layer 16 which are stacked from bottom to top, the metal contact layer 16 comprises a P-metal contact region, the P-metal contact region is an annular region, and current is injected into a light exit hole 16b in the center of the annular region through the periphery of the annular region; the metal contact layer 16 further comprises an N-metal contact region, which encloses the P-metal contact region.

[0023] The substrate 10, the N-type distributed Bragg reflector 11, the multiple quantum well layer 12, the P-type distributed Bragg reflector 13, the contact layer 14, the thin-film oxide layer 15 and the metal contact layer 16 are sequentially stackedFigure 1 The VCSEL chip shown.

[0024] The thin film oxide layer 15 can be a silicon nitride layer. The P-type distributed Bragg reflector 13 includes 20 to 25 reflector layers (dielectric thin film), and the N-type distributed Bragg reflector 11 includes 30 to 35 reflector layers, for different applications.

[0025] Figure 2 for Figure 1 Top view, in Figure 2 In the metal contact layer 16, a metal contact area is formed, which includes a P metal contact area and an N metal contact area. The N metal contact area is disposed along the edge of the metal contact layer 16 and surrounds the P metal contact area inside it.

[0026] The P-metal contact area is also connected to the P-type distributed Bragg reflector 13, and the N-metal contact area is connected to the N-type distributed Bragg reflector 11.

[0027] In this design, the P-metal contact area forms an annular region, with the light-emitting aperture 16b at its center. By setting the annular P-metal contact area, current can be injected from all four directions. Compared to the single-direction current injection in the prior art, this application can inject current from all four directions, improving the current path and achieving more stable current injection characteristics. This also improves the heat accumulation caused by single-direction current injection, reduces the parasitic capacitance between the electrode and the metal contact layer 16, shrinks the etching platform, further reduces the oxidation area, increases the reliability of the device, and enhances the device characteristics.

[0028] Specifically, the P-metal contact area includes a first P-metal contact area 16P.1 and a second P-metal contact area 16P.2. Both the first P-metal contact area 16P.1 and the second P-metal contact area 16P.2 are annular areas, and the first P-metal contact area 16P.1 is located within the second P-metal contact area 16P.2.

[0029] The first P-metal contact area 16P.1 is fitted inside the second P-metal contact area 16P.2. Current is injected from the circumference of the ring through the first P-metal contact area 16P.1 and the second P-metal contact area 16P.2 in sequence, which can enhance the stability of current injection.

[0030] A P-electrode 16P.3 is formed outside the P-metal contact area. The P-electrode 16P.3 is a ring electrode. Multiple circumferentially distributed channels 16a are formed between the P-electrode 16P.3 and the P-metal contact area for injecting current.

[0031] For example, the application is provided with four channels 16a, which are evenly distributed along the annular circumference, so that the current can be injected through the four-directional channels 16a to obtain stable current injection characteristics.

[0032] The N metal contact region includes a first N metal contact region 16N.1 and a second N metal contact region 16N.2, which are oppositely arranged to form an enclosed region, and the P metal contact region is located in the enclosed region. The first N metal contact region 16N.1 and the second N metal contact region 16N.2 are connected by an N electrode 16N.3.

[0033] The P metal contact region and the P electrode 16P.3 are located in the enclosed region, and the N metal contact region formed by the first N metal contact region 16N.1 and the second N metal contact region 16N.2 forms an enclosed tendency to the P metal contact region and the P electrode 16P.3, which cooperates with the P metal contact region and the P electrode 16P.3 to realize the required function of the device.

[0034] In addition, as shown in Figure 2 The metal contact layer 16 includes a buffer layer 161, a transition layer 162 and a metal layer 163 stacked from bottom to top. The buffer layer 161, the transition layer 162 and the metal layer 163 are titanium layer, platinum layer and gold layer respectively.

[0035] The application extends the P metal contact region and the N metal contact region as much as possible, and the thickness of the P metal contact region and the N metal contact region is changed. The titanium layer as the buffer layer 161 needs to increase the thickness of the titanium layer so that the gold material of the gold layer with higher density is not easy to rush into the wafer surface, causing more capacitance to be generated. The electrode manufacturing needs to be designed by simulating the current introduction amount. Because the operating current of the high-speed VCSEL is small, the gold wire thickness and the electrode size can be greatly reduced to control the capacitance. The etching platform uses multiple etching technology to make the active region (multi-quantum well layer 12) and the thin film oxide layer 15 produce a secondary plane, so that the plane area is reduced again to achieve the advantage of reducing the capacitance.

[0036] In summary, the VCSEL chip of the application improves the device characteristics and improves the parasitic capacitance by improving the current injection method. For a single VCSEL, four-point partitioning (first P metal contact region 16P.1, second P metal contact region 16P.2 / first N metal contact region 16N.1, second N metal contact region 16N.2) is adopted, and the current flows from the electrode in four directions into the P metal contact region, so that the original large-area capacitance is split, and the area of the P metal contact region and the N metal contact region is lengthened, so that the electrode does not need to be enlarged to make contact, thereby reducing the contact surface capacitance, and reducing the size of the etching platform, reducing the active region capacitance, and increasing the area of the P metal contact region and the N metal contact region in the recombination region S. Figure 4 ​

[0037] It is noted that the position of the electrode simulation is very important to the current introduction amount, and thus the relative position of the four-point electrode is particularly important. The extension of the metal contact region needs to consider the expansion due to the thermal effect of operation, and the metal will be broken due to the stress, and the extension metal (the P metal contact region and the N metal contact region) is more prone to this phenomenon. In addition, the etching platform size and the multiple etching gas amount need to be controlled stably, and the diffraction limit of the exposure machine platform needs to be considered, so that the design of reducing the plane to reduce the capacitance can be completed.

[0038] The above only describes the embodiments of the present application and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A VCSEL chip, characterized by, The application relates to a light-emitting diode, which comprises a substrate, an N-type distributed Bragg reflector, a multi-quantum well layer, a P-type distributed Bragg reflector, a contact layer, a thin-film oxide layer and a metal contact layer arranged in a stack from bottom to top, wherein the metal contact layer comprises a P-metal contact region, the P-metal contact region is an annular region, current is injected into a light-emitting hole in the center of the annular region through the periphery of the annular region, and the metal contact layer further comprises an N-metal contact region, which encloses the P-metal contact region. The P-metal contact region comprises a first P-metal contact region and a second P-metal contact region, both of which are annular regions, and the first P-metal contact region is arranged in the second P-metal contact region.

2. The VCSEL chip of claim 1, wherein, A P electrode is formed outside the P-metal contact region, the P electrode is an annular electrode, a plurality of annularly distributed channels are formed between the P electrode and the P-metal contact region for injecting current.

3. The VCSEL chip of claim 2, wherein, The N-metal contact region comprises a first N-metal contact region and a second N-metal contact region, and the first N-metal contact region and the second N-metal contact region are oppositely arranged to form an enclosed region, and the P-metal contact region is located in the enclosed region.

4. The VCSEL chip of claim 1, wherein, The first N-metal contact region and the second N-metal contact region are connected by an N electrode.

5. The VCSEL chip of claim 4, wherein, The metal contact layer comprises a buffer layer, a transition layer and a metal layer arranged in a stack from bottom to top.

6. The VCSEL chip according to any one of claims 1 to 5, characterized in that, The buffer layer, the transition layer and the metal layer are respectively a titanium layer, a platinum layer and a gold layer.

7. The VCSEL chip of claim 6, wherein, The P-metal contact region is connected with the P-type distributed Bragg reflector, and the N-metal contact region is connected with the N-type distributed Bragg reflector.

8. The VCSEL chip according to any one of claims 1 to 5, characterized in that, ​

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