Deviation self-correcting circuit and sectional current steering DAC (Digital-to-Analog Converter)

Abstract

The utility model discloses a deviation self-correcting circuit, which comprises a time sequence adjusting array, a comparison module, a latch module and a decoding module, and is characterized in that a binary weighted current source array is delayed by different degrees through the time sequence adjusting array; then a comparison module is used for comparing the adjusted signal with a first control signal, a gear switch corresponding to the minimum deviation of the two control signals is selected, a latch module is used for latching the comparison result and outputting the comparison result to a decoding module, the decoding module converts the voltage signal into a binary code and then provides the binary code to a time sequence adjusting array, and the time sequence adjusting array is used for adjusting the time sequence. The switch is used for controlling on-off of the switch. The utility model also provides a sectional type current steering DAC using the deviation self-correcting circuit, and by correcting the deviation between control signals, burrs generated by ramp signals are avoided, and the linearity is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to digital analog converter technical field, concretely relates to a kind of deviation self-correcting circuit of reducing time sequence control deviation, improve linearity and current steering type DAC by the circuit composition. BACKGROUND

[0002] The current source array in the common segmented current steering type DAC is composed of binary weighted current source array and thermometer decoding current source array, wherein, binary weighted type controls low bit digital code, and thermometer decoding type controls high bit digital code.In actual circuit design, in order to improve yield, the matching of current source array timing must be ensured under PVT (Process, Voltage, Temperature) condition, and this will bring great difficulty to circuit and layout design.When the timing of current source array exists deviation, it leads to generate spur pulse, further influence the linearity of reference ramp voltage.

[0003] Figure 2 The mutual influence of reference ramp signal RAMP and current source array timing control signal is shown, as shown in the figure, reference ramp signal RAMP is DAC output ramp voltage, first control signal is the timing control signal of the lowest bit of thermometer decoding current source array, second control signal is the timing control signal of the highest bit of binary weighted current source array, and third control signal is the timing control signal of the second highest bit of binary weighted current source array.When deviation exists between third control signal and second control signal (as shown in Figure 2 201), the deviation will cause reference ramp signal to generate spur pulse (as shown in Figure 2 203), the generation of the spur is due to the mismatch of timing control jump of binary weighted current source array.Similarly, when deviation exists between third control signal and first control signal (as shown in Figure 2 202), the deviation will cause reference ramp signal to generate spur pulse (as shown in Figure 2 204), since the number of current sources controlled by first control signal is more, the energy of generated spur pulse is also larger, and the influence on ramp signal is also larger.The mutual influence between these current source array control signals will eventually affect the linearity of reference ramp signal, when such ramp signal is introduced into image sensor to be used for quantizing pixel signal, it will affect quantization value, and finally reduce picture quality.Therefore, it is of great significance to study how to reduce the timing deviation of binary weighted current source array and thermometer decoding current source array, avoid generating spur, and solve the nonlinearity problem of reference ramp signal.

[0004] The patent application with the publication number CN104617953A proposes a calibration system for current source array in segmented current steering digital-to-analog converter. The technical problem solved by the application is that, due to the influence of process deviation, there is deviation and mismatch among the current source arrays, so that the current flowing to the current source array has deviation compared with the theoretical value. The scheme compensates the deviation and mismatch among the current source arrays by adding a series of compensation circuits, such as external test circuit, calibration circuit, calibration storage unit, etc., to compensate the deviation between the actual value and the theoretical value of the current source array caused by the deviation and mismatch among the current source arrays, so that the size of each current source in the binary-coded current source array is in binary proportional relationship, and the size of each current source in the thermometer-coded current source array is the same, thereby achieving the purpose of improving linearity. The defect of the scheme is that the added circuits are more, which leads to the increase of layout area and cost.

[0005] The patent application with the publication number CN102025374A proposes an automatic calibration circuit for real-time correction of differential non-linear error of digital-to-analog converter, which is used for improving the linearity of DAC. The circuit is increased with calibration DAC, application DAC, summing amplifier, controller and other circuits. However, due to the complex structure of these circuits and the large layout area, although the linearity can be improved, the area is greatly increased. In the current trend of chip area compression, the increase of DAC circuit area will not meet the product application requirements. SUMMARY

[0006] TECHNICAL PROBLEM

[0007] For the segmented current steering DAC, there is timing deviation between different control signals of the output, which leads to the generation of glitch pulse in the generated reference ramp signal, thereby affecting the linearity.

[0008] The utility model discloses a segmented current steering DAC capable of correcting timing deviation of current source array, which can reduce the deviation between the control signals of the current source array and improve the linearity of the reference ramp signal by introducing a self-correcting circuit.

[0009] SOLUTION TO THE TECHNICAL PROBLEM

[0010] The utility model provides a circuit capable of correcting timing deviation of current source array, and the deviation self-correcting circuit comprises:

[0011] A timing adjustment array is used to adjust the delay amount of the initial control signal V_IN of the binary-weighted current source array, and a plurality of gear adjustment switches are set to make the signal delay amount corresponding to each gear increase;

[0012] A comparison module compares the first control signal with the signals V_OUT1 corresponding to each gear after being adjusted by the timing adjustment array, and selects the gear switch corresponding to the minimum deviation between the two control signals.

[0013] a latch module for latching the result outputted by the comparison module and providing the result to the decoding module at the same time;

[0014] the decoding module decodes the result outputted by the comparison module into binary code, and the timing adjustment array controls the opening of the switch by identifying the binary code.

[0015] Further, the timing adjustment array comprises N branches, each branch is composed of the same number of inverters INV and a control switch S in series, and the inverters in each branch are in series, the input signal V_IN is connected to the input end of the first branch, the output end of the first branch is connected to the input end of the second branch and the input end of the first control switch S1 of the first branch at the same time, and the rest of the branches are the same, the output ends of the first control switch S1, the second control switch S2 and the Nth control switch SN are connected in parallel to output the signal V_OUT1. N

[0016] Further, the comparison module is in the structure of D flip-flop, the D end of the D flip-flop is connected to the output signal V_OUT1 of the timing adjustment array, the CLK end is connected to the first control signal, and the Q end outputs the signal V_OUT2.

[0017] Further, the latch module is composed of N D flip-flops, the D end of each D flip-flop is connected to the output signal V_OUT2 of the comparison module, and the CLK end is connected to the clock signal CLK_IN <n-1:0>, Q end output signal V_OUT3, the output signal of each D flip-flop is merged and the final output signal V_OUT3 <n-1:0>.

[0018] Further, the decoding module comprises N parallel branches, the first branch is composed of three inverters connected in series, the second branch to the (N-1)th branch are each composed of two inverters and an NOR gate, one input terminal of the NOR gate is connected to the output terminal of the inverter connected in series in the branch, the other input terminal of the NOR gate is connected to the output terminal of the first inverter in the previous branch, and the output signals of the branches are combined and output as a signal V_OUT4 <n-1:0>.

[0019] In another aspect, the utility model provides an improved segmented current steering type DAC, including the deviation self correcting circuit, high bit digital code and low bit digital code, thermometer decoding circuit, latch, current source array, voltage conversion current circuit and band gap reference voltage source.

[0020] Beneficial effect

[0021] Compared with the current existing current steering type DAC, the utility model reduces the deviation between the timing control signals through the introduction of deviation self correcting circuit, thereby avoid the DAC output ramp signal to produce burr, improve the linearity of ramp signal. BRIEF DESCRIPTION OF DRAWINGS

[0022] The drawings provided here are used to further illustrate the embodiments of the utility model, so as to facilitate understanding, and do not constitute the limitation to the embodiments of the utility model.

[0023] Figure 1 It is the structure schematic drawing of the utility model deviation self correcting circuit;

[0024] Figure 2 It is the structure schematic drawing of timing adjustment array in the utility model deviation self correcting circuit;

[0025] Figure 3 It is the structure schematic drawing of comparison module in the utility model deviation self correcting circuit;

[0026] Figure 4 It is the structure schematic drawing of latch module in the utility model deviation self correcting circuit;

[0027] Figure 5 It is the structure schematic drawing of decoding module in the utility model deviation self correcting circuit;

[0028] Figure 6 It is the structure schematic drawing of the utility model improved segmented current steering type DAC;

[0029] Figure 7 It is the schematic diagram of the influence of the deviation of control signal of current source array in the DAC before improvement on ramp signal. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical scheme and advantages of the utility model more clearly, the utility model will be further described in detail below in combination with examples and drawings, the schematic implementation mode of the utility model and its description are only used to explain the utility model, and do not serve as the limitation of the utility model. In order to be brief, the technology known in the art will not be described in this paper, and if there are processes not specially described in detail, they are realized by the prior art by the person skilled in the art.

[0031] In the existing DAC design, the deviation in the timing of the control signals of the current source array will cause glitches in the final output ramp signal, affecting the linearity. The DAC outputs a ramp voltage signal RAMP, the first control signal is the timing control signal of the lowest bit of the thermometer decoding type current source array (denoted by signal A in this paper), the second control signal is the timing control signal of the highest bit of the binary weighted type current source array (denoted by signal B in this paper), and the third control signal is the timing control signal of the second highest bit of the binary weighted type current source array (denoted by signal C in this paper). When there is a deviation between the third control signal and the second control signal (as shown in 201), the deviation will cause glitches in the reference ramp signal (as shown in 203), and the glitches are caused by the mismatch in the timing control of the binary weighted type current source array. Similarly, when there is a deviation between the third control signal and the first control signal (as shown in 202), the deviation will cause glitches in the reference ramp signal (as shown in 204), and the number of current sources controlled by the first control signal is large, so the energy of the generated glitches is also large, and the influence on the ramp signal is also large. The mutual influence between the control signals of these current source arrays will eventually affect the linearity of the reference ramp signal, and when such a ramp signal is introduced into an image sensor to quantize the pixel signal, the quantization value will be affected, and the image quality will be ultimately reduced. Figure 2 Figure 2 Figure 2 Figure 2

[0032] Figure 1 The structure of the deviation self-correction circuit of the utility model is shown, as shown in the figure, the deviation self-correction circuit comprises a timing adjustment array, a comparison module, a latch module and a decoding module.

[0033] The timing adjustment array is used to adjust the delay amount of the initial control signal V_IN of the binary weighted type current source array, and the signal delay amount corresponding to each gear is increased by setting a plurality of gear adjustment switches.

[0034] ​​​​The comparison module compares the first control signal signal A with the signals V_OUT1 corresponding to each gear of the timing adjustment array respectively, and selects the gear switch corresponding to the minimum deviation between the two control signals.

[0035] The latch module is used for latching the output result of the comparison module and simultaneously providing the result to the decoding module.

[0036] The decoding module decodes the output result of the comparison module into a binary code, and the timing adjustment array controls the opening of the switch by identifying the binary code.

[0037] The utility model discloses an improvement on the prior art, which provides a deviation self-correction circuit capable of delaying the initial control signal of a binary weighted current source array to different degrees, and then comparing the delayed control signal with a first control signal to output a control signal of the binary weighted current source array with the minimum deviation from the first control signal.

[0038] For the convenience of understanding, the following will illustrate the deviation self-correction steps by way of example:

[0039] Step 1: input the initial control timing V_IN of the binary weighted current source array into the timing adjustment array;

[0040] Step 2: connect the gating switch 401 to the A end to enter the deviation self-correction state, at this time, the A end successively opens each gear switch of the timing adjustment array to realize the delay of the control signal of the binary weighted current source array, for example, design 8 gear switches, and the difference between the delay amounts of the control signals of each gear is 100 ps.

[0041] Step 3: connect the gating switch 402 to the C end to compare each gear control signal output by the timing adjustment array with the first control signal, for example, if the comparison result is HHHLLLLL, it indicates that when only the first gear switch of the timing adjustment array is opened, the comparison result of the two control signals is high (H), and similarly, when only the third gear switch is opened, the comparison result is high (H), and when only the fourth gear switch is opened, the comparison result is low (L).

[0042] Step 4: convert the comparison result into a binary code recognizable by the timing adjustment array through the decoding module, for example, decode the above comparison result HHHLLLLL into 00010000, and after the decoding is completed, the deviation self-correction ends.

[0043] Step 5: connect the gating switch 401 to the B end to start entering the normal digital-to-analog conversion state, and the decoding module outputs the decoded result to the timing adjustment array to control the opening of the optimal gear switch.

[0044] Step 6: connecting the strobe switch 402 to the D terminal, outputting the control signal V_OUT of the binary weighted current source array with the minimum deviation from the first control signal after adjustment.

[0045] The timing adjustment array is a circuit capable of adjusting the signal delay as required. As a possible structure, as shown in Figure 2 , the timing adjustment array includes a first branch, a second branch, and an Nth branch, each branch is composed of the same number of inverters INV and a control switch S in series, and the inverters of each branch are connected in series. The input signal V_IN is connected to the input terminal of the first branch, the output terminal of the first branch is connected to the input terminal of the second branch and the input terminal of the first control switch S1 of the first branch, and the rest of the branches are the same. The output terminals of the first control switch S1, the second control switch S2, and the Nth control switch SN are connected in parallel to output the signal V_OUT1. N

[0046] It should be noted that the timing adjustment array can only open one control switch at a time, and different delay amounts of signals can be output by opening different gear switches.

[0047] A possible structure of the comparison module is shown in Figure 3 , which uses a D flip-flop structure. The D terminal of the D flip-flop is connected to the output signal V_OUT1 of the timing adjustment array, the CLK terminal is connected to the first control signal, and the Q terminal outputs the signal V_OUT2.

[0048] A possible structure of the latch module is shown in Figure 4 , which is composed of N D flip-flops. The D terminal of each D flip-flop is connected to the output signal V_OUT2 of the comparison module, and the CLK terminal is connected to the clock signal CLK_IN <n-1:0>, Q end output signal V_OUT3, the output signal of each D flip-flop is merged and the final output signal V_OUT3 <n-1:0>.

[0049] A possible structure of the decoding module is shown in Figure 5 Fig. 2, which comprises N parallel branches, the first branch consisting of three inverters connected in series, the second to (N-1)th branches each consisting of two inverters and an NOR gate, one input of the NOR gate being connected to the output of the inverter in series in the branch, the other input of the NOR gate being connected to the output of the first inverter in the preceding branch, the output signals of the branches being combined to output the signal V_OUT4 <n-1:0>.

[0050] Figure 6 The structure of the improved segmented current steering type DAC is shown, as shown in the figure, the segmented current steering type DAC comprises high bit digital code and low bit digital code, a thermometer decoding circuit, a latch, a deviation self-correcting circuit, a current source array, a voltage-to-current circuit and a band gap reference voltage source.

[0051] By introducing the deviation self-correcting circuit, the timing deviation of both the binary weighted type current source array and the thermometer decoding type current source array is reduced, such as being reduced to within 100 ps, thereby eliminating glitches of the ramp signal and improving the DAC linearity. When the improved segmented current steering type DAC is used in an image sensor, the image quality can be improved.

[0052] The above specific embodiments further explain the purpose, technical scheme and beneficial effects of the utility model, and it should be understood that the above description is only a specific embodiment of the utility model, and is not used to limit the protection scope of the utility model, and any modification, equivalent replacement, improvement, etc. within the spirit and principle of the utility model should be included in the protection scope of the utility model. ​ ​

Claims

1. A bias self-correcting circuit, characterized by, The correction circuit comprises: a timing adjustment array for adjusting the delay amount of the initial control signal V_IN of the binary-weighted current source array, and a plurality of gear adjustment switches are arranged to make the signal delay amount of each gear increase; a comparison module for comparing the first control signal with the signal V_OUT1 corresponding to each gear after being adjusted by the timing adjustment array, and selecting the gear switch corresponding to the minimum deviation between the two control signals; a latch module for latching the output result of the comparison module and simultaneously providing the result to a decoding module; the decoding module decodes the output result of the comparison module into a binary code, and the timing adjustment array identifies the binary code to control the opening of the switch.

2. The offset self-correcting circuit of claim 1, wherein, The timing adjustment array comprises N branches, each branch is composed of the same number of inverters INV and a control switch S in series, and the inverters of each branch are in series, the input signal V_IN is connected to the input end of the first branch, the output end of the first branch is connected to the input end of the second branch and the input end of the control switch S1 of the first branch at the same time, and the rest of the branches are the same, the output ends of the first control switch S1, the second control switch S2 and the Nth control switch SN are connected in parallel, and the output signal V_OUT1 is output. N ​ 3. The offset self-correcting circuit of claim 1, wherein, The comparison module is a D flip-flop structure, the D end of the D flip-flop is connected to the output signal V_OUT1 of the timing adjustment array, the CLK end is connected to the first control signal, and the Q end outputs a signal V_OUT2.

4. The offset self-correcting circuit of claim 1, wherein, The latch module is composed of N D flip-flops, the D end of each D flip-flop is connected to the output signal V_OUT2 of the comparison module, and the CLK end is connected to the clock signal CLK_IN <n-1:0>, Q end output signal V_OUT3, the output signal of each D flip-flop is merged and the final output signal V_OUT3 <n-1:0> 。< / n-1:0> 5. The offset self-correcting circuit of claim 1, wherein, The decoding module comprises N parallel branches, the first branch is composed of three inverters connected in series, the second branch to the (N-1)th branch are each composed of two inverters and an NOR gate, one input terminal of the NOR gate is connected to the output terminal of the inverter connected in series in the branch, and the other input terminal of the NOR gate is connected to the output terminal of the first inverter in the previous stage branch, and the output signals of the branches are combined and output as a signal V_OUT4 <n-1:0> 。< / n-1:0> 6. A segmented current steering DAC comprising the offset self-correcting circuit of any one of claims 1-5, wherein, The segmented current steering type DAC further comprises high and low digital codes, a thermometer decoding circuit, a latch, a current source array, a voltage-to-current circuit and a bandgap reference voltage source.

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