Integrated circuit device

Abstract

The utility model provides an integrated circuit device comprising a semiconductor layer. The semiconductor layer comprises a first material with first Gibbs free energy and a second material with second Gibbs free energy smaller than the first Gibbs free energy. The first material includes a p-type oxide semiconductor material. The integrated circuit device also includes a dielectric layer contacting the first surface of the semiconductor layer, a gate conductive structure contacting the dielectric layer opposite the semiconductor layer, and a first source drain conductive structure and a second source drain conductive structure electrically connected to the semiconductor layer.

Description

TECHNICAL FIELD

[0001] The present application relates to an integrated circuit device. BACKGROUND

[0002] Oxide-based semiconductors (e.g., p-type and n-type oxide semiconductors) have been used in a variety of integrated circuit (IC) devices, particularly those including components of thin-film transistor (TFT) circuitry. A popular application of TFT circuitry is in optical components (e.g., image sensors, display elements, etc.), in part because TFTs typically have a high degree of transparency. This transparency is due in part to the thin layers of material used in TFTs, as well as the transparent nature of some oxide semiconductors used therein. SUMMARY

[0003] An IC device is provided. The IC device includes a semiconductor layer including a first material having a first Gibbs free energy and a second material having a second Gibbs free energy less than the first Gibbs free energy. The first material includes a p-type oxide semiconductor material. The IC device also includes a dielectric layer contacting a first surface of the semiconductor layer, a gate conductive structure contacting the dielectric layer opposite the semiconductor layer, and a first source / drain conductive structure and a second source / drain conductive structure electrically connected to the semiconductor layer.

[0004] An IC device is provided. The IC device includes a gate conductive layer, a dielectric layer disposed above the gate conductive layer, a semiconductor layer disposed above the dielectric layer, and a first source / drain conductive structure and a second source / drain conductive structure disposed above the semiconductor layer. The semiconductor layer includes a plurality of layers of a first material having a first Gibbs free energy and one or more layers of a second material having a second Gibbs free energy less than the first Gibbs free energy. The first material includes a p-type oxide semiconductor material. Each successive pair of the plurality of layers of the first material is separated by a corresponding layer of the one or more layers of the second material. A thickness of each of the plurality of layers of the first material is greater than a thickness of each of the one or more layers of the second material. BRIEF DESCRIPTION OF DRAWINGS

[0005] The present application will be best understood by reading the following detailed description together with the drawings, in which:

[0006] Figure 1A Cross-sectional views of some embodiments of a back end of line (BEOL) bottom gate transistor of an IC device employing a stable p-type oxide semiconductor layer in accordance with the present disclosure are shown.

[0007] Figure 1BCross-sectional views of some embodiments of BEOL top-gate transistors of IC devices employing stable p-type oxide semiconductor layers according to the present disclosure are shown.

[0008] Figure 1C Cross-sectional views of some embodiments of front-end-of-line (FEOL) transistors of IC devices employing stable p-type oxide semiconductor layers according to the present disclosure are shown.

[0009] Figures 2A to 2F 、 Figures 3A to 3F 、 Figures 4A to 4F 、 Figures 5A to 5H 、 Figures 6A to 6H 、 Figures 7A to 7H 、 Figures 8A to 8H 、 Figures 9A to 9J and Figures 10A to 10F Cross-sectional side views of some embodiments of IC devices employing respective stable p-type oxide semiconductor layers at various stages of fabrication according to the present disclosure are shown.

[0010] Figure 11 Methods of forming IC devices employing stable p-type oxide semiconductor layers according to some embodiments are shown.

[0011] Figures 12A to 12C Methods of forming stable p-type oxide semiconductor layers according to some embodiments are shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of first feature on top of or on a second feature in the following description can include embodiments in which the first feature is formed in direct contact with the second feature, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Additionally, the present disclosure can make use of reference numbers and / or letters in various instances. Such use of reference numbers and / or letters is for the purpose of simplifying the present disclosure and is not intended to be limiting in and of itself.

[0013] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] In contrast to n-type oxide semiconductors, some p-type oxide semiconductors are believed to be electrically unstable due to chemical changes within the semiconductor (e.g., changes in oxygen vacancy levels) that occur during processing steps of the IC device after formation of the oxide semiconductor layer and during operation of the completed IC device. More specifically, changes in oxygen vacancies can cause related fluctuations in the number of charge carriers available in the p-type oxide semiconductor, which can negatively impact the electrical performance of transistors employing the p-type oxide semiconductor.

[0015] To address these issues, some embodiments of the present disclosure provide IC devices that employ a stable p-type oxide semiconductor layer that includes an additional material that employs a lower Gibbs free energy (e.g., at a particular temperature and pressure) than the p-type oxide semiconductor material used in prior art semiconductor layers. Generally speaking, the Gibbs free energy is a thermodynamic potential that can be used to calculate the maximum amount of work, other than pressure-volume work, that can be performed by a thermodynamically closed system at constant temperature and pressure. The maximum amount of work resulting from a reversible process is calculated as the change in Gibbs free energy from the initial state to the final state of the system. Thus, the lower the change in Gibbs free energy, the less energy is required to effect the change. Moreover, a negative Gibbs free energy change, i.e., a final state having a lower Gibbs free energy than the initial state, can result in a corresponding spontaneous reaction in the system.

[0016] More formally, the Gibbs free energy of a system or material is denoted in the art as G(p,

[0017] T) = U + pV - TS = H - TS, where p is pressure, T is temperature, U is internal energy, V is volume, H is enthalpy, and S is the entropy of the system or material.

[0018] Thus, in some embodiments, the additional material, by virtue of its lower Gibbs free energy, can more readily undergo the creation and annihilation of oxygen vacancies in response to the transfer of energy (e.g., thermal energy) to and from the processing steps of the IC device, thereby stabilizing the oxygen vacancy levels in the p-type oxide semiconductor material.

[0019] Accordingly, use of some embodiments can provide transistors (e.g., TFTs) employing p-type oxide semiconductors that facilitate improved levels of electrical performance (e.g., responsive and consistent transistor operation) in p-type semiconductor regions by providing a stable amount of charge carriers associated with oxygen vacancies, while providing advantages typically associated with the use of oxide semiconductors (e.g., transparency).

[0020] Figure 1A A cross-sectional view of some embodiments of a back end of line (BEOL) bottom gate transistor 102A (e.g., a thin film transistor (TFT)) of an IC device 100A employing a stable p-type oxide semiconductor layer 101 according to the present disclosure is shown. Other portions of the IC device 100A (e.g., front end of line (FEOL) regions, including a semiconductor substrate having doped regions for transistors) are not shown in Figure 1A FIG. 1 for simplicity of the following discussion.

[0021] Above the FEOL regions of the IC device 100A can be one or more dielectric layers 112, which can be separated by etch stop layers 115. Further, each dielectric layer 112 can include conductive layers 114 and interconnects or vias 113 to provide electrical connectivity between various electronic components (e.g., BEOL transistors). As shown, Figure 1A The BEOL bottom gate transistor 102A can be disposed within one of the dielectric layers 112, for example. For example, a gate conductive layer 156 of the BEOL bottom gate transistor 102A can be disposed above the etch stop layer 115. A gate dielectric layer 148 (e.g., silicon dioxide (Si02), another silicon oxide (SiOx), or another dielectric material) can be disposed above the gate conductive layer 156 such that the gate conductive layer 156 contacts the gate dielectric layer 148.

[0022] Further, as disclosed in greater detail below, a semiconductor layer 101 (e.g., including a p-type oxide semiconductor according to embodiments of the present disclosure) is disposed above the gate dielectric layer 148. Further, first and second source / drain conductive structures 157 are disposed above the semiconductor layer 101 such that the first and second source / drain conductive structures 157 contact the semiconductor layer 101. In some embodiments, the conductive layers 114 can be coupled to the source / drain conductive structures 157 through conductive vias 113 to connect the BEOL bottom to connect the transistor 102A to other electronic components.

[0023] Figure 1B A cross-sectional view of some embodiments of a BEOL top gate transistor 102B of an IC device 100B employing a stable p-type oxide semiconductor layer 101 according to the present disclosure is shown. As Figure 1BAs shown, the BEOL top gate transistor 102B can be set in relation to, for example... Figure 1A The bottom gate transistor 102A of the BEOL shown is located in a similar position (e.g., within the dielectric layer 112).

[0024] More specifically, in the BEOL region, first and second source-drain conductive structures 157 (e.g., above the etch stop layer 115) can be disposed. Furthermore, a stable p-type oxide semiconductor layer 101 can be disposed above the first and second source-drain conductive structures 157 and the etch stop layer 115, such that the first and second source-drain conductive structures 157 contact the stable p-type oxide semiconductor layer 101. A gate dielectric layer 148 can be formed above the stable p-type oxide semiconductor layer 101. Additionally, a gate conductive layer 156 can be disposed above the gate dielectric layer 148 to contact the gate dielectric layer 148. Furthermore, a conductive layer 114 can be electrically connected to the gate conductive layer 156 through a conductive via 113 to connect the BEOL top gate transistor 102B to other electronic components.

[0025] Apart from Figure 1A BEOL bottom gate transistor 102A and Figure 1B In addition to the BEOL top-gate transistor 102B, front-end process (FEOL) transistors can also be incorporated into a stable p-type oxide semiconductor layer 101. For example, Figure 1C Cross-sectional views of some embodiments of the FEOL transistor 102C of an IC device 100C employing a stable p-type oxide semiconductor layer 101 according to the present disclosure are shown.

[0026] More specifically, such as Figure 1C As shown, the FEOL region can employ a stable p-type oxide semiconductor layer 101 as a substrate, on which one or more dielectric layers 112 can be disposed, possibly interleaved with an etch stop layer 115. In some embodiments, the p-type oxide semiconductor layer 101 may include n-doped source-drain regions 104. A gate dielectric layer 148 can be disposed on the p-type oxide semiconductor layer 101 (e.g., within the first dielectric layer 112), followed by a gate conductive layer 156. In some embodiments, a spacer structure 155 may laterally surround the gate dielectric layer 148 and the gate conductive layer 156. Furthermore, in some embodiments, the conductive layer 114 may be electrically connected to the source-drain regions 104 through conductive vias 113, thereby facilitating the connection of the FEOL transistor 102C to other electronic components, such as other transistors.

[0027] In each of the BEOL bottom gate transistor 102A, the BEOL top gate transistor 102B, and the FEOL transistor 102C, the inclusion of the stable p-type oxide semiconductor layer 101 can facilitate enhanced operational performance compared to transistors employing other p-type oxide semiconductor layers, while taking advantage of other characteristics associated with p-type oxide semiconductor layers, such as significant transparency. To focus the following discussion, the various embodiments of the stable p-type oxide semiconductor layer 101 are discussed below in the context of a BEOL bottom gate transistor. However, the use of these embodiments is not limited to use within a BEOL bottom gate transistor, as noted above.

[0028] Figures 2A to 2F Figures 3A to 3F Figures 4A to 4F Figures 5A to 5H Figures 6A to 6H Figures 7A to 7H Figures 8A to 8H Figures 9A to 9J Figures 10A to 10F FIGS. 1-3 show cross-sectional views of some embodiments of an IC device at various stages of fabrication, each employing a respective stable p-type oxide semiconductor layer within a BEOL backside gate transistor (e.g., TFT), in accordance with the present disclosure. Although Figures 2A to 2F Figures 3A to 3F Figures 4A to 4F Figures 5A to 5H Figures 6A to 6H Figures 7A to 7H Figures 8A to 8H Figures 9A to 9J Figures 10A to 10F Each of FIGS. 1-3, while described as a separate series of steps, it should be understood that these steps are not limiting, as the order of the steps within each series can be changed in other embodiments, and the disclosed methods are applicable to other structures as well. In other embodiments, some of the steps shown and / or described can be omitted in whole or in part.

[0029] Figures 2A to 2F FIGS. 4-6 show cross-sectional views of some embodiments of a BEOL backside gate transistor including a p-type oxide semiconductor layer 101A at various stages of fabrication, in accordance with the present disclosure. For example, Figure 2A ​​​​​​​​​​​​​​​​Formation (e.g., deposition) of a gate dielectric layer 148 is shown over the gate conductive layer 156. In some embodiments, the gate conductive layer 156 can include at least one of titanium nitride (TiN), hydrogen-rich TiN, tungsten (W), copper (Cu), molybdenum (Mo), molybdenum tungsten (MoW), tantalum nitride (TaN), or other conductive materials. The gate dielectric layer 148 can include at least one of silicon dioxide (SiO2), aluminum oxide (AI2O3), hafnium oxide (HfO), HfO mixed with zirconium oxide (ZrO) (HfO:ZrO), HfO mixed with AI (HfO:AI2O3), HfO mixed with lanthanum oxide (La2O3) (HfO:La2O3), HfO mixed with SiO2(HfO:SiO2), HfO mixed with strontium oxide (SrO) (HfO:SrO), or other dielectric materials.

[0030] Figures 2B to 2D Formation (e.g., deposition) of a p-type oxide semiconductor layer 101A is shown over the gate dielectric layer 148. Figure 2B A first layer of a first material 201 including a p-type oxide semiconductor material is shown. In some embodiments, the p-type oxide semiconductor material can include at least one of copper oxide (CuOx), tin oxide (SnOx), titanium oxide (TiOx), or another oxide semiconductor material. Further, in some embodiments, the first layer of the first material 201, as well as other layers of the first material 201 described herein, can be from a few nanometers to a few tens of nanometers thick. For example, in some embodiments, the first layer of the first material 201, as well as other layers of the first material 201 described herein, can be at least 3 nanometers (nm) thick, while in other embodiments, can be at least 20 nm thick. Also, in some embodiments, the first layer of the first material 201, as well as other layers of the first material 201 described herein, can be no more than 50 nm thick, while in other embodiments, can be no more than 100 nm thick.

[0031] Figure 2C Formation (e.g., deposition) of a layer of a second material 202 is shown over the first layer of the first material 201. In some embodiments, the second material 202 can have a Gibbs free energy that is less than the Gibbs free energy of the first material 202. In some embodiments, the second material 202 can include at least one of gallium nitride (GaN), aluminum oxide (AIOx), tantalum oxide (TaOx), yttrium oxide (YOx), scandium oxide (ScOx), niobium oxide (NbOx), or another metal nitride or metal oxide having a Gibbs free energy that is lower than the Gibbs free energy of the first material 201.

[0032] In some embodiments, the layer of the second material 202, as well as other layers of the second material 202, can be a few angstroms thick. For example, the second material layer 202 and other layers of the second material 202 can be at least 5 Angstroms thick, while in other embodiments can be at least 20 Angstroms thick. Also, in some embodiments, the layers of the second material 202 can be less than or equal to 50 Angstroms thick. The thickness of the second material 202 can be a minimum thickness sufficient to stabilize the level of oxygen vacancies in the first material 201 based on the particular first material 201 and second material 202.

[0033] Figure 2D A second layer of the first material 201 is shown formed (e.g., deposited) on the layer of the second material 202. In some embodiments, the second layer of the first material 201 can have the same thickness as the first layer of the first material 201, and thus the thickness can be from a few nanometers to tens of nanometers.

[0034] Figure 2E An upper dielectric layer 112 is shown formed (e.g., deposited) over the p-type oxide semiconductor layer 101 A. In some embodiments, the upper dielectric layer 112 can include at least one of SiOx, silicon nitride (SiNx), or another dielectric material.

[0035] Figure 2F The first and second source / drain conductive structures 157 are shown formed in the upper dielectric layer 112 such that the first and second source / drain conductive structures 157 are electrically connected to the p-type oxide semiconductor layer 101 A. In some embodiments, the upper dielectric layer 112 is etched to expose an upper surface of the p-type oxide semiconductor layer 101 A, and a conductive material is deposited in the etched portion to form the first and second source / drain conductive structures 157. In some embodiments, prior to depositing the source / drain conductive structures 157, an intermediate conductive layer 158 can be conformally deposited in the etched portion (e.g., to provide a diffusion barrier between the first and second source / drain conductive structures 157 and the surrounding region of the upper dielectric layer 112 and the upper surface of the p-type oxide semiconductor layer 101 A).

[0036] Thus, in the p-type oxide semiconductor layer 101 A of the resulting transistor structure, in some embodiments, the relatively small amount of the second material 202 added to the first material 201 can stabilize the level of oxygen vacancies in the first material 201. This is because the second material 202 has a lower Gibbs free energy relative to the first material 201. For example, in response to energy transferred into and out of the IC device (e.g., the second material 202 can be more susceptible to oxygen vacancy generation and annihilation than the first material 201) in processing steps that transfer energy, this can stabilize the level of oxygen vacancies in the first material 201, thereby providing the transistor structure with an improved level of electrical performance over a p-type oxide semiconductor that does not include the second material 202.

[0037] Figures 3A to 3FCross-sectional views of some embodiments of a BEOL backside gate transistor including a p-type oxide semiconductor layer 101B according to the present disclosure are shown at various stages of fabrication. In some embodiments, Figure 3A , Figure 3E and Figure 3F and Figure 2A , Figure 2E and Figure 2F depicted stages are the same as or similar to those described above. Figures 3B to 3D Formation (e.g., deposition) of a p-type oxide semiconductor layer 101B over the gate dielectric layer 148 is shown. Figure 3B A first layer of a first material 201 including a p-type oxide semiconductor material is shown. In some embodiments, the p-type oxide semiconductor material can include one or more of those listed above in connection with Figure 2B and can have the same thickness as described above.

[0038] Figure 3C Formation (e.g., deposition) of a layer of a second material 202 over the first layer of the first material 201 is shown. In some embodiments, the second material 202 can have a Gibbs free energy that is less than that of the first material 201, as described above. In some embodiments, the second material 202 can include at least one of the same materials discussed above in connection with Figure 2C and can have the same thickness as described above.

[0039] Figure 3D Formation (e.g., deposition) of a second layer of the first material 201 over the layer of the second material 202 is shown. In some embodiments, the second layer of the first material 201 can be thicker than the first layer of the first material 201. For example, in some embodiments, the second layer of the first material 201 can be at least three times thicker than the first layer of the first material 201. In other embodiments, the second layer of the first material 201 can be at least ten times thicker than the first layer of the first material 201. In some embodiments, the second layer of the first material 201 can be made thicker than the first layer of the first material 201 to compensate for a higher expected rate of oxygen vacancy instability in the lower regions of the p-type oxide semiconductor layer 101B.

[0040] Figures 4A to 4F Cross-sectional views of some embodiments of a BEOL backside gate transistor including a p-type oxide semiconductor layer 101C according to the present disclosure are shown at various stages of fabrication. In some embodiments, Figure 4A , Figure 4E and Figure 4F and Figure 2A , Figure 2E and Figure 2F depicted stages are the same as or similar to those described above. Figures 4B to 4DA p-type oxide semiconductor layer 101C is shown being formed (e.g., deposited) over the gate dielectric layer 148. Figure 4B A first layer of a first material 201 comprising a p-type oxide semiconductor material is shown. In some embodiments, the p-type oxide semiconductor material can include at least one of those listed above in connection with Figure 2B and can have the same thickness as described above.

[0041] Figure 4C A layer of a second material 202 is shown being formed (e.g., deposited) on the first layer of the first material 201. In some embodiments, the second material 202 can have a Gibbs free energy that is less than the Gibbs free energy of the first material 201, as described above. In some embodiments, the second material 202 can include at least one of the same materials discussed above in connection with Figure 2C and can have the same thickness as described above.

[0042] Figure 4D A second layer of the first material 201 is shown being formed (e.g., deposited) on the layer of the second material 202. In some embodiments, the first layer of the first material 201 can be thicker than the second layer of the first material 201. For example, in some embodiments, the first layer of the first material 201 can be at least three times thicker than the second layer of the first material 201. In other embodiments, the first layer of the first material 201 can be at least ten times thicker than the second layer of the first material 201. In some embodiments, the first layer of the first material 201 can be made thicker than the second layer of the first material 201 to compensate for a higher expected rate of oxygen vacancy instability in the upper region of the p-type oxide semiconductor layer 101C.

[0043] Figures 5A to 5H Cross-sectional views of some embodiments of a BEOL backside gate transistor comprising a p-type oxide semiconductor layer 101D according to the present disclosure are shown at various stages of fabrication. In some embodiments, Figure 5A , Figure 5G and Figure 5H are the same as or similar to the stages depicted above. Figure 2A , Figure 2E and Figure 2F as described above. Figures 5B to 5F A p-type oxide semiconductor layer 101D is shown being formed (e.g., deposited) over the gate dielectric layer 148. Figure 5B A layer of a first material 201 comprising a p-type oxide semiconductor material is shown. In some embodiments, the p-type oxide semiconductor material can include at least one of those listed above in connection with Figure 2B and can have the same thickness as described above.

[0044] Figure 5C A layer of a second material 202 is shown formed (e.g., deposited) on the layer of the first material 201. In some embodiments, the second material 202 can have a Gibbs free energy that is less than the Gibbs free energy of the first material 201, as described above. In some embodiments, the second material 202 can include at least one of the same materials discussed above in connection with Figure 2C and can have the same thickness as described above.

[0045] Figures 5D to 5F A layer of the second material 202 is shown thermally driven (e.g., through heating) (e.g., downward) inside the layer of the first material 201. In some embodiments, the thermal driving can be performed by heating a surrounding gaseous environment of the first material 201 and / or the second material 202, directly heating (e.g., through light) the first material 201 and / or the second material 202, or another heating method. In some embodiments, the final position of the layer of the second material 202 within the layer of the first material 201 can be controlled by the amount of thermal energy added and / or the amount of time elapsed during the thermal driving, as Figures 5D to 5F shown. While Figure 5F the final position of the layer of the second material 202 is depicted near a lower surface of the layer of the first material 201, other positions of the layer of the second material 202, such as near an upper surface of the layer of the first material 201 (e.g., as Figure 5D shown), or in the center of the layer of the first material 201 (e.g., as Figure 5E shown), can also be selected as the final position of the layer of the second material 202. Figures 5D to 5F The layer of the second material 202 is depicted maintaining its shape, in some embodiments, the layer of the second material 202 can become at least slightly diffuse within the layer of the first material 201 due to the thermal driving.

[0046] Figures 6A to 6H Cross-sectional views of some embodiments of a BEOL backside gate transistor including a p-type oxide semiconductor layer 101E according to the present disclosure are shown at various stages of fabrication. In some embodiments, Figure 6A , Figure 6G and Figure 6H are the same as or similar to the stages depicted in Figure 2A , Figure 2E and Figure 2F , as described above. Figures 6B to 6F A p-type oxide semiconductor layer 101E is shown formed (e.g., deposited) over the gate dielectric layer 148. Figure 6B A first layer of a first material 201 including a p-type oxide semiconductor material is shown. In some embodiments, the p-type oxide semiconductor material can include at least one of the same materials discussed above in connection with Figure 2Bat least one of the same materials discussed above, and can have the same thickness as described above.

[0047] Figure 6C A first layer of a second material 202 is shown formed (e.g., deposited) on the first layer of the first material 201. In some embodiments, the second material 202 can have a Gibbs free energy that is less than the Gibbs free energy of the first material 201, as described above. In some embodiments, the second material 202 can include at least one of the same materials discussed above in connection with Figure 2C

[0048] Figures 6D to 6F Layers (e.g., alternating layers) of the first material 201 and the second material 202 are shown subsequently formed (e.g., deposited) on the first layer of the second material 202. Figure 6D A second layer of the first material 201 is shown formed on the first layer of the second material 202. Figure 6E A second layer of the second material 202 is shown formed on the second layer of the first material 201. Figure 6F A third layer of the first material 201 is shown formed on the second layer of the second material 202. Thus, the p-type oxide semiconductor layer 101E can include a total of five layers.

[0049] In some embodiments, the first and second layers of the second material 202 have the same thickness, and can be positioned equidistant from the vertical center of the second layer of the first material 201. Thus, the first and third layers of the first material 201 can have the same thickness. As Figure 6F shown, the second layer of the first material 201 can be thicker than the first and third layers of the first material 201. In other embodiments, the second layer of the first material 201 can have the same thickness as the first and third layers, or be thinner than the first and third layers.

[0050] Figures 7A to 7H Cross-sectional views of some embodiments of a BEOL backside gate transistor including a p-type oxide semiconductor layer 101F according to the present disclosure at various stages of fabrication are shown. In some embodiments, the p-type oxide semiconductor layer 101F is formed (e.g., deposited) on the gate dielectric layer 148. Figure 7A 7G and 7H are the same as or similar to the stages depicted in Figure 6A Figure 6G and Figure 6H as described above. Figures 7B to 7F A p-type oxide semiconductor layer 101F is shown formed (e.g., deposited) over the gate dielectric layer 148. Figures 7B to 7F ​​​formation of alternating layers of a first material 201 and a second material 202, such as those described above and associated thicknesses, and where the Gibbs free energy of the second material 202 is less than the Gibbs free energy of the first material 201. Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F formation of a first layer of the first material 201, a first layer of the second material 202, a second layer of the first material 201, a second layer of the second material 202, and a third layer of the first material 201, respectively, to form a total of five layers of the p-type oxide semiconductor layer 101F.

[0051] In some embodiments, as shown in Figure 7F the second layer of the second material 202 can be located at a vertical center position within the p-type oxide semiconductor layer 101F. Thus, the third layer of the first material 201 can be thicker than the first or second layer of the first material 201. As shown in Figure 7D In some embodiments, the second layer of the first material 201 can be thicker than the first layer of the first material 201. In other embodiments, the second layer of the first material 201 can have the same thickness as the first layer of the first material 201 or be thinner than the first layer.

[0052] Figures 8A to 8H formation of alternating layers of a first material 201 and a second material 202, such as those described above and associated thicknesses, and where the Gibbs free energy of the second material 202 is less than the Gibbs free energy of the first material 201. Figure 8A , Figure 8G and Figure 8H as depicted in Figure 6A , Figure 6G and Figure 6H as described above. Figures 8B to 8F formation (e.g., deposition) of the p-type oxide semiconductor layer 101G over the gate dielectric layer 148. Figures 8B to 8F formation of alternating layers of a first material 201 and a second material 202, such as those described above and associated thicknesses, and where the Gibbs free energy of the second material 202 is less than the Gibbs free energy of the first material 201. Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F formation of a first layer of the first material 201, a first layer of the second material 202, a second layer of the first material 201, a second layer of the second material 202, and a third layer of the first material 201, respectively, to form a total of five layers of the p-type oxide semiconductor layer 101G.

[0053] In some embodiments, such as Figure 8F As shown, the first layer of the second material 202 can be located at the vertical center position within the p-type oxide semiconductor layer 101G. Therefore, the first layer of the first material 201 can be thicker than either the second or third layer in the first material 201. Figure 8F As shown, in some embodiments, the second layer of the first material 201 may be thicker than the third layer of the first material 201. In other embodiments, the second layer of the first material 201 may be the same thickness as or thinner than the third layer.

[0054] Figures 9A to 9J Cross-sectional views are shown of some embodiments of a BEOL back-gate transistor including a p-type oxide semiconductor layer 101H according to this disclosure at various stages of fabrication. In some embodiments, Figure 9A , Figure 9I and Figure 9J and Figure 6A , Figure 6G and Figure 6H The stages described are the same or similar, as described above. Figures 9B to 9H A p-type oxide semiconductor layer 101H is shown formed (e.g., deposited) over a gate dielectric layer 148. Figures 9B to 9H The formation of alternating layers of a first material 201 and a second material 202 is shown, as described above, with the materials and associated thicknesses, and wherein the Gibbs free energy of the second material 202 is less than that of the first material 201. Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G and Figure 9H The first layer of the first material 201, the first layer of the second material 202, the second layer of the first material 201, the second layer of the second material 202, the third layer of the first material 201, the third layer of the second material 202, and the fourth layer of the first material 201 are displayed in sequence to form a total of seven layers of p-type oxide semiconductor layer 101H.

[0055] In some embodiments, such as Figure 9HAs shown, the second layer of the second material 202 can be located at a vertical center location within the p-type oxide semiconductor layer 101H. Further, in some embodiments, the second and third layers of the first material 201 can have a same first thickness, and the first and fourth layers of the first material 201 can have a same second thickness. Further, in some embodiments, the first thickness can be equal to the second thickness. Other embodiments of the p-type oxide semiconductor layer 101H can also exhibit this symmetry on a horizontal plane located centrally within the p-type oxide semiconductor layer 101H. However, in other embodiments, this symmetry can not be provided, as each of the first, second, third, and fourth layers of the first material 201 can have different thicknesses. Further, while the p-type oxide semiconductor layer 101H includes four layers of the first material 201, other embodiments can include more than four layers (e.g., n layers) of the first material 201 and (e.g., n-1 layers) of the second material 202 therebetween.

[0056] Figures 10A to 10F Cross-sectional views of some embodiments of a BEOL backside gate transistor including a p-type oxide semiconductor layer 101I according to the present disclosure are shown at various stages of fabrication. In some embodiments, Figure 10A , Figure 10E and Figure 10F with Figure 2A , Figure 2E and Figure 2F depicted stages are the same as or similar to those described above. Figures 10B to 10D Formation (e.g., deposition) of a p-type oxide semiconductor layer 101I over the gate dielectric layer 148 is shown. Figure 10B A layer of a first material 201 including a p-type oxide semiconductor material is shown. In some embodiments, the p-type oxide semiconductor material can include at least one of those materials listed above in connection with Figure 2B and can have the same thickness as described above.

[0057] Figure 10C Formation (e.g., deposition) of a layer of a second material 202 over the layer of the first material 201 is shown. In some embodiments, the second material 202 can have a Gibbs free energy that is less than that of the first material 201, as described above. In some embodiments, the second material 202 can include at least one of the same materials discussed above in connection with Figure 2C and can have the same thickness as described above.

[0058] Figure 10DA layer of a third material 201 A is shown formed (e.g., deposited) on the layer of the second material 202, where the third material comprises a p-type oxide semiconductor material that is different from (e.g., has a different chemical composition than) the p-type oxide semiconductor material of the first material 201. In some embodiments, the third material 201 A can comprise one or more of the materials listed above in connection with the first material 201 (e.g., CuOx, SnOx, TiOx, or another oxide semiconductor material). Additionally, in some embodiments, the third material 201 A can have a Gibbs free energy that is greater than the Gibbs free energy of the second material 202. The Gibbs free energy of the third material 201 A can be greater than, less than, or equal to the Gibbs free energy of the first material 201.

[0059] In some embodiments, the thickness of the layer of the third material 201 A can be as described above in connection with the layer of the first material 201. As Figure 2B indicated, the layer of the first material 201 and the layer of the third material 201 A can have the same thickness, while in other embodiments, the layer of the first material 201 can be thicker or thinner than the layer of the third material 201 A. Figure 10D

[0060] While specific embodiments are described above in connection with Figures 2A to 10F the first material 201, the present disclosure is not so limited, and aspects of the various embodiments can be combined in other manners not explicitly described herein. For example, while two layers comprising different p-type oxide semiconductor materials are discussed, each of the foregoing embodiments can be combined with one or more of the other embodiments discussed above to create embodiments in which more than two separate layers of different p-type oxide semiconductor materials exist. Other combinations of the various embodiments described above are also possible. Figures 10A to 10F

[0061] Figure 11 A method 1100 of forming an IC device comprising a stable p-type oxide semiconductor layer is shown, in accordance with some embodiments. While this and other methods shown and / or described herein are shown as a series of steps or events, it will be appreciated that the disclosure is not limited to the order of steps or events as shown. Thus, in some embodiments, the steps can be performed in an order other than that shown, and / or concurrently. Furthermore, in some embodiments, steps or events shown can be subdivided into multiple steps or events, which can be performed at separate times or concurrently with other steps or sub-steps. In some embodiments, some of the steps or events shown can be omitted, and other steps or events not shown can be included.

[0062] Steps 1102 through 1108 can correspond, for example, to the previously described steps 1002 through 1010, respectively. Figures 2A to 2F Figures 3A to 3F Figures 4A to 4F ,​​​​ Figures 5A to 5H , Figures 6A to 6H , Figures 7A to 7H , Figures 8A to 8H , Figures 9A to 9J as well as Figures 10A to 10F The structures shown in the figure. In some embodiments, they all correspond to Figure 1A IC device 100A. However, method 1100 can also be applied to IC devices. Figure 1B IC device 100B and Figure 1C The same embodiment of the IC device 100C.

[0063] At step 1102, for example, in the substrate layer (e.g., dielectric layer 112 or...) Figure 1A The etch stop layer 115) forms a gate conductive structure (e.g., Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A The gate conductive layer 156). In step 1104, a dielectric layer (e.g., the gate conductive layer) is formed above the gate conductive structure. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A (Gate dielectric layer 148). Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A Cross-sectional views corresponding to some embodiments of steps 1102 and 1104 are shown.

[0064] In step 1106, a p-type oxide semiconductor structure (e.g., ...) is formed above the dielectric layer. Figure 2D p-type oxide semiconductor layer 101A, Figure 3D p-type oxide semiconductor layer 101B Figure 4D p-type oxide semiconductor layer 101C, Figure 5F p-type oxide semiconductor layer 101D, Figure 6F p-type oxide semiconductor layer 101E, Figure 7F p-type oxide semiconductor layer 101F, Figure 8F p-type oxide semiconductor layer 101G, Figure 9Hp-type oxide semiconductor layer 101H and Figure 10D p-type oxide semiconductor layer 101I). In some embodiments, the p-type oxide semiconductor structure includes a first material (e.g., first material 201) having a first Gibbs free energy and a second material (e.g., second material 202) having a second Gibbs free energy that is less than the first Gibbs free energy. The first material can include a p-type oxide semiconductor material. Figures 2B to 2D Figures 3B to 3D Figures 4B to 4D Figures 5B to 5F Figures 6B to 6F Figures 7B to 7F Figures 8B to 8F Figures 9B to 9H Figures 10B-10D shows cross-sectional views corresponding to some embodiments of step 1106. Particular examples of step 1106 will be discussed below in connection with Figures 12A-12C

[0065] At step 1108, first and second source / drain conductive structures (e.g., first and second source / drain conductive structures 157) are formed over the p-type oxide semiconductor structure. Figure 2F Figure 3F Figure 4F Figure 5H Figure 6H Figure 7H Figure 8H Figure 9J Figure 10F Figure 2E Figure 2F Figure 3E Figure 3F Figure 4E Figure 4F Figure 5G Figure 5H Figure 6G Figure 6H Figure 7G Figure 7H Figure 8G Figure 8H Figure 9I Figure 9J Figure 10E Figure 10F shows cross-sectional views corresponding to some embodiments of step 1108.

[0066] Figures 12A-12C Methods 1106A, 1106B, and 1106C show methods of forming a stable p-type oxide semiconductor layer, according to some embodiments. Each of methods 1106A, 1106B, and 1106C can represent an embodiment of step 1106 of method 1100. Figure 11

[0067] ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​In Figure 11 the method 1106A. Referring to Figure 12A , at step 1202, a first layer of a first material (e.g., the first material 201) is formed over a dielectric layer (e.g., the gate dielectric layer 148). Figure 2B , Figure 3B , Figure 4B , Figure 6B , Figure 7B , Figure 8B and Figure 9B show cross-sectional diagrams corresponding to some embodiments of step 1202.

[0068] At step 1204, a first layer of a second material (e.g., the second material 202) is formed over the first layer of the first material. Figure 2C , Figure 3C , Figure 4C , Figure 6C , Figure 7C , Figure 8C and Figure 9C show cross-sectional diagrams corresponding to some embodiments of step 1204.

[0069] At step 1206, a second layer of the first material is formed over the first layer of the second material. Figure 2D , Figure 3D , Figure 4D , Figure 6D , Figure 7D , Figure 8D and Figure 9D show cross-sectional diagrams corresponding to some embodiments of step 1206.

[0070] Optionally, at step 1208, a second layer of the second material is formed over the second layer of the first material. Figure 6E , Figure 7E , Figure 8E and Figure 9E show cross-sectional diagrams corresponding to some embodiments of step 1208.

[0071] Optionally, at step 1210, a third layer of the first material is formed over the second layer of the second material. Figure 6F , Figure 7F , Figure 8F and Figure 9F show cross-sectional diagrams corresponding to some embodiments of step 1210.

[0072] Optionally, at step 1212, a third layer of the second material is formed over the third layer of the first material. Figure 9G show cross-sectional diagrams corresponding to some embodiments of step 1212.

[0073] Optionally, in step 1214, a fourth layer of the first material is formed over the third layer of the second material. Figure 9H Cross-sectional views corresponding to some embodiments of step 1214 are shown.

[0074] exist Figure 12B In method 1106B, in step 1222, a layer of a first material (e.g., first material 201) is formed over a dielectric layer (e.g., gate dielectric layer 148). Figure 5B Cross-sectional views corresponding to some embodiments of step 1222 are shown.

[0075] In step 1224, a layer of a second material (e.g., second material 202) is formed over the layer of the first material. Figure 5C Cross-sectional views corresponding to some embodiments of step 1224 are shown.

[0076] In step 1226, the layer of the first material and / or the layer of the second material are heated to thermally drive the layer of the second material into the interior of the layer of the first material. Figures 5D-5F Cross-sectional views corresponding to some embodiments of step 1226 are shown.

[0077] exist Figure 12C In method 1106C, in step 1242, a layer of a first material (e.g., first material 201) of the first type is formed over a dielectric layer (e.g., gate dielectric layer 148). Figure 10B Cross-sectional views corresponding to some embodiments of step 1242 are shown.

[0078] In step 1244, a layer of a second material (e.g., second material 202) is formed over the layer of the first material of the first type. Figure 10C Cross-sectional views corresponding to some embodiments of step 1244 are shown.

[0079] In step 1246, a layer of a second type of first material (e.g., third material 201A) different from the first material of the first type is formed on top of the layer of the second material. Figure 10D Cross-sectional views corresponding to some embodiments of step 1246 are shown.

[0080] Some embodiments relate to an IC device. This IC device includes a semiconductor layer comprising a first material having a first Gibbs free energy and a second material having a second Gibbs free energy less than the first Gibbs free energy. The first material includes a p-type oxide semiconductor material. This IC device also includes a dielectric layer contacting a first surface of the semiconductor layer, a gate conductive structure of the contact dielectric layer opposite to the semiconductor layer, and a first source-drain conductive structure and a second source-drain conductive structure electrically connected to the semiconductor layer.

[0081] In some embodiments, wherein: the semiconductor layer comprises at least two layers of the first material; and each consecutive pair of the at least two layers of the first material is separated by a corresponding layer of the second material.

[0082] In some embodiments, wherein a thickness of each of the at least two layers of the first material is at least 3 nanometers and less than or equal to 100 nanometers.

[0083] In some embodiments, wherein a thickness of each corresponding layer of the second material is at least 5 Angstroms and less than or equal to 50 Angstroms.

[0084] In some embodiments, wherein the semiconductor layer comprises: two layers of the first material; and one layer of the second material disposed between the two layers of the first material.

[0085] In some embodiments, wherein the two layers of the first material have a same thickness.

[0086] In some embodiments, wherein a thickness of one of the two layers of the first material is greater than a thickness of another of the two layers of the first material.

[0087] In some embodiments, wherein a chemical composition of a first of the two layers of the first material is different than a chemical composition of a second of the two layers of the first material.

[0088] In some embodiments, wherein the semiconductor layer comprises: a first layer, a second layer, and a third layer of the first material; a first layer of the second material disposed between and adjacent to the first layer and the second layer of the first material; and a second layer of the second material disposed between and adjacent to the second layer and the third layer of the first material.

[0089] In some embodiments, wherein a thickness of the second layer of the first material is greater than a thickness of the first layer of the first material and a thickness of the third layer of the first material.

[0090] In some embodiments, wherein a thickness of the first layer of the first material is greater than a thickness of the second layer of the first material and a thickness of the third layer of the first material.

[0091] In some embodiments, wherein the semiconductor layer comprises: a first layer of the first material, a second layer of the first material, a third layer of the first material, and a fourth layer of the first material; a first layer of the second material disposed between and adjacent to the first layer and the second layer of the first material; a second layer of the second material disposed between and adjacent to the second layer and the third layer of the first material; and a third layer of the second material disposed between and adjacent to the third layer and the fourth layer of the first material.

[0092] In some embodiments, wherein the first layer, the second layer, the third layer, and the fourth layer of the first material have substantially the same thickness.

[0093] In some embodiments, wherein the p-type oxide semiconductor material comprises at least one of copper oxide (CuOx), tin oxide (SnOx), or titanium oxide (TiOx).

[0094] In some embodiments, wherein the second material comprises at least one of gallium nitride (GaN), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), scandium oxide (ScOx), or niobium oxide (NbOx).

[0095] Some embodiments relate to another IC device. The IC device includes a gate conductive layer, a dielectric layer disposed above the gate conductive layer, a semiconductor layer disposed above the dielectric layer, and a first source / drain conductive structure and a second source / drain conductive structure disposed above the semiconductor layer. The semiconductor layer includes a plurality of layers of a first material having a first Gibbs free energy and one or more layers of a second material having a second Gibbs free energy less than the first Gibbs free energy. The first material includes a p-type oxide semiconductor material. Each successive pair of the plurality of layers of the first material is separated by a corresponding layer of the one or more layers of the second material. A thickness of each of the plurality of layers of the first material is greater than a thickness of each of the one or more layers of the second material.

[0096] Some embodiments relate to a method. The method includes forming a conductive gate structure above a substrate layer; forming a dielectric layer above the conductive gate structure; and forming a p-type oxide semiconductor structure above the dielectric layer, a first source / drain conductive structure and a second source / drain conductive structure above the p-type oxide semiconductor structure. The p-type oxide semiconductor structure includes a first material having a first Gibbs free energy and a second material having a second Gibbs free energy less than the first Gibbs free energy. The first material includes a p-type oxide semiconductor material.

[0097] In some embodiments, wherein forming the p-type oxide semiconductor structure comprises: forming a first layer of the first material over the dielectric layer; forming a layer of the second material over the first layer of the first material; and forming a second layer of the first material on the layer of the second material.

[0098] In some embodiments, wherein forming the p-type oxide semiconductor structure comprises: forming a layer of the first material of a first type over the dielectric layer, the first type of the first material comprising a first type of the p-type oxide semiconductor material; forming a layer of the second material over the layer of the first type of the first material; and forming a layer of the first material of a second type over the layer of the second material, the second type of the first material comprising a second type of the p-type oxide semiconductor material.

[0099] In some embodiments, wherein forming the p-type oxide semiconductor structure comprises: forming a layer of the first material over the dielectric layer; forming a layer of the second material over the layer of the first material; and heating the layer of the first material and the layer of the second material to thermally drive the layer of the second material into an interior of the layer of the first material.

[0100] It should be understood that the use of the terms "first", "second", "third", etc. in this written description and in the following claims are used only as general identifiers to distinguish between different components of a figure or series of figures. Such terms do not imply any temporal or structural proximity, as such, and are not intended to set forth corresponding components in different illustrated examples and / or unillustrated examples. For example, a "first dielectric layer" set forth in connection with a first figure can not necessarily correspond to a "first dielectric layer" set forth in connection with another figure, and can not necessarily correspond to a "first dielectric layer" in unillustrated examples.

[0101] The foregoing outlines features of several embodiments so that a technical person skilled in the art can better understand the nature of the present disclosure. A skilled person will understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. A skilled person will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, characterized by comprising: a semiconductor layer comprising: a first material having a first Gibbs free energy, the first material comprising a p-type oxide semiconductor material; and a second material having a second Gibbs free energy less than the first Gibbs free energy; a dielectric layer contacting a first surface of the semiconductor layer; a gate conductive structure contacting the dielectric layer opposite the semiconductor layer; and a first source / drain conductive structure and a second source / drain conductive structure electrically connected to the semiconductor layer.

2. The integrated circuit device of claim 1, wherein: the semiconductor layer comprises at least two layers of the first material; and each successive pair of the at least two layers of the first material is separated by a corresponding layer of the second material.

3. The integrated circuit device of claim 2, wherein, each of the at least two layers of the first material has a thickness of at least 3 nanometers and less than or equal to 100 nanometers.

4. The integrated circuit device of claim 2, wherein, each corresponding layer of the second material has a thickness of at least 5 Angstroms and less than or equal to 50 Angstroms.

5. The integrated circuit device of claim 1, wherein, the semiconductor layer comprises: two layers of the first material; and one layer of the second material disposed between the two layers of the first material.

6. The integrated circuit device of claim 5, wherein, one of the two layers of the first material has a greater thickness than the other of the two layers of the first material.

7. The integrated circuit device of claim 1, wherein, the semiconductor layer comprises: a first layer, a second layer, and a third layer of the first material; a first layer of the second material disposed between and adjacent to the first layer and the second layer of the first material; and a second layer of the second material disposed between and adjacent to the second layer and the third layer of the first material.

8. The integrated circuit device of claim 7, wherein, the second layer of the first material has a greater thickness than the first layer of the first material and the third layer of the first material.

9. The integrated circuit device of claim 1, wherein, the semiconductor layer comprises: a first layer, a second layer, a third layer, and a fourth layer of the first material; a first layer of the second material disposed between and adjacent to the first layer and the second layer of the first material; a second layer of the second material disposed between and adjacent to the second layer and the third layer of the first material; and a third layer of the second material disposed between and adjacent to the third layer and the fourth layer of the first material.

10. An integrated circuit device, characterized by comprising: a gate conductive layer; a dielectric layer disposed over the gate conductive layer; a semiconductor layer disposed over the dielectric layer, the semiconductor layer comprising: a plurality of layers of a first material having a first Gibbs free energy, the first material comprising a p-type oxide semiconductor material; and a plurality of layers of a second material having a second Gibbs free energy less than the first Gibbs free energy. one or more layers of a second material having a second Gibbs free energy that is less than the first Gibbs free energy, wherein each successive pair of the plurality of layers of the first material is separated by a corresponding layer of the one or more layers of the second material, and wherein a thickness of each layer of the plurality of layers of the first material is greater than a thickness of each layer of the one or more layers of the second material; and a first source / drain conductive structure and a second source / drain conductive structure disposed above the semiconductor layer.

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