Grounding state monitoring equipment

Abstract

The utility model provides grounding state monitoring equipment. The grounding state monitoring equipment comprises a plurality of external equipment ports, triodes, a grounding port, a logic gate circuit chip and a control chip, wherein the triodes are configured corresponding to the external equipment ports; the external equipment port is used for connecting external equipment, and the grounding port is grounded; a monitoring signal of the external equipment port and a feedback signal of the grounding port are used for controlling on and off of the correspondingly configured triodes; the logic gate circuit chip comprises a NAND gate chip and an OR gate chip; two input ends of a NAND gate in the NAND gate chip are respectively connected with a signal output end of one triode; two input ends of an OR gate in the OR gate chip are respectively connected with an output end of one NAND gate; the control chip is connected with the output end of the OR gate chip and is used for outputting a signal for indicating the grounding state of the external equipment based on the potential state of the output end of the OR gate chip; based on the equipment, the grounding state of the equipment can be judged based on a signal processing mode of logical operation, and the monitoring accuracy and reliability are improved.

Description

Technical Field

[0001] This application relates to the field of assembly and manufacturing technology, and in particular to a grounding status monitoring device. Background Technology

[0002] In existing equipment safety management, safety protection is usually achieved by grounding the equipment's grounding wire. If the grounding wire is not grounded, it will cause safety hazards. In practical applications, the grounding status of the grounding wire usually needs to be checked manually, and it is impossible to monitor the grounding status of the grounding wire in real time, which makes the safety of equipment use relatively low. Utility Model Content

[0003] This application provides a grounding status monitoring device that can determine the grounding status of external devices based on signal processing using logical operations, thereby improving the accuracy and reliability of monitoring. The technical solution is as follows.

[0004] This application provides a grounding status monitoring device, which includes multiple external device ports, transistors configured corresponding to each external device port, grounding ports, logic gate circuit chips, and control chips;

[0005] The external device port is used to connect to external devices, and the grounding port is grounded;

[0006] The monitoring signal from the external device port and the feedback signal from the grounding port are used to control the on / off state of the corresponding transistors.

[0007] The logic gate chip includes a NAND gate chip and an OR gate chip; in the NAND gate chip, the two input terminals of the NAND gate are respectively connected to the signal output terminal of a transistor, and the received signal is subjected to NAND logic operation; in the OR gate chip, the two input terminals of the OR gate are respectively connected to the output terminal of a NAND gate, and the received signal is subjected to OR logic operation.

[0008] The control chip is connected to the output terminal of the OR gate chip and is used to output a signal based on the potential state of the output terminal of the OR gate chip; the signal output by the control chip is used to indicate the grounding state of the external device.

[0009] In one possible implementation, when both the monitoring signal from the external device port and the feedback signal from the ground port are low-level signals, the input of the NAND gate is a first-level signal; when the monitoring signal from the external device port is high-level and the feedback signal from the ground port is low-level, the input of the NAND gate is a second-level signal; the first-level signal and the second-level signal are different.

[0010] In one possible implementation, the transistors configured for each external device port are NPN transistors; the base of the transistor is connected to the external device port, the emitter of the transistor is connected to the ground port, and the collector of the transistor is connected to a NAND gate and a positive power supply.

[0011] In one possible implementation, the transistors configured for each external device port are NPN transistors; the base of the transistor is connected to the external device port, the emitter of the transistor is connected to the ground port, and the collector of the transistor is connected to a NAND gate and a positive power supply.

[0012] In one possible implementation, the device includes multiple levels of OR gate chips, where the input of each level of OR gate chip is the output of the OR gate chip in the previous level; the number of output signals of the last level of OR gate chip is the same as the number of input ports of the control chip.

[0013] In one possible implementation, the device further includes a switch assembly configured corresponding to each external device port; the circuit containing the switch assembly is connected in parallel with the circuit containing the corresponding external device port.

[0014] When an external device is connected to the external device port, the switch component corresponding to the external device port is in the ON state; when no external device is connected to the external device port, the switch component corresponding to the external device port is in the OFF state.

[0015] In one possible implementation, the device includes a serial communication chip, which is used to send signals output by the control chip to a connected display device so as to display the grounding status of the external device through the display device.

[0016] In one possible implementation, the device further includes a grounding status indication component. If the control chip determines that an external device has an abnormal grounding status, the output signal of the control chip triggers the grounding status indication component to issue an alarm signal. If the control chip determines that the grounding status of all grounded devices is normal, the output signal of the control chip triggers the grounding status indication component to issue a safety signal.

[0017] In one possible implementation, the grounding status indication component includes at least one of the following: an audible signal indication component and an optical signal indication component.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application.

[0020] Figure 1 A schematic diagram of a grounding status monitoring device provided in an exemplary embodiment of this application is shown;

[0021] Figure 2 A schematic diagram of a grounding status monitoring device provided in another exemplary embodiment of this application is shown;

[0022] Figure 3 A schematic diagram illustrating the on / off state of a transistor as shown in an exemplary embodiment of this application is provided.

[0023] Figure 4 A schematic diagram of a NAND gate chip provided in an exemplary embodiment of this application is shown;

[0024] Figure 5 A schematic diagram of an OR gate chip provided in an exemplary embodiment of this application is shown;

[0025] Figure 6 A schematic diagram of a control chip illustrating an exemplary embodiment of this application is shown;

[0026] Figure 7 A schematic diagram of a secondary OR gate chip provided in an exemplary embodiment of this application is shown;

[0027] Figure 8 A schematic diagram of the encapsulated grounding status monitoring device is shown. Detailed Implementation

[0028] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "positive", "negative", "far", "near", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] The following is combined Figures 1-8 This application describes the grounding status monitoring device provided in the embodiments of this application.

[0033] This application provides a grounding status monitoring device that can determine the grounding status of external devices based on signal processing using logical operations, thereby improving the accuracy and reliability of monitoring. Figure 1 A schematic diagram of a grounding status monitoring device provided in an exemplary embodiment of this application is shown, such as... Figure 1 As shown, the device includes multiple external device ports 110, transistors 120 configured corresponding to each external device port 110, a ground port 130, a logic gate circuit chip 140, and a control chip 150.

[0034] External device port 110 is used to connect external devices, and grounding port 130 is used for grounding;

[0035] The monitoring signal from the external device port 110 and the feedback signal from the ground port 130 are used to control the on / off state of the corresponding transistor 120;

[0036] The logic gate chip 140 includes a NAND gate chip and an OR gate chip; the two input terminals of the NAND gate in the NAND gate chip are respectively connected to the signal output terminal of a transistor 120, and perform NAND logic operation on the received signal; the two input terminals of the OR gate in the OR gate chip are respectively connected to the output terminal of a NAND gate, and perform OR logic operation on the received signal.

[0037] The control chip 150 is connected to the output terminal of the OR gate chip and is used to output a signal based on the potential state of the output terminal of the OR gate chip; the signal output by the control chip 150 is used to indicate the grounding status of the external device.

[0038] The external device port 110 is used to connect external devices. In one possible implementation, multiple external device ports can be compatible with one or more types of external device interface standards, such as USB, HDMI, etc. Through these ports, external devices can establish an electrical connection with the grounding status monitoring device for grounding status monitoring. When an external device is connected, the external device port 110 generates a corresponding monitoring signal, which reflects the electrical characteristics and connection status information of the external device.

[0039] Each external device port 110 pair should be equipped with a transistor 120. The transistor 120 can be used to receive the monitoring signal from the external device port 110 and the feedback signal from the ground port 130. Based on the logical combination of these two signals, the transistor 120 realizes the on / off control.

[0040] The grounding port 130 is at a low potential with the grounding status monitoring device and sends a feedback signal to the transistor 120. This feedback signal, together with the monitoring signal from the external device port 110, acts on the transistor 120 to determine the grounding status of the external device. For example, if the external device is properly grounded, there will be a specific potential relationship between the monitoring signal and the feedback signal; otherwise, there will be a difference. This difference can be reflected by the on / off state of the transistor 120.

[0041] The logic gate chip 140 includes NAND gates and OR gates. The NAND gates in the NAND chip perform NAND logic operations on the signals received from the two transistors 120. That is, when both inputs are high, the output of the NAND gate is low; otherwise, it outputs a high level, thus integrating the grounding status information of different ports. The OR gates in the OR chip have their two inputs connected to the outputs of one of the NAND gates. They perform OR logic operations on the received signals. When the output of one of the NAND gates is high, the output of the OR gate is also high, thereby combining the processing results of multiple NAND gates so that the subsequent control chip can make a judgment based on a unified signal.

[0042] The control chip 150 is connected to the output of the OR gate chip to monitor the potential state of the OR gate chip's output in real time. Based on this potential state, the control chip 150 outputs a signal. For example, in one possible scenario, if the OR gate chip outputs a high level, the control chip 150 can determine that at least one external device has a grounding abnormality, and the control chip 150 outputs a corresponding fault indication signal; if the OR gate chip outputs a low level, it indicates that all external devices are grounded normally, and the control chip 150 outputs a normal status signal.

[0043] When an external device is connected to external device port 110, external device port 110 generates a monitoring signal and transmits it to the corresponding transistor 120. Simultaneously, the feedback signal from ground port 130 also acts on transistor 120. Transistor 120 switches on and off based on the combination of these two signals, and its output signal is sent to logic gate chip 140. The NAND gate chip in logic gate chip 140 performs NAND operations on the output signals of multiple transistors 120, integrating the grounding information from different external device ports. Then, the OR gate chip performs an OR operation on the output result of the NAND gate chip to obtain a comprehensive potential status signal. Control chip 150 determines the overall grounding status of the external device based on the output potential status of the OR gate chip and outputs a corresponding indication signal.

[0044] In summary, the grounding status monitoring device provided in this application includes multiple external device ports, transistors configured corresponding to each external device port, a grounding port, logic gate circuit chips, and a control chip. The external device ports are used to connect external devices, and the grounding port is grounded. The monitoring signal from the external device port and the feedback signal from the grounding port are used to control the on / off state of the corresponding transistors. The logic gate circuit chips include NAND gate chips and OR gate chips. The two input terminals of the NAND gate in the NAND gate chip are each connected to the signal output terminal of a transistor. The two input terminals of the OR gate in the OR gate chip are each connected to the output terminal of a NAND gate. The control chip is connected to the output terminal of the OR gate chip and is used to output a signal indicating the grounding status of the external device based on the potential state of the OR gate chip's output terminal. Through this grounding status monitoring device, the grounding status of the external device can be accurately determined based on the monitoring signal from the external device port and the feedback signal from the grounding port. This signal processing method based on logic operations can effectively avoid misjudgments and improve the accuracy and reliability of monitoring. In addition, by setting up multiple external device ports, the grounding status of multiple devices to be monitored can be monitored simultaneously, which can improve monitoring efficiency.

[0045] In one possible implementation, the grounding status monitoring device further includes switching components configured corresponding to each external device port; this effectively isolates unused ports, preventing the intrusion of external interference signals and further improving the accuracy of device status monitoring. In this case, Figure 2 A schematic diagram of a grounding status monitoring device provided in another exemplary embodiment of this application is shown, such as... Figure 2 As shown, the grounding status monitoring device includes multiple external device ports 110, transistors 120 configured corresponding to each external device port 110, grounding ports 130, logic gate circuit chips 140, and control chips 150.

[0046] External device port 110 is used to connect external devices, and grounding port 130 is used for grounding;

[0047] The monitoring signal from the external device port 110 and the feedback signal from the ground port 130 are used to control the on / off state of the corresponding transistor 120;

[0048] The logic gate chip 140 includes a NAND gate chip and an OR gate chip; the two input terminals of the NAND gate in the NAND gate chip are respectively connected to the signal output terminal of a transistor 120, and perform NAND logic operation on the received signal; the two input terminals of the OR gate in the OR gate chip are respectively connected to the output terminal of a NAND gate, and perform OR logic operation on the received signal.

[0049] The control chip 150 is connected to the output terminal of the OR gate chip and is used to output a signal based on the potential state of the output terminal of the OR gate chip; the signal output by the control chip 150 is used to indicate the grounding status of the external device.

[0050] In addition, the device also includes a switch assembly 160 configured corresponding to each external device port 110; the circuit where the switch assembly 160 is located is connected in parallel with the circuit where the corresponding external device port 110 is located.

[0051] When an external device is connected to the external device port 110, the corresponding switch assembly 160 is in the open state; when no external device is connected to the external device port 110, the corresponding switch assembly 160 is in the closed state.

[0052] When an external device is connected to the external device port, setting the switch assembly 160 to the ON state allows the monitoring signal fed back from the external device port to reflect the current grounding status of the external device. However, when no external device is connected to the external device port, if the switch assembly 160 is not set or is in the ON state, the monitoring signal of that external device port will reflect that it is not grounded, thus affecting other external device ports. Therefore, in this case, by setting the switch assembly 160 to the OFF state, the monitoring signal of the external device port will reflect that it is grounded, thereby avoiding affecting other devices.

[0053] Furthermore, the number of connected devices can be adjusted by regulating the open / closed state of the switch assembly 160. In one possible implementation, the switch assembly 160 can be a bar switch.

[0054] In practical applications, when both the monitoring signal from the external device port 110 and the feedback signal from the ground port 130 are low-level signals, the input of the NAND gate is a first-level signal; when the monitoring signal from the external device port 110 is a high-level signal and the feedback signal from the ground port 130 is a low-level signal, the input of the NAND gate is a second-level signal; the first-level signal and the second-level signal are different.

[0055] Depending on the connection between the external device port, the ground port, and the transistor, the signal type at the input of the NAND gate may differ. For example, if both the monitoring signal from external device port 110 and the feedback signal from ground port 130 are low-level signals, the corresponding input of the NAND gate will be a high-level signal; if the monitoring signal from external device port 110 is high-level and the feedback signal from ground port 130 is low-level, the input of the NAND gate will be low-level; or, if both the monitoring signal from external device port 110 and the feedback signal from ground port 130 are low-level signals, the corresponding input of the NAND gate will be low-level; if the monitoring signal from external device port 110 is high-level and the feedback signal from ground port 130 is low-level, the input of the NAND gate will be high-level.

[0056] Indicatively, each external device port 110 is equipped with an NPN transistor corresponding to an NPN transistor; the base of the transistor 120 is connected to the external device port 110, the emitter of the transistor 120 is connected to the ground port 130, and the collector of the transistor 120 is connected to a NAND gate and the positive power supply.

[0057] An NPN transistor consists of two N-type semiconductors sandwiching a P-type semiconductor. Its operating principle is based on the control of the collector-emitter current by the base current. When the PN junction between the base and emitter is forward biased (base voltage higher than emitter voltage), a base current is generated. Under certain conditions, an amplified collector current is also generated between the collector and emitter.

[0058] In this case, when the external device is properly grounded, the potential of the external device port 110 is relatively low (close to the ground potential), that is, the base input is low level, the NPN transistor is cut off, the collector potential is close to the positive power supply voltage, and a high level signal is output. This high level signal will be transmitted to the input of the corresponding NAND gate.

[0059] When the external device is not properly grounded, the potential of port 110 of the external device may be high (higher than the potential when grounded), that is, the base input is high level, the NPN transistor is turned on. Since the emitter is grounded, the collector is connected to the positive power supply and the NAND gate. When the transistor is turned on, there is an approximate short circuit between the collector and the emitter, the collector potential is pulled low, close to the ground potential, and the collector outputs a low level signal. This low level signal will be transmitted to the input of the corresponding NAND gate.

[0060] Taking the transistor 120 configured for each external device port 110 as an example, which is an NPN type transistor, Figure 3 A schematic diagram illustrating the on / off state of a transistor as shown in an exemplary embodiment of this application is provided, as follows: Figure 3 As shown, each of the four external device ports ID1 to ID4 is equipped with its own NPN transistor. The base of each transistor is connected to the external device port, the emitter is connected to the ground port, and the collector is connected to a NAND gate and the positive power supply. The signal input of the transistors corresponding to external device ports ID1 and ID2 is NAND gate 1, and the signal input of the transistors corresponding to external device ports ID3 and ID4 is NAND gate 2. When the external device connected to external device port ID1 is not properly grounded, the corresponding external device port is at a high potential, the corresponding transistor is turned on, and the collector output is low. When the external device connected to port ID2 is properly grounded, its corresponding port is at a low potential, the corresponding transistor is cut off, and the collector outputs a high-level signal. After inputting the output signals of the transistors corresponding to ID1 and ID2 into NAND gate 1, NAND gate 1 outputs a high-level signal. Similarly, when the external devices connected to ports ID3 and ID4 are both properly grounded, the signals input to NAND gate 2 are both high-level signals, and NAND gate 2 outputs a low-level signal. The output signals of NAND gate 1 and NAND gate 2 are respectively input into an OR gate, and the OR gate outputs a high-level signal.

[0061] In one possible implementation, a NAND gate chip can integrate multiple NAND gates. Each NAND gate has two corresponding input terminals, and each input terminal is connected to the signal output terminal of a transistor. Correspondingly, each NAND gate has a corresponding output terminal. For example, if a NAND gate chip integrates four NAND gates, then the NAND gate chip has output terminals corresponding to each NAND gate; that is, a NAND gate chip has four output terminals. Figure 4 A schematic diagram of a NAND gate chip provided in an exemplary embodiment of this application is shown, as follows: Figure 4 As shown, NAND gate chip U1 and NAND gate chip U2 each integrate four NAND gates. The two input terminals of each NAND gate are connected to the output terminals of two transistors, respectively. Figure 4The output terminals of transistors Q1-Q16 are connected to NAND gate chips U1 and U2 respectively. When the external devices ID1 to ID16 are all at low level, the 5V positive terminal outputs current through R5-R32 to the logic input terminals (1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B) of U1-U2. The judgment result is output by 1Y, 2Y, 3Y, and 4Y of each NAND gate chip.

[0062] Optionally, a reverse connection protection diode can be configured between the external device port 110 and the transistor 120, such as... Figure 4 The diodes D1-D16 shown are to prevent reverse connection from burning out the circuit.

[0063] An OR gate chip can integrate multiple OR gates, each with two inputs. Each input is connected to the output of a NAND gate. Correspondingly, the OR gate chip can have outputs corresponding to multiple OR gates. For example, if an OR gate chip integrates four OR gates, then the chip has outputs corresponding to each OR gate; that is, the OR gate chip has four outputs. Figure 5 A schematic diagram of an OR gate chip provided in an exemplary embodiment of this application is shown, as follows: Figure 5 As shown, the OR gate chip U3 integrates four OR gates, corresponding to eight input ports, namely Out1-Out8, and four output ports, namely O1-O4.

[0064] Since the number of input ports of NAND gate chips and OR gate chips is limited, when there are a large number of external devices that need to be monitored for grounding status, multiple NAND gate chips and OR gate chips need to be configured.

[0065] Furthermore, since the number of input ports of the control chip is limited, in order to ensure that the output signal of the OR gate chip can be transmitted to the control chip, the device can be configured with multiple levels of OR gate chips. The input of each level of OR gate chip is the output of the OR gate chip of the previous level. The number of output signals of the last level of OR gate chip is consistent with the number of input ports of the control chip 150. By performing one or more OR operations on the output signals of the NAND gate chip through multiple levels of OR gate chips, the number of output signals of the last level of OR gate chip is consistent with the number of input ports of the control chip, thereby ensuring that the monitoring signals of each external device can be transmitted to the control chip 150. Figure 6 A schematic diagram of a control chip illustrating an exemplary embodiment of this application is shown, such as... Figure 6 As shown, the control chip U5 has two input interfaces, IO2 and IO3. In this case, it can be used as follows: Figure 4 The NAND gate chip shown and as Figure 5Taking the OR gate chip shown as an example, it can monitor the grounding status of 16 external devices and output four output signals. When the control chip 150 has two input terminals, further OR operation is required to ensure that the signal output by the OR gate chip can be connected to the control chip 150. In this case, two levels of OR gate chips can be deployed. The input terminals of the second-level OR gate chip are connected to one output terminal of the first-level OR gate chip respectively. The control chip 150 is connected to the output terminal of the second-level OR gate chip. Figure 7 A schematic diagram of a secondary OR gate chip provided in an exemplary embodiment of this application is shown, such as... Figure 7 As shown, the input terminal of the secondary OR gate chip U4 receives four output signals O1-O4 from the primary OR gate chip U3, and the output terminal receives two output signals D2-D3, which are then transmitted to the input port of the control chip 150.

[0066] It should be noted that the number of secondary OR gate chips can be configured based on the different number of input ports of the control chip. For example, when the control chip has only one input port, a secondary OR gate chip still needs to be configured to integrate the two output signals from the previous secondary OR gate chip into one input to the control chip; or, when the control chip has four input ports, there is no need to configure secondary OR gate chips, and the four input signals from the primary OR gate chip can be directly connected to the control chip, and so on. Based on the different number of input ports of different chip specifications, the number of various chips can be flexibly adjusted according to actual needs. The chip types and quantities provided in the embodiments of this application are only illustrative and this application does not impose any limitations on them.

[0067] Optionally, the device includes a serial communication chip 170, which is used to send the signal output by the control chip 150 to the connected display device so as to display the grounding status of the external device through the display device.

[0068] The serial communication chip 170 can interact with the control chip 150 via a standard serial communication protocol, receiving specific format signals output by the control chip 150. These signals are processed by the signal conditioning and conversion circuitry within the serial communication chip 170, and then adapted into a data format suitable for transmission on the display device's communication interface before being sent to the connected display device. Upon receiving the data, the display device, according to preset display rules and interface layout, displays the grounding status of the external device in intuitive graphical, textual, or indicator light formats. For example, when the external device is properly grounded, the display device may show a green indicator light and the text "Grounding Normal"; conversely, when a grounding fault occurs, a red indicator light will flash and a "Grounding Fault" warning message will be displayed. This allows operators to quickly and accurately understand the grounding status of the external device and take timely measures for maintenance or repair.

[0069] Optionally, the device also includes a grounding status indication component 180. If the control chip 150 determines that there is an external device with an abnormal grounding status, the output signal of the control chip 150 triggers the grounding status indication component 180 to issue an alarm signal; if the control chip 150 determines that the grounding status of all grounded devices is normal, the output signal of the control chip 150 triggers the grounding status indication component 180 to issue a safety signal.

[0070] The grounding status indication component 180 may include at least one of the following: an audible signal indication component and an optical signal indication component. For example, if the grounding status indication component 180 is an audible signal indication component, the alarm signal may be a continuous loud beep, and the safety signal may be a brief beep, such as a brief "beep". If the grounding status indication component 180 is an optical signal indication component, the alarm signal may be a warning light of the target color, or it may be a flashing warning light of the target color with a relatively fast flashing frequency, such as a flashing red warning light. The safety signal may be a solid green indicator light, etc. Furthermore, the grounding status indication component 180 may emit both audible and optical signals to help operators understand the grounding status of external equipment, make timely operational or maintenance decisions, and ensure the safety and reliability of equipment operation.

[0071] In one possible implementation, the grounding status monitoring device provided in this application embodiment can be encapsulated in a device housing to protect the grounding status monitoring device through the housing; Figure 8 A schematic diagram of the packaged grounding status monitoring device is shown, such as... Figure 8As shown, the device housing 810 encapsulates the grounding status monitoring device 820 provided in this application embodiment. The device housing 810 provides interfaces corresponding to the grounding status monitoring device 820, such as external device ports, grounding ports, interfaces for connecting serial communication chips, and interfaces for connecting grounding status indication components, etc.

[0072] In summary, the grounding status monitoring device provided in this application includes multiple external device ports, transistors configured corresponding to each external device port, a grounding port, logic gate circuit chips, and a control chip. The external device ports are used to connect external devices, and the grounding port is grounded. The monitoring signal from the external device port and the feedback signal from the grounding port are used to control the on / off state of the corresponding transistors. The logic gate circuit chips include NAND gate chips and OR gate chips. The two input terminals of the NAND gate in the NAND gate chip are each connected to the signal output terminal of a transistor. The two input terminals of the OR gate in the OR gate chip are each connected to the output terminal of a NAND gate. The control chip is connected to the output terminal of the OR gate chip and is used to output a signal indicating the grounding status of the external device based on the potential state of the OR gate chip's output terminal. Through this grounding status monitoring device, the grounding status of the external device can be accurately determined based on the monitoring signal from the external device port and the feedback signal from the grounding port. This signal processing method based on logic operations can effectively avoid misjudgments and improve the accuracy and reliability of monitoring. In addition, by setting up multiple external device ports, the grounding status of multiple devices to be monitored can be monitored simultaneously, which can improve monitoring efficiency.

[0073] Furthermore, by setting up switch components, unused ports can be effectively isolated when no external devices are connected, preventing the intrusion of external interference signals, further improving the accuracy of device status monitoring, and reducing unnecessary circuit energy loss, which helps to improve the stability and safety of the entire device.

[0074] By setting up a grounding status indicator component and a serial communication chip for connecting external display devices, the grounding status of the device can be fed back in a timely manner. When the grounding status of the device is abnormal, an alarm can be issued in time to remind the user, thereby avoiding safety accidents and equipment damage that may be caused by poor grounding.

[0075] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0076] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A grounding status monitoring device, characterized in that, The device includes multiple external device ports (110), transistors (120) configured corresponding to each external device port (110), ground ports (130), logic gate circuit chips (140), and control chips (150); The external device port (110) is used to connect external devices, and the grounding port (130) is grounded; The monitoring signal of the external device port (110) and the feedback signal of the ground port (130) are used to control the on / off state of the corresponding transistor (120); The logic gate chip (140) includes a NAND gate chip and an OR gate chip; the two input terminals of the NAND gate in the NAND gate chip are respectively connected to the signal output terminal of a transistor (120) and perform NAND logic operation on the received signal; the two input terminals of the OR gate in the OR gate chip are respectively connected to the output terminal of a NAND gate and perform OR logic operation on the received signal. The control chip (150) is connected to the output terminal of the OR gate chip and is used to output a signal based on the potential state of the output terminal of the OR gate chip; the signal output by the control chip (150) is used to indicate the grounding state of the external device.

2. The device according to claim 1, characterized in that, When both the monitoring signal from the external device port (110) and the feedback signal from the ground port (130) are low-level signals, the input of the NAND gate is a first-level signal; when the monitoring signal from the external device port (110) is high-level and the feedback signal from the ground port (130) is low-level, the input of the NAND gate is a second-level signal; the first-level signal and the second-level signal are different.

3. The device according to claim 2, characterized in that, Each external device port (110) is equipped with an NPN transistor (120); the base of the transistor (120) is connected to the external device port (110), the emitter of the transistor (120) is connected to the ground port (130), and the collector of the transistor (120) is connected to a NAND gate and a positive power supply.

4. The device according to claim 1, characterized in that, The device includes multiple levels of OR gate chips, with the input of each level of OR gate chip being the output of the previous level of OR gate chip; the number of output signals of the last level of OR gate chip is consistent with the number of input ports of the control chip (150).

5. The device according to claim 1, characterized in that, The device also includes a switch assembly (160) configured corresponding to each external device port (110); the circuit where the switch assembly (160) is located is connected in parallel with the circuit where the corresponding external device port (110) is located; When an external device is connected to the external device port (110), the switch assembly (160) corresponding to the external device port (110) is in the open state; when no external device is connected to the external device port (110), the switch assembly (160) corresponding to the external device port (110) is in the closed state.

6. The device according to claim 1, characterized in that, The device includes a serial communication chip (170), which is used to send the signal output by the control chip (150) to the connected display device so as to display the grounding status of the external device through the display device.

7. The device according to claim 1, characterized in that, The device also includes a grounding status indication component (180). When the control chip (150) determines that there is an external device with an abnormal grounding status, the output signal of the control chip (150) triggers the grounding status indication component (180) to issue an alarm signal; when the control chip (150) determines that the grounding status of all grounding devices is normal, the output signal of the control chip (150) triggers the grounding status indication component (180) to issue a safety signal.

8. The device according to claim 7, characterized in that, The grounding status indication component (180) includes at least one of the following: an audible signal indication component and an optical signal indication component.

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