10Gbps rate gain pre-emphasis circuit

Abstract

The utility model discloses a 10Gbps rate gain pre-emphasis circuit, which comprises an Image circuit and a Delay circuit, the Image circuit comprises a first input pair transistor group, and the Delay circuit comprises a second input pair transistor group; one side of the first input geminate transistor group is provided with a first voltage dividing geminate transistor group, one side of the second input geminate transistor group is provided with a second voltage dividing geminate transistor group, a drain electrode of the first voltage dividing geminate transistor group is connected with a source electrode of the first input geminate transistor group, and a drain electrode of the second voltage dividing geminate transistor group is connected with a source electrode of the second input geminate transistor group; the source electrode of the first voltage-dividing pair transistor group and the source electrode of the second voltage-dividing pair transistor group are connected with an output resistor; the output end of the first input pair transistor group is connected with the Image channel mos transistor group, and the output end of the second input pair transistor group is connected with the Delay channel mos transistor group; according to the utility model, signal transmission can be carried out at a higher rate and higher pre-emphasis intensity, and the voltage withstanding performance of the pre-emphasis circuit can be ensured at the same time.

Description

Technical Field

[0001] This utility model belongs to the technical field of pre-emphasis circuits, and relates to a 10Gbps rate gain pre-emphasis circuit. Background Technology

[0002] The existing CML logic level driver circuit with pre-emphasis function generates a CML logic level signal by subtracting the circuits of the Imain channel and the Delay channel and outputting the result to the output resistor. The pre-emphasis intensity is adjusted by setting the differential signal control register to adjust the signal delay in the Imain and Delay channels. The Imain channel consists of an input pair of two MOSFETs and a tail current pair of two MOSFETs, while the Delay channel consists of an input pair of two MOSFETs and a tail current MOSFET.

[0003] This results in the tail current of the Imain channel being I in existing CML logic level drive circuits with pre-emphasis functionality. main +I pre The tail current of the Delay channel is I. pre Therefore, the final differential amplitude of the signal output through the output resistor R0 is (I main +2I pre )×R0, the intraocular difference amplitude is I main ×R0, the pre-weighting strength is 20×log[(I main +2I pre ) / I main It can be concluded that its pre-emphasis strength is limited, and under the premise of ensuring a conversion rate of 10Gbps, if low-voltage high-speed MOSFETs with a threshold voltage of 1V are selected as the input pair transistors of the Imain and Delay channels according to the existing pre-emphasis circuit, there will be a risk of voltage withstand failure.

[0004] Therefore, in view of the shortcomings of existing pre-emphasis circuits, such as limited pre-emphasis strength and the risk of voltage withstand failure, this utility model provides a 10Gbps rate gain pre-emphasis circuit. Utility Model Content

[0005] The purpose of this invention is to provide a 10Gbps rate gain pre-emphasis circuit that can transmit signals at a higher rate and with a higher pre-emphasis intensity, while ensuring the voltage withstand performance of the pre-emphasis circuit.

[0006] This utility model is achieved through the following technical solution:

[0007] A 10Gbps rate gain pre-emphasis circuit includes an Imain circuit and a Delay circuit. The Imain circuit includes a first input transistor pair, and the Delay circuit includes a second input transistor pair. A first voltage divider pair is disposed on one side of the first input transistor pair, and a second voltage divider pair is disposed on one side of the second input transistor pair. The drain of the first voltage divider pair is connected to the source of the first input transistor pair, and the drain of the second voltage divider pair is connected to the source of the second input transistor pair. The sources of the first and second voltage divider pairs are connected to an output resistor. The output terminal of the first input transistor pair is connected to the Imain channel MOSFET group, and the output terminal of the second input transistor pair is connected to the Delay channel MOSFET group.

[0008] To better realize this utility model, further, the first input transistor pair includes a first input MOSFET and a second input MOSFET, and the first voltage divider transistor pair includes a first voltage divider MOSFET and a second voltage divider MOSFET; the source of the first voltage divider MOSFET is connected to the output resistor, and the drain of the first voltage divider MOSFET is connected to the source of the first input MOSFET; the source of the second voltage divider MOSFET is connected to the output resistor, and the drain of the second voltage divider MOSFET is connected to the source of the second input MOSFET; the drains of both the first and second input MOSFETs are connected to the Imain channel MOSFET group.

[0009] To better realize this utility model, furthermore, the gates of the first voltage divider MOSFET and the second voltage divider MOSFET are both connected to a bias voltage circuit.

[0010] To better realize this utility model, the Imain channel MOSFET group further includes MOSFET No. 5 and MOSFET No. 6. The source of MOSFET No. 5 is connected to the drain of input MOSFET No. 1 and the drain of input MOSFET No. 2. The drain of MOSFET No. 5 is connected to the source of MOSFET No. 6. The drain of MOSFET No. 6 is grounded.

[0011] To better realize this utility model, further, the threshold voltage of the first input MOSFET, the second input MOSFET, the first voltage divider MOSFET, and the second voltage divider MOSFET is less than or equal to 1V; the substrate and source of the first input MOSFET, the second input MOSFET, the first voltage divider MOSFET, and the second voltage divider MOSFET are connected.

[0012] To better realize this utility model, further, the second input transistor pair includes a third input MOSFET and a fourth input MOSFET, and the second voltage divider transistor pair includes a third voltage divider MOSFET and a fourth voltage divider MOSFET; the source of the third voltage divider MOSFET is connected to the output resistor, and the drain of the third voltage divider MOSFET is connected to the source of the third input MOSFET; the source of the fourth voltage divider MOSFET is connected to the output resistor, and the drain of the fourth voltage divider MOSFET is connected to the source of the fourth input MOSFET; the drains of both the third and fourth input MOSFETs are connected to the Delay channel MOSFET group.

[0013] To better realize this utility model, furthermore, the gates of the third voltage divider MOSFET and the fourth voltage divider MOSFET are both connected to a bias voltage circuit.

[0014] To better realize this utility model, the Delay channel MOSFET group further includes MOSFET No. 7 and MOSFET No. 8. The source of MOSFET No. 7 is connected to the drain of input MOSFET No. 3 and the drain of input MOSFET No. 4. The drain of MOSFET No. 7 is connected to the source of MOSFET No. 8. The drain of MOSFET No. 8 is grounded.

[0015] To better realize this utility model, furthermore, the threshold voltage of the No. 3 input MOSFET, No. 4 input MOSFET, No. 3 voltage divider MOSFET, and No. 4 voltage divider MOSFET is less than or equal to V; the substrate and source of the No. 3 input MOSFET, No. 4 input MOSFET, No. 3 voltage divider MOSFET, and No. 4 voltage divider MOSFET are connected.

[0016] Compared with the prior art, this utility model has the following advantages and beneficial effects:

[0017] This invention enables signal transmission at a higher rate and with a higher pre-emphasis intensity, while ensuring the voltage withstand performance of the pre-emphasis circuit. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit architecture of this utility model;

[0019] Figure 2 This is a schematic diagram of the specific circuit of this utility model;

[0020] Figure 3 This is a schematic diagram of the current in the Imain circuit;

[0021] Figure 4 This is a schematic diagram of the current in the Delay circuit;

[0022] Figure 5 A schematic diagram for calculating the current difference between the Inmain circuit and the Delay circuit.

[0023] Wherein: 1-First input transistor pair; 2-Second input transistor pair; 3-First voltage divider transistor pair; 4-Second voltage divider transistor pair; 5-Output resistor; 6-Imain channel MOSFET pair; 7-Delay channel MOSFET pair; M1-Input MOSFET 1; M2-Input MOSFET 2; M3-Input MOSFET 3; M4-Input MOSFET 4; M5-MOSFET 5; M6-MOSFET 6; M7-MOSFET 7; M8-MOSFET 8; M11-Voltage divider MOSFET 1; M12-Voltage divider MOSFET 2; M13-Voltage divider MOSFET 3; M14-Voltage divider MOSFET 4. Detailed Implementation

[0024] The following detailed description is illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to the present invention. As used herein, unless otherwise expressly indicated by the present invention, the singular form is intended to include the plural form as well. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] For ease of description, the words "up," "down," "left," and "right" appearing in this utility model only indicate that they are consistent with the up, down, left, and right directions of the accompanying drawings themselves, and do not limit the structure. They are merely for the purpose of facilitating the description of this utility model and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0027] Terminology Explanation: The terms "installation," "connection," "linking," and "fixing" in this utility model should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction relationship between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0028] Example 1:

[0029] This embodiment provides a 10Gbps rate gain pre-emphasis circuit, such as... Figure 1 and Figure 2 As shown, the circuit includes an Imain circuit and a Delay circuit. The Imain circuit includes a first input transistor pair 1, and the Delay circuit includes a second input transistor pair 2. A first voltage divider pair 3 is disposed on one side of the first input transistor pair 1, and a second voltage divider pair 4 is disposed on one side of the second input transistor pair 2. The drain of the first voltage divider pair 3 is connected to the source of the first input transistor pair 1, and the drain of the second voltage divider pair 4 is connected to the source of the second input transistor pair 2. The sources of the first voltage divider pair 3 and the second voltage divider pair 4 are connected to an output resistor 5. The output terminal of the first input transistor pair 1 is connected to an Imain channel MOSFET group 6, and the output terminal of the second input transistor pair 2 is connected to a Delay channel MOSFET group 7.

[0030] The threshold voltages of the first input transistor pair 1, the second input transistor pair 2, the first voltage divider transistor pair 3, and the second voltage divider transistor pair 4 are less than or equal to 1V, preferably 1V. The first input transistor pair 1, the second input transistor pair 2, the first voltage divider transistor pair 3, and the second voltage divider transistor pair 4 use 1V DNW MOSFETs, which are smaller in size, have lower threshold voltages, and lower parasitic parameters than 1.8V MOSFETs, thus enabling the pre-emphasis circuit to achieve a slew rate of 10Gbps.

[0031] like Figure 1 The 10Gbps rate gain pre-emphasis circuit shown has an input power supply of 1.8V. However, the threshold voltages of the first input transistor pair 1 and the second input transistor pair 2 are 1V. To avoid overvoltage of the first input transistor pair 1 and the second input transistor pair 2, a first voltage divider pair 3 is set on one side of the first input transistor pair 1 for voltage division, and a second voltage divider pair 4 is set on one side of the second input transistor pair 2 for voltage division. This ensures that the voltages of the first input transistor pair 1, the second input transistor pair 2, the first voltage divider pair 3, and the second voltage divider pair 4 are all less than the threshold voltage, thus ensuring the safety of the entire pre-emphasis circuit.

[0032] like Figure 3 As shown, this utility model eliminates the I in the wake of the existing pre-emphasis circuit Imain circuit. pre Wake, only I was retained main Wake. For example... Figure 4 As shown, the delay circuit output holds I. pre Wake. The final result is as follows: Figure 5 The total current is obtained by subtracting the currents of the Imain circuit and the Delay circuit shown.

[0033] The final differential amplitude of the signal output through output resistor 5 is:

[0034] Voeppd=(I main +Ipre )×R0;

[0035] Where: Voeppd represents the amplitude of the external eye difference; I main I represents the current in the main circuit; pre R0 represents the current in the Delay circuit; R0 represents the resistance value of the output resistor.

[0036] The final intraocular differential amplitude of the signal output through output resistor 5 is:

[0037] Vieppd=(I main -I pre )×R0;

[0038] Vieppd represents the amplitude of intraocular difference; I main I represents the current in the main circuit; pre R0 represents the current in the Delay circuit; R0 represents the resistance value of the output resistor.

[0039] The pre-weighting strength is:

[0040]

[0041] Where: K represents the pre-weighting intensity.

[0042] Example 2:

[0043] A 10Gbps rate gain pre-emphasis circuit, an improvement on embodiment 1, is as follows: Figure 2 As shown, the first input transistor pair 1 includes input MOSFET M1 and input MOSFET M2, and the first voltage divider transistor pair 3 includes voltage divider MOSFET M11 and voltage divider MOSFET M12. The source of voltage divider MOSFET M11 is connected to the output resistor 5, and the drain of voltage divider MOSFET M11 is connected to the source of input MOSFET M1. The source of voltage divider MOSFET M12 is connected to the output resistor 5, and the drain of voltage divider MOSFET M12 is connected to the source of input MOSFET M2. The drains of input MOSFET M1 and input MOSFET M2 are both connected to the Imain channel MOSFET pair 6.

[0044] like Figure 2 As shown, the gates of input MOSFET M1 and input MOSFET M2 are connected to the INP and INN signal paths of the differential signal, respectively. A differential control register 8 is connected between the INP and INN signal paths. The delay of the differential signal in the Imain and Delay circuits can be adjusted through the differential control register 8, thereby adjusting the final pre-emphasis width.

[0045] Furthermore, such as Figure 2As shown, the gates of the first voltage divider MOSFET M11 and the second voltage divider MOSFET M12 are both connected to a bias voltage circuit. The bias voltage circuit inputs a bias voltage Vbn to the gates of the first voltage divider MOSFET M11 and the second voltage divider MOSFET M12. By adjusting the value of the bias voltage Vbn, the terminal voltages of the first input MOSFET M1, the second input MOSFET M2, the first voltage divider MOSFET M11, and the second voltage divider MOSFET M12 are all less than or equal to the threshold voltage, i.e., less than or equal to 1V, effectively preventing overvoltage of the first input MOSFET M1, the second input MOSFET M2, the first voltage divider MOSFET M11, and the second voltage divider MOSFET M12.

[0046] The other parts of this embodiment are the same as those in Embodiment 1, so they will not be described again.

[0047] Example 3:

[0048] A 10Gbps rate gain pre-emphasis circuit, improved based on Embodiment 1 or 2, such as... Figure 2 As shown, the second input transistor pair 2 includes input MOSFET M3 (number 3) and input MOSFET M4 (number 4), and the second voltage divider transistor pair 4 includes voltage divider MOSFET M13 (number 3) and voltage divider MOSFET M14 (number 4). The source of voltage divider MOSFET M13 is connected to the output resistor 5, and the drain of voltage divider MOSFET M13 is connected to the source of input MOSFET M3. The source of voltage divider MOSFET M14 is connected to the output resistor 5, and the drain of voltage divider MOSFET M14 is connected to the source of input MOSFET M4. The drains of both input MOSFET M3 and input MOSFET M4 are connected to the Delay channel MOSFET pair 7.

[0049] like Figure 2 As shown, the gates of input MOSFET M3 (number 3) and input MOSFET M4 (number 4) are connected to the INP and INN signal paths of the differential signal, respectively, and a differential control register 8 is connected between the INP and INN signal paths.

[0050] Furthermore, the gates of the third voltage divider MOSFET M13 and the fourth voltage divider MOSFET M14 are both connected to a bias voltage circuit. The bias voltage circuit inputs a bias voltage Vbn to the gates of the third voltage divider MOSFET M13 and the fourth voltage divider MOSFET M14. By adjusting the value of the bias voltage Vbn, the terminal voltages of the third input MOSFET M3, the fourth input MOSFET M4, the third voltage divider MOSFET M13, and the fourth voltage divider MOSFET M14 are all less than or equal to the threshold voltage, i.e., less than or equal to 1V, effectively preventing overvoltage of the third input MOSFET M3, the fourth input MOSFET M4, the third voltage divider MOSFET M13, and the fourth voltage divider MOSFET M14.

[0051] The other parts of this embodiment are the same as those in Embodiment 1 or 2, so they will not be described again.

[0052] Example 4:

[0053] A 10Gbps rate gain pre-emphasis circuit, improved based on any one of embodiments 1-3, includes a main channel MOSFET group 6 comprising MOSFET M5 (number 5) and MOSFET M6 (number 6). The source of MOSFET M5 is connected to the drain of input MOSFET M1 (number 1) and the drain of input MOSFET M2 (number 2). The drain of MOSFET M5 is connected to the source of MOSFET M6 (number 6). The drain of MOSFET M6 is grounded. A delay channel MOSFET group 7 comprises MOSFET M7 (number 7) and MOSFET M8 (number 8). The source of MOSFET M7 is connected to the drain of input MOSFET M3 (number 3) and the drain of input MOSFET M4 (number 4). The drain of MOSFET M7 is connected to the source of MOSFET M8 (number 8). The drain of MOSFET M8 is grounded.

[0054] Adding MOSFET M5 (number 5) to divide the voltage of MOSFET M6 (number 6), and adding MOSFET M7 (number 7) to divide the voltage of MOSFET M8 (number 8), gives the Imain and Delay circuits better withstand voltage. It also suppresses the channel length modulation effect of MOSFETs M6 (number 6) and M8 (number 8), thereby improving the accuracy of the current in the circuit.

[0055] The other parts of this embodiment are the same as any one of embodiments 1-3, so they will not be described again.

[0056] Example 5:

[0057] A 10Gbps rate gain pre-emphasis circuit, improved based on any one of embodiments 1-4, such as... Figure 2 As shown, the threshold voltages of input MOSFETs M1, M2, M11, and M12 are less than or equal to 1V; the substrates of input MOSFETs M1, M2, M11, and M12 are connected to the source. Similarly, the threshold voltages of input MOSFETs M3, M4, M13, and M14 are also less than or equal to 1V; the substrates of input MOSFETs M3, M4, M13, and M14 are connected to the source.

[0058] Input MOSFETs M1, M2, M11, and M12 all use 1V DNW MOSFETs, which are smaller, have lower threshold voltages, and fewer parasitic parameters than 1.8V MOSFETs, enabling the pre-emphasis circuit to achieve a slew rate of 10Gbps. Furthermore, connecting the substrate and source terminals of these MOSFETs avoids the body effect that could cause a rise in threshold voltage, thus improving the slew rate of the pre-emphasis circuit.

[0059] Similarly, input MOSFETs M3 (number 3), M4 (number 4), M13 (number 3), and M14 (number 4) all use 1V DNW MOSFETs. Compared to 1.8V MOSFETs, these are smaller, have lower threshold voltages, and fewer parasitic parameters, enabling the pre-emphasis circuit to achieve a slew rate of 10Gbps. Furthermore, connecting the substrate and source of input MOSFETs M3, M4, M13, and M14 avoids the body effect that could cause a rise in threshold voltage, thus improving the slew rate of the pre-emphasis circuit.

[0060] The other parts of this embodiment are the same as any one of embodiments 1-4, so they will not be described again.

[0061] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. A 10Gbps rate gain pre-emphasis circuit, comprising an Imain circuit and a Delay circuit, characterized in that, The Imain circuit includes a first input transistor pair (1), and the Delay circuit includes a second input transistor pair (2). A first voltage divider pair (3) is provided on one side of the first input transistor pair (1), and a second voltage divider pair (4) is provided on one side of the second input transistor pair (2). The drain of the first voltage divider pair (3) is connected to the source of the first input transistor pair (1), and the drain of the second voltage divider pair (4) is connected to the source of the second input transistor pair (2). The sources of the first voltage divider pair (3) and the second voltage divider pair (4) are connected to an output resistor (5). The output terminal of the first input transistor pair (1) is connected to the Imain channel MOSFET group (6), and the output terminal of the second input transistor pair (2) is connected to the Delay channel MOSFET group (7).

2. The 10Gbps rate gain pre-emphasis circuit according to claim 1, characterized in that, The first input transistor pair (1) includes a first input MOSFET (M1) and a second input MOSFET (M2), and the first voltage divider transistor pair (3) includes a first voltage divider MOSFET (M11) and a second voltage divider MOSFET (M12). The source of the first voltage divider MOSFET (M11) is connected to the output resistor (5), and the drain of the first voltage divider MOSFET (M11) is connected to the source of the first input MOSFET (M1). The source of the second voltage divider MOSFET (M12) is connected to the output resistor (5), and the drain of the second voltage divider MOSFET (M12) is connected to the source of the second input MOSFET (M2). The drains of the first input MOSFET (M1) and the second input MOSFET (M2) are both connected to the Imain channel MOSFET pair (6).

3. The 10Gbps rate gain pre-emphasis circuit according to claim 2, characterized in that, The gates of the first voltage divider MOSFET (M11) and the second voltage divider MOSFET (M12) are both connected to the bias voltage circuit.

4. The 10Gbps rate gain pre-emphasis circuit according to claim 3, characterized in that, The Imain channel MOSFET group (6) includes MOSFET No. 5 (M5) and MOSFET No. 6 (M6). The source of MOSFET No. 5 (M5) is connected to the drain of input MOSFET No. 1 (M1) and the drain of input MOSFET No. 2 (M2). The drain of MOSFET No. 5 (M5) is connected to the source of MOSFET No. 6 (M6). The drain of MOSFET No. 6 (M6) is grounded.

5. A 10Gbps rate gain pre-emphasis circuit according to claim 4, characterized in that, The threshold voltages of the first input MOSFET (M1), the second input MOSFET (M2), the first voltage divider MOSFET (M11), and the second voltage divider MOSFET (M12) are less than or equal to 1V; the substrate and source of the first input MOSFET (M1), the second input MOSFET (M2), the first voltage divider MOSFET (M11), and the second voltage divider MOSFET (M12) are connected.

6. The 10Gbps rate gain pre-emphasis circuit according to claim 1, characterized in that, The second input transistor pair (2) includes a third input MOSFET (M3) and a fourth input MOSFET (M4), and the second voltage divider transistor pair (4) includes a third voltage divider MOSFET (M13) and a fourth voltage divider MOSFET (M14); the source of the third voltage divider MOSFET (M13) is connected to the output resistor (5), and the drain of the third voltage divider MOSFET (M13) is connected to the source of the third input MOSFET (M3); The source of the fourth voltage divider MOSFET (M14) is connected to the output resistor (5), the drain of the fourth voltage divider MOSFET (M14) is connected to the source of the fourth input MOSFET (M4), and the drains of the third input MOSFET (M3) and the fourth input MOSFET (M4) are both connected to the Delay channel MOSFET group (7).

7. A 10Gbps rate gain pre-emphasis circuit according to claim 6, characterized in that, The gates of the third voltage divider MOSFET (M13) and the fourth voltage divider MOSFET (M14) are both connected to the bias voltage circuit.

8. A 10Gbps rate gain pre-emphasis circuit according to claim 7, characterized in that, The Delay channel MOSFET group (7) includes MOSFET No. 7 (M7) and MOSFET No. 8 (M8). The source of MOSFET No. 7 (M7) is connected to the drain of input MOSFET No. 3 (M3) and the drain of input MOSFET No. 4 (M4). The drain of MOSFET No. 7 (M7) is connected to the source of MOSFET No. 8 (M8). The drain of MOSFET No. 8 (M8) is grounded.

9. A 10Gbps rate gain pre-emphasis circuit according to claim 8, characterized in that, The threshold voltages of the input MOSFETs M3, M4, M13, and M14 are less than or equal to 1V; the substrates of the input MOSFETs M3, M4, M13, and M14 are connected to the source.

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