Semiconductor process platform

Abstract

The utility model provides a semiconductor process platform, comprising a front end module located in an atmospheric environment; a first-stage vacuum transmission cavity and a second-stage vacuum transmission cavity, wherein the first-stage vacuum transmission cavity is connected between the second-stage vacuum transmission cavity and the front-end module; the side wall of each of the first-stage vacuum transmission cavity and the second-stage vacuum transmission cavity comprises a plurality of interfaces, the interfaces can be connected with the reaction cavity, and the number of the interfaces of the second-stage vacuum transmission cavity is greater than or equal to 8; and the two transmission cavity vacuumizing devices are respectively connected with the first-stage vacuum transmission cavity and the second-stage vacuum transmission cavity. The semiconductor process platform has the advantages that the occupied area is small, the types of processes which can be carried out by the semiconductor process platform are increased, a plurality of reaction cavities can be configured for long-time processes, and the substrate processing efficiency is improved. And the second-stage vacuum transmission cavity can achieve a higher vacuum degree on the basis of the first-stage vacuum transmission cavity, so that the substrate processing quality is improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor equipment technology, and in particular to a semiconductor process platform. Background Technology

[0002] Semiconductor platforms are indispensable key equipment in the semiconductor manufacturing process. They are responsible for performing various processing steps on the substrate to produce high-performance semiconductor chips. Existing platforms are typically equipped with a fixed number of reaction chambers of a single specification. The platform can only process one substrate at a time. If a reaction chamber in a certain processing step fails, the entire platform needs to be shut down for maintenance or the equipment needs to be replaced, which not only affects substrate processing efficiency but also increases equipment maintenance costs.

[0003] As technology nodes evolve towards smaller sizes, platforms typically require more reaction chambers, each with varying sizes, process types, and processing times. Existing platforms cannot meet the requirements for versatility. Taking copper seed layer deposition as an example, various reaction chambers are needed, including but not limited to: pretreatment chambers, chemical vapor deposition (CVD) self-assembled layer chambers, atomic layer deposition (ALD) tantalum nitride chambers, physical vapor deposition (PVD) tantalum nitride chambers, CVD cobalt chambers, CVD ruthenium chambers, and PVD copper chambers. These reaction chambers usually need to operate in a high-vacuum environment to ensure process accuracy and chip quality.

[0004] The platform also includes transport cavities to facilitate substrate transfer between the reaction cavities. To improve the final chip performance, these transport cavities also require a high vacuum. For example, the metal on the substrate surface is highly susceptible to oxidation by oxygen in the air, which alters various metal electrode properties, including resistance, film thickness, and defects. A high-vacuum transport cavity prevents oxygen leakage into the platform, thereby improving the final semiconductor chip performance.

[0005] When the platform is equipped with multiple reaction chambers, it not only occupies a large area, but the robotic arm inside the transfer chamber also needs to move back and forth on the slide rail. This not only results in low transfer efficiency, but the vibration generated by the robotic arm's movement can also easily cause deposits on the robotic arm's surface to fall off, contaminating the transfer chamber and thus reducing the substrate yield.

[0006] How to improve the fault tolerance, substrate processing efficiency, and substrate processing quality of the platform in complex processes while minimizing the footprint is an urgent problem to be solved. Utility Model Content

[0007] The purpose of this invention is to provide a semiconductor process platform, including a first-stage vacuum transfer cavity and a second-stage vacuum transfer cavity. The second-stage vacuum transfer cavity can connect to at least seven reaction chambers, significantly increasing the types of processes that the semiconductor process platform can perform. Due to the large number of reaction chambers, the semiconductor process platform of this invention can also be configured with redundant reaction chambers, preventing the entire semiconductor process platform from being affected by the long processing time of some processes or the downtime of some reaction chambers, thus greatly improving substrate processing efficiency. Furthermore, the second-stage vacuum transfer cavity can achieve a higher vacuum level than the first-stage vacuum transfer cavity, which helps to improve substrate processing quality.

[0008] To achieve the above objectives, this utility model provides a semiconductor process platform, comprising:

[0009] The front-end module exists in an atmospheric environment;

[0010] A first-stage vacuum transmission cavity and a second-stage vacuum transmission cavity are connected and disposed between the second-stage vacuum transmission cavity and the front-end module; the sidewalls of both the first-stage and second-stage vacuum transmission cavities include multiple interfaces, which can be connected to the reaction chamber; the second-stage vacuum transmission cavity has a greater than or equal to 8 interfaces.

[0011] Two vacuum pumping devices for the transmission chambers are respectively connected to the first-stage vacuum transmission chamber and the second-stage vacuum transmission chamber.

[0012] Optionally, the number of interfaces in the second-stage vacuum transmission cavity is 10.

[0013] Optionally, the number of interfaces in the second-stage vacuum transmission cavity is greater than the number of interfaces in the first-stage vacuum transmission cavity.

[0014] Optionally, the interface includes a first interface connected to the reaction chamber; the cross-section of the outer wall of the first-stage vacuum transmission chamber and the second-stage vacuum transmission chamber each includes multiple sides, each side corresponding to one of the first interfaces.

[0015] Optionally, the reaction chamber includes a physical vapor deposition chamber, and at least one of the first interfaces of the second-stage vacuum transfer chamber is connected to the physical vapor deposition chamber.

[0016] Optionally, the physical vapor deposition chamber is used to deposit thin films containing metal elements.

[0017] Optionally, the metallic element is copper.

[0018] Optionally, the same process may be performed in at least two reaction chambers.

[0019] Optionally, the vacuum pumping device for the transfer chamber includes a molecular pump and a cryogenic condensation pump.

[0020] Optionally, the vacuum level of the first-stage vacuum transmission cavity is 10. -7 Torr to 10 -8 Torr, the vacuum level of the second-stage vacuum transmission cavity is 10. -8 Torr to 10 -9 Torr.

[0021] Optionally, the center of the first-stage vacuum transmission cavity is the center of a circle, and the radius from the farthest end of the reaction cavity is the radius of the circle, wherein the radius of the circle is in the range of 1200mm to 1800mm.

[0022] Optionally, the center of the second-stage vacuum transmission cavity is a circle with a radius extending from the farthest point of the reaction cavity, and the radius of the circle is in the range of 2000mm to 2500mm.

[0023] Optionally, the reaction chamber includes a pretreatment chamber, which is disposed between the front-end module and the first-stage vacuum transmission chamber.

[0024] Optionally, the semiconductor process platform further includes: a buffer chamber and a buffer chamber vacuum device;

[0025] The buffer cavities are respectively connected and disposed between the front-end module and the first-stage vacuum transmission cavity, and between the first-stage vacuum transmission cavity and the second-stage vacuum transmission cavity;

[0026] The vacuum pumping device for the buffer chambers is connected to the plurality of buffer chambers respectively.

[0027] Optionally, the interface includes a second interface for connecting to the buffer cavity; the second interface is larger than the first interface, or the second interface is the same size as the first interface.

[0028] Optionally, the interior of the buffer cavity is divided into multiple partitions, and each partition contains a substrate carrier disk;

[0029] The first-stage vacuum transfer cavity, the second-stage vacuum transfer cavity, and the front-end module are all equipped with robotic arms; the robotic arms transfer the substrate into and out of the buffer cavity through the first transfer path and the second transfer path above the substrate support plate; the first transfer path and the second transfer path are located at different heights.

[0030] Optionally, the interior of the buffer cavity is divided into multiple layers in the vertical direction, and each layer includes multiple partitions.

[0031] Optionally, the substrate carrier disk has cooling fluid channels inside.

[0032] Optionally, the substrate carrier disk is provided with a heating element inside.

[0033] Optionally, the vacuum pump for the buffer chamber is a dry pump.

[0034] Compared with the prior art, the beneficial effects of this utility model include at least the following:

[0035] 1) The semiconductor process platform of this invention includes a first-stage vacuum transfer cavity and a second-stage vacuum transfer cavity. The second-stage vacuum transfer cavity can connect to at least eight reaction chambers, increasing the types of processes that the semiconductor process platform can perform and allowing for the simultaneous processing of multiple substrates. Due to the large number of reaction chambers, the semiconductor process platform of this invention can also be configured with redundant reaction chambers to avoid affecting the entire semiconductor process platform's process flow due to the long processing time of some processes or the downtime of reaction chambers, thus greatly improving substrate processing efficiency. The second-stage vacuum transfer cavity can achieve a higher vacuum level than the first-stage vacuum transfer cavity, which helps to improve substrate processing quality.

[0036] 2) In both the first-stage and second-stage vacuum transfer cavities, the transfer path of the robot arm is simple, eliminating the need for a sliding rail for the robot arm to glide along. This avoids the vibrations generated during the robot arm's movement that could cause deposits on its surface to fall off, significantly reducing particulate contaminants and improving substrate yield.

[0037] 3) In this invention, a buffer cavity is provided between the first-stage vacuum transmission cavity and the second-stage vacuum transmission cavity, and between the first-stage vacuum transmission cavity and the front-end module. The buffer cavity can accommodate multiple substrates simultaneously, and the paths of the substrates entering and leaving the buffer cavity do not interfere with each other, greatly improving the transmission efficiency of the substrates. At the same time, the substrates can also be cooled or preheated in the buffer cavity, greatly reducing the time the substrates spend in the semiconductor process platform.

[0038] 4) The semiconductor process platform of this utility model has a reasonable layout and occupies a small area. Attached Figure Description

[0039] To more clearly illustrate the technical solution of this utility model, the accompanying drawings used in the description will be briefly introduced below. Obviously, the drawings in the following description are one embodiment of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:

[0040] Figure 1 A schematic diagram illustrating the steps involved in copper seed layer deposition;

[0041] Figure 2 This is a schematic diagram of the process platform of this utility model;

[0042] Figure 3This is a schematic diagram showing the connection between the second-stage vacuum transmission chamber and the reaction chamber in this invention.

[0043] Figure 4 This is a schematic diagram of the buffer cavity in this utility model. Detailed Implementation

[0044] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0045] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0046] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0047] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0048] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0049] Furthermore, in the description of this application, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0050] In logic chip manufacturing, the deposition of a copper seed layer is fundamental to the electroplating of copper in copper interconnect processes. The quality of the copper seed layer directly affects the uniformity and quality of the electroplated copper. The copper seed layer needs to be thin and uniform to ensure that the electroplated copper can uniformly fill the high aspect ratio structure.

[0051] As technology nodes become smaller, the number of process steps required to achieve high-performance copper seed layer deposition is also increasing. These process steps work together to ensure high-quality deposition of the copper seed layer, thereby positively impacting the overall performance of the chip.

[0052] Figure 1 The image shows a substrate W with a low-dielectric-constant dielectric layer A1 on its surface. The dielectric layer A1 can be made of silicon-oxygen-carbon (SiOC), used in the semiconductor industry to reduce interconnect resistance-capacitance (RC) delay in integrated circuits. Figure 1 As shown in Figure a, a trench A3 is formed on the surface of dielectric layer A1 for copper seed layer deposition, and the bottom of trench A3 is filled with metal A2 (e.g., copper, tungsten, etc.).

[0053] like Figure 1 As shown, the process steps required in a semiconductor process platform typically include the following operations:

[0054] Preclean:

[0055] Contaminants such as oxides and carbon on the surface of substrate W can damage its surface structure and affect semiconductor device characteristics, such as reducing lifespan and increasing leakage current. Pre-cleaning can remove these contaminants and maintain the original ordered structure of the substrate W surface. Pre-cleaning the substrate W before depositing the copper seed layer prepares it for subsequent selective deposition.

[0056] Deposition of barrier layers:

[0057] Copper atoms have high mobility in dielectric materials and silicon, easily diffusing into the dielectric material. This affects the minority carrier lifetime and junction leakage current of the device, causing circuit failure and reducing device reliability. Therefore, before depositing copper material, a barrier layer is usually deposited to prevent copper atoms from entering the dielectric layer A1 and protecting it from copper atom erosion. However, the resistivity of the barrier layer material is higher than that of copper. To ensure a good electrical connection between the bottom of trench A3 filled with metal A2 and the copper seed layer, a selective deposition method can be used to deposit the barrier layer only on the sidewalls of trench A3 (i.e., the surface of the dielectric material), instead of depositing it at the bottom of trench A3 (the top of metal A2). Figure 1 As shown in Figure (b), a self-assembled monolayer (SAM) A4 can be deposited at the bottom of trench A3 first.

[0058] Self-assembled monolayer A4 is an organic monolayer selectively formed on the surface of metallic A2, such as... Figure 1 As shown in Figure (b), the self-assembled monolayer A4 does not deposit on the sidewall of trench A3, but instead forms a protective film on the metal A2 at the bottom of trench A3 before the copper seed layer is deposited, to ensure that the subsequent barrier layer is deposited only on the surface of the dielectric material and not on the surface of the metal.

[0059] Next, as Figure 1 As shown in Figure (c), a first barrier layer A5 can be deposited. The first barrier layer A5 selectively grows only on the sidewalls of trench A3 and not on the self-assembled monolayer A4 at the bottom of trench A3. The first barrier layer A5 can be a TaN (tantalum nitride) layer, a Ru (ruthenium) layer, etc. The function of the first barrier layer A5 is to prevent copper atoms from entering the dielectric layer A1, protecting the dielectric layer A1 from copper atom erosion. The first barrier layer A5 can be deposited using at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0060] As technology nodes shrink, the selectively deposited first barrier layer A5 may exhibit discontinuities, thus necessitating the selective deposition of barrier layers made of multiple materials to adequately cover the sidewalls of trench A3. In some embodiments, such as Figure 1 As shown in Figure (d), a second barrier layer A6 can be deposited on the surface of the first barrier layer A5. The second barrier layer A6 can be at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0061] The second barrier layer A6 will not grow on the self-assembled monolayer A4. The second barrier layer A6 can be a TaN layer or a Ta (tantalum) layer.

[0062] After the growth of the barrier layer is completed, such as Figure 1 As shown in Figure (e), the self-assembled monolayer A4 is removed so that a subsequent copper seed layer can be deposited on the metal A2 at the bottom of trench A3. The self-assembled monolayer A4 can be removed by at least one of rapid thermal treatment, plasma treatment, or UV treatment.

[0063] To promote the nucleation and growth of subsequent copper seed layers, after removing the self-assembled monolayer A4, an adhesion layer (glue layer) A7 needs to be deposited on the sidewalls and bottom of trench A3 to further promote the growth of subsequent copper seed layers. For example... Figure 1 As shown in Figure (f), the adhesion layer A7 can be a Co (cobalt) layer, a Ru (ruthenium) layer, a mixture of the two, or a stacked structure. The adhesion layer A7 can be grown by PECVD (plasma-assisted chemical vapor deposition).

[0064] After that, as Figure 1 As shown in Figure (g), a copper seed layer A8 is deposited by PVD within trench A3. In some embodiments, such as... Figure 1 As shown in Figure (h), a copper reflow process is performed within the PVD cavity. The copper reflow process reduces the aspect ratio of trench A3, which helps to reduce defects generated during subsequent copper plating, such as sidewall voids and line-top voids.

[0065] After the copper seed layer A8 is deposited, the substrate W is removed from the semiconductor process platform for copper electroplating to fill the trench A3 with copper, forming a complete copper interconnect structure. During the electroplating process, the copper seed layer A8 acts as the cathode, and copper ions in the electroplating solution are reduced and deposited in the trench A3 under the action of an applied electric field.

[0066] The copper seed layer deposition process involves multiple steps, all of which must be completed within the same semiconductor process platform to ensure the quality of the copper seed layer. Existing semiconductor process platforms have a limited number of reaction chambers, making it difficult for most platforms to meet the requirements of copper seed layer deposition. Even the few platforms capable of copper seed layer deposition can only process substrate W on a single wafer. In current semiconductor processes, if a process takes too long or a reaction chamber fails, it will affect the entire process of the semiconductor platform.

[0067] This invention provides a semiconductor process platform that, through a rational layout, increases the number of reaction chambers while saving floor space. This increases the types of processes the platform can perform. The number of reaction chambers can be configured based on process duration, or redundant reaction chambers can be configured to prevent process interruptions caused by chamber downtime. This semiconductor process platform significantly improves substrate processing efficiency and achieves higher vacuum levels, contributing to improved substrate processing quality.

[0068] like Figure 2 As shown, this utility model provides a semiconductor process platform 1, comprising: an EFEMEquipment Front-End Module 10, a first-stage vacuum transmission cavity 20a, a second-stage vacuum transmission cavity 20b, multiple buffer cavities 40, and multiple reaction cavities 30.

[0069] The front-end module 10 is located in an atmospheric environment and includes multiple front-opening wafer transfer boxes 101 (FOUP) and an atmospheric transfer chamber 102. The first-stage vacuum transfer chamber 20a is connected between the second-stage vacuum transfer chamber 20b and the front-end module 10.

[0070] The sidewalls of both the first-stage vacuum transmission cavity 20a and the second-stage vacuum transmission cavity 20b include multiple interfaces. For example... Figure 2 As shown, the interface includes a first interface 60, which is used to connect to the reaction chamber 30. Vacuum valves 70 (e.g., ...) are provided between the first-stage vacuum transmission chamber 20a and the corresponding reaction chamber 30, and between the second-stage vacuum transmission chamber 20b and the corresponding reaction chamber 30. Figure 3 As shown, the first-stage vacuum transmission chamber 20a is selectively connected to the corresponding reaction chamber 30, and the second-stage vacuum transmission chamber 20b is selectively connected to the corresponding reaction chamber 30. The corresponding vacuum valve 70 is opened to expose the corresponding first interface 60 only when substrate transfer is performed between the first-stage vacuum transmission chamber 20a, the second-stage vacuum transmission chamber 20b, and the reaction chamber 30.

[0071] The reaction chamber 30 can be a pretreatment chamber, a chemical vapor deposition chamber, an atomic layer deposition chamber, a physical vapor deposition chamber, or a plasma-assisted chemical vapor deposition chamber, etc. The pretreatment chamber is typically connected to the first-stage vacuum transfer chamber 20a. The physical vapor deposition chamber occupies a larger area and requires a higher vacuum level, so it is typically connected to a second-stage vacuum transfer chamber 20b, which has a higher vacuum level. In one embodiment, the physical vapor deposition chamber is used to deposit a thin film containing a metal element, which may be copper.

[0072] In this embodiment, the first-stage vacuum transmission cavity 20a includes 4 to 8 first interfaces 60, meaning the first-stage vacuum transmission cavity 20a connects to 4 to 8 reaction chambers 30. To facilitate layout and reduce the footprint of the semiconductor process platform 1, the second-stage vacuum transmission cavity 20b has a greater number of first interfaces 60 than the first-stage vacuum transmission cavity 20a. In this embodiment, the second-stage vacuum transmission cavity 20b has a number of first interfaces 60 greater than or equal to 8, meaning the second-stage vacuum transmission cavity 20b connects to at least 8 reaction chambers 30. The semiconductor process platform 1 of this invention increases the number of reaction chambers 30, thus increasing the types of processes that the semiconductor process platform 1 can perform, and meeting the needs of complex process technologies (such as copper seed layer deposition).

[0073] The same or different processes can be performed in the reaction chamber 30. In one embodiment, the number of reaction chambers 30 in the semiconductor process platform 1 is 14. If six different processes need to be performed in the semiconductor process platform 1, and each process is configured with two reaction chambers 30, then at least two substrates can be processed in the semiconductor process platform 1 at the same time.

[0074] In one embodiment, at least two reaction chambers 30 may be configured for processes with longer processing times to improve substrate processing efficiency. In another embodiment, the semiconductor process platform 1 is also configured with redundant reaction chambers 30 to prevent the entire semiconductor process platform 1 from being affected by the failure of an individual reaction chamber 30. When maintaining the semiconductor process platform 1, only individual reaction chambers 30 need to be repaired, without having to stop the entire semiconductor process platform 1 from operating, greatly reducing the maintenance cost of the semiconductor process platform 1.

[0075] like Figure 2 As shown, in this embodiment, the cross-section of the outer walls of both the first-stage vacuum transfer cavity 20a and the second-stage vacuum transfer cavity 20b includes multiple sides, each corresponding to a first interface 60. Robotic arms 50b and 50c are respectively disposed within the first-stage vacuum transfer cavity 20a and the second-stage vacuum transfer cavity 20b. The robotic arms 50b and 50c pass through the corresponding first interfaces 60, enabling substrate transfer between the first-stage vacuum transfer cavity 20a and the reaction cavity 30, and between the second-stage vacuum transfer cavity 20b and the reaction cavity 30. Compared to traditional linear transfer cavities, the transfer paths of the robotic arms 50b and 50c are simpler, eliminating the need for sliding rails. This avoids vibrations during the sliding of the robotic arms 50b and 50c that could cause deposits on their surfaces to detach, significantly reducing particulate contaminants and improving substrate yield.

[0076] The first-stage vacuum transmission cavity 20a is a circle with its center at the center and its radius extending to the farthest point of the reaction cavity 30 (connected to the first-stage vacuum transmission cavity 20a). The radius of this circle ranges from 1200mm to 1800mm. The second-stage vacuum transmission cavity 20b is a circle with its center at the center and its radius extending to the farthest point of the reaction cavity 30 (connected to the second-stage vacuum transmission cavity 20b). The radius of this circle ranges from 2000mm to 2500mm. The semiconductor process platform 1 of this invention has a reasonable layout, minimizing the floor space required while increasing the number of reaction cavities 30.

[0077] Both the first-stage vacuum transmission chamber 20a and the second-stage vacuum transmission chamber 20b are equipped with a vacuum pumping device. For example... Figure 3 As shown, in this embodiment, the vacuum pumping device for the transfer chamber includes a molecular pump 201 and a cryogenic condensation pump 202. The molecular pump 201 reduces the vacuum level by transferring gas outside the pump, while the cryogenic condensation pump 202 reduces the vacuum level by adsorbing gas at low temperature. Since the gas adsorbed at low temperature is not discharged outside the pump, the cryogenic condensation pump 202 is suitable for use in situations with higher vacuum levels and is typically configured to be used after the molecular pump 201 is started.

[0078] In this embodiment, the vacuum level of the first-stage vacuum transmission cavity 20a is 10. -7Torr to 10 -8 Torr, the vacuum level of the second-stage vacuum transmission cavity 20b is 10. -8 Torr to 10 -9 Torr. The second-stage vacuum transfer cavity 20b can achieve a higher vacuum level based on the first-stage vacuum transfer cavity 20a, which can prevent the metal electrodes on the substrate surface from being oxidized by residual oxygen in the cavity, and greatly improve the substrate processing quality.

[0079] like Figure 2 As shown, multiple buffer chambers 40 are respectively connected and disposed between the front-end module 10 and the first-stage vacuum transmission chamber 20a, and between the first-stage vacuum transmission chamber 20a and the second-stage vacuum transmission chamber 20b. The interface includes a second interface 80, which is used to connect the buffer chambers 40. Each buffer chamber 40 is equipped with a buffer chamber vacuum pumping device, such as... Figure 4 As shown, the buffer chamber vacuum device in this embodiment is a dry pump 46.

[0080] like Figure 2 As shown, in this embodiment, a buffer chamber 40a is provided between the front-end module 10 and the first-stage vacuum transfer chamber 20a. This buffer chamber 40a serves as an airlock chamber for wafer transfer. To maintain the reaction chamber 30, the first-stage vacuum transfer chamber 20a, and the second-stage vacuum transfer chamber 20b in a stable vacuum state, the airlock chamber 30 performs pressure conversion between vacuum and atmospheric pressure to prevent the substrate from being damaged by suddenly entering an atmospheric pressure environment from a vacuum environment. Vacuum valves (not shown in the figure) between the airlock chamber and the atmospheric transfer chamber 102, and between the airlock chamber and the first-stage vacuum transfer chamber 20a, allow the airlock chamber to selectively connect the atmospheric transfer chamber 102 and the first-stage vacuum transfer chamber 20a. The robotic arm 50a inside the atmospheric transfer chamber 102 can slide on the track 1021 to realize the transfer of the substrate between the front-opening wafer transfer box 101 and the airlock chamber.

[0081] like Figure 2 As shown, in this embodiment, two buffer cavities 40b and 40c are provided between the first-stage vacuum transmission cavity 20a and the second-stage vacuum transmission cavity 20b.

[0082] Vacuum valves are provided between the first-stage vacuum transmission chamber 20a and the buffer chambers 40a, 40b, and 40c, and between the second-stage vacuum transmission chamber 20b and the buffer chambers 40b and 40c. Figure 2 (Not shown in the diagram), the buffer chambers 40a, 40b, and 40c are selectively connected to the first-stage vacuum transmission chamber 20a and the second-stage vacuum transmission chamber 20b via vacuum valves. The corresponding vacuum valve is only opened to expose the corresponding second interface 80 when substrate transfer is performed between the first-stage vacuum transmission chamber 20a, the second-stage vacuum transmission chamber 20b, and the buffer chamber 40.

[0083] In some embodiments, buffer cavities 40b and 40c may share a second interface 80, which is larger than the first interface 60. The second interface 80 connected to buffer cavity 40a is the same size as the first interface 60. In other embodiments, such as Figure 2 The buffer cavity can be individually connected to the corresponding second interface 80.

[0084] like Figure 2 As shown, in this embodiment, reaction chambers 30a and 30b serve as pretreatment chambers. A robotic arm 50a transfers the substrate from the front-end module 10 to the gaslock chamber. Then, the robotic arm 50b transfers the substrate from the gaslock chamber to the reaction chamber 30, which is connected to the first-stage vacuum transfer chamber 20a. After the corresponding processes are completed in the reaction chamber 30, the robotic arm 50b transfers the substrate to buffer chambers 40b and 40c. Next, the robotic arm 50c transfers the substrate from the buffer chambers 40b and 40c to the reaction chamber 30, which is connected to the second-stage vacuum transfer chamber 20b. After all process steps are completed, the substrate is sequentially transferred to the front-end module 10 via the second-stage vacuum transfer chamber 20b, buffer chamber 40, first-stage vacuum transfer chamber 20a, and gaslock chamber.

[0085] like Figure 4 As shown, the interior of the buffer cavity 40 is vertically divided into multiple layers, each layer further divided into multiple partitions 43, and each partition 43 contains a substrate carrier disk 46. In this embodiment, the buffer cavity 40 is internally divided into two layers, each layer divided into two partitions 43. Robots 50a, 50b, and 50c transfer substrates into and out of the buffer cavity 40 via a first transfer path 41 and a second transfer path 42 above the substrate carrier disk 46. The first transfer path 41 and the second transfer path 42 are located at different heights. The buffer cavity 40 of this invention can simultaneously accommodate multiple substrates, and the paths for substrates entering and leaving the buffer cavity 40 do not interfere with each other, greatly improving the substrate transfer efficiency.

[0086] In one embodiment, such as Figure 4 As shown, the substrate carrier disk 46 has a cooling fluid channel 452 inside, which can cool the substrate within the buffer cavity 40. In another embodiment, as... Figure 4 As shown, the substrate carrier disk 46 is also equipped with a heating element 451, which can preheat the substrate within the buffer cavity 40. This saves the time required for the substrate to cool or preheat within the reaction cavity 30, further improving the working efficiency of the semiconductor process platform 1.

[0087] The aforementioned semiconductor process platform can also be applied to other processes that require multiple reaction steps, such as tungsten metal interconnect processes and cobalt metal interconnect processes.

[0088] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0089] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A semiconductor process platform, characterized in that, Include: The front-end module exists in an atmospheric environment; A first-stage vacuum transmission cavity and a second-stage vacuum transmission cavity are connected and disposed between the second-stage vacuum transmission cavity and the front-end module; the sidewalls of both the first-stage and second-stage vacuum transmission cavities include multiple interfaces, which can be connected to the reaction chamber; the second-stage vacuum transmission cavity has a greater than or equal to 8 interfaces. Two vacuum pumping devices for the transmission chambers are respectively connected to the first-stage vacuum transmission chamber and the second-stage vacuum transmission chamber.

2. The semiconductor process platform as described in claim 1, characterized in that, The second-stage vacuum transmission cavity has 10 interfaces.

3. The semiconductor process platform as described in claim 1, characterized in that, The number of interfaces in the second-stage vacuum transmission cavity is greater than the number of interfaces in the first-stage vacuum transmission cavity.

4. The semiconductor process platform as described in claim 1, characterized in that, The interface includes a first interface, which is connected to the reaction chamber; the cross-section of the outer wall of the first-stage vacuum transmission chamber and the second-stage vacuum transmission chamber each includes multiple sides, each side corresponding to one of the first interfaces.

5. The semiconductor process platform as described in claim 4, characterized in that, The reaction chamber includes a physical vapor deposition chamber, and at least one of the first interfaces of the second-stage vacuum transport chamber is connected to the physical vapor deposition chamber.

6. The semiconductor process platform as described in claim 5, characterized in that, The physical vapor deposition chamber is used to deposit thin films containing metal elements.

7. The semiconductor process platform as described in claim 6, characterized in that, The metallic element is copper.

8. The semiconductor process platform as described in claim 1, characterized in that, The same process is performed in at least two reaction chambers.

9. The semiconductor process platform as described in claim 1, characterized in that, The vacuum pumping device for the transmission chamber includes a molecular pump and a cryogenic condensation pump.

10. The semiconductor process platform as described in claim 1, characterized in that, The vacuum level of the first-stage vacuum transmission cavity is 10. -7 Torr to 10 -8 Torr, the vacuum level of the second-stage vacuum transmission cavity is 10. -8 Torr to 10 -9 Torr.

11. The semiconductor process platform as described in claim 1, characterized in that, The center of the first-stage vacuum transmission cavity is the center of the circle, and the radius from the farthest end of the reaction cavity is the radius of the circle, which ranges from 1200mm to 1800mm.

12. The semiconductor process platform as described in claim 1, characterized in that, The center of the second-stage vacuum transmission cavity is the center of the circle, and the radius from the farthest end of the reaction cavity is the radius of the circle, which ranges from 2000mm to 2500mm.

13. The semiconductor process platform as described in claim 1, characterized in that, The reaction chamber includes a pretreatment chamber, which is disposed between the front-end module and the first-stage vacuum transmission chamber.

14. The semiconductor process platform as described in claim 4, characterized in that, Also includes: Buffer chamber and buffer chamber vacuum device; The buffer cavities are respectively connected and disposed between the front-end module and the first-stage vacuum transmission cavity, and between the first-stage vacuum transmission cavity and the second-stage vacuum transmission cavity; The vacuum pumping device for the buffer chambers is connected to the plurality of buffer chambers respectively.

15. The semiconductor process platform as described in claim 14, characterized in that, The interface includes a second interface for connecting to the buffer cavity; the second interface is larger than the first interface, or the second interface is the same size as the first interface.

16. The semiconductor process platform as described in claim 14, characterized in that, The interior of the buffer cavity is divided into multiple partitions, and each partition contains a substrate carrier disk. The first-stage vacuum transfer cavity, the second-stage vacuum transfer cavity, and the front-end module are all equipped with robotic arms; the robotic arms transfer the substrate into and out of the buffer cavity through the first transfer path and the second transfer path above the substrate support plate; the first transfer path and the second transfer path are located at different heights.

17. The semiconductor process platform as described in claim 16, characterized in that, The interior of the buffer cavity is divided into multiple layers in the vertical direction, and each layer includes multiple partitions.

18. The semiconductor process platform as described in claim 16, characterized in that, The substrate carrier disk has cooling fluid channels inside.

19. The semiconductor process platform as described in claim 16, characterized in that, The substrate support disk is equipped with a heating element inside.

20. The semiconductor process platform as described in claim 14, characterized in that, The vacuum pump for the buffer chamber is a dry pump.

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