Protection circuit, digital input receiver circuit, and digital input receiver chip
By designing control and current limiting modules in the digital input receiver, the problem of excessive discharge current caused by short circuit of external resistors is solved, reducing the risk of chip burnout and optimizing power consumption, thus achieving safer and more efficient circuit operation.
Patent Information
- Application Number
- CN202423107347.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2034-12-16
AI Technical Summary
Existing digital input receivers have excessive discharge current when the external resistor is short-circuited, which poses a high risk of chip burnout and increases power consumption.
A protection circuit was designed, including a control module, a protection module, and a current limiting module. By comparing the on-chip operating current with the input current, a protection start signal is output to discharge part of the input current, and the maximum discharge current is limited by the current limiting module to avoid excessive current.
This reduces the risk of chip burnout and lowers circuit power consumption when current discharge is not required, thereby improving circuit safety and energy efficiency.
Smart Images
Figure CN223666036U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a protection circuit, a digital input receiver circuit and a digital input receiver chip. BACKGROUND
[0002] Digital input receivers are widely used in industrial controllers, however, the digital input receivers in the prior art do not consider fault protection, when an off-chip resistor is short-circuited, the discharge current in the chip is very large, possibly tens or even hundreds of milliampere (mA) levels, which can cause a high risk of burning the chip. CONTENT OF THE INVENTION
[0003] The protection circuit, the digital input receiver circuit and the digital input receiver chip provided by the embodiments of the present disclosure can reduce the risk of burning the chip caused by excessive discharge current, and can also reduce the energy consumption of the circuit.
[0004] In a first aspect, the present disclosure provides a protection circuit, comprising a current input end, a field ground end, a sensing end, a control module, a protection module and a current limiting module, a first input end of the control module is connected to the current input end, a second input end of the control module is connected to the sensing end, an output end of the control module is connected to a control end of the protection module, an input end of the protection module is connected to the current input end, and an output end of the protection module is connected to the field ground end through the current limiting module.
[0005] The control module is configured to compare an operating current in the chip with an input current of the current input end, and output a protection opening signal when the operating current is less than the input current. The protection module is configured to turn on the current input end and the field ground end according to the protection opening signal to discharge part of the input current. The current limiting module is configured to limit the maximum discharge current of the protection module to be less than or equal to a threshold current.
[0006] In some embodiments of the present disclosure, the current limiting module comprises a first transistor, a second transistor and a reference current source, an output end of the reference current source is connected to a control end of the first transistor, a second end of the first transistor and a control end of the second transistor, a first end of the first transistor and a first end of the second transistor are connected to the field ground end, and a second end of the second transistor is connected to the output end of the protection module.
[0007] In some embodiments of the present disclosure, the protection module comprises a third transistor, a control end of the third transistor is connected to the output end of the control module, a first end of the third transistor is connected to the current input end, and a second end of the third transistor is connected to the field ground end through the current limiting module.
[0008] In some embodiments of the present disclosure, the current limiting module further comprises a clamping unit, a first end of the clamping unit being connected to the current input end, and a second end of the clamping unit being connected to the control end of the protection module.
[0009] The clamping unit is configured to limit the maximum control voltage of the protection module to limit the maximum discharge current.
[0010] In some embodiments of the present disclosure, the clamping unit comprises a single diode-connected clamping transistor connected between the current input end and the control end of the protection module, or the clamping unit comprises a plurality of diode-connected clamping transistors connected in series between the current input end and the control end of the protection module.
[0011] In some embodiments of the present disclosure, the control module comprises a resistor, a fourth transistor, a fifth transistor, a first reference current source and a second reference current source, a first end of the fourth transistor being connected to the current input end, a control end of the fourth transistor being connected to a second end of the fourth transistor and a control end of the fifth transistor, a first end of the fifth transistor being connected to a first end of the resistor, a second end of the fifth transistor being connected to the control end of the protection module, the second end of the fourth transistor being connected to the field ground end through the first reference current source, and the second end of the fifth transistor being connected to the field ground end through the second reference current source.
[0012] In some embodiments of the present disclosure, the protection circuit further comprises a sixth transistor, a seventh transistor and an eighth transistor, the second end of the fourth transistor being connected to the first reference current source through the sixth transistor, the second end of the fifth transistor being connected to the second reference current source through the seventh transistor, the second end of the third transistor being connected to the second end of the second transistor through the eighth transistor, a control end of the sixth transistor, a control end of the seventh transistor and a control end of the eighth transistor being connected to a bias voltage.
[0013] The withstand voltage values of the first transistor, the second transistor, the sixth transistor, the seventh transistor and the eighth transistor are less than a first preset voltage, the withstand voltage values of the third transistor, the fourth transistor and the fifth transistor are greater than a second preset voltage, and the second preset voltage is greater than the first preset voltage.
[0014] In some embodiments of the present disclosure, the protection circuit further comprises a ninth transistor connected between the field ground end and the output end of the current limiting module, and a control end of the ninth transistor being connected to a bias voltage.
[0015] In a second aspect, the present disclosure provides a digital input receiver circuit comprising any protection circuit provided in the first aspect.
[0016] In a third aspect, the present disclosure provides a digital input receiver chip comprising any protection circuit provided in the first aspect.
[0017] In the technical solution of the embodiments of the present disclosure, the protection circuit comprises a current input end, a field ground end, a sensing end, a control module, a protection module and a current limiting module, the first input end of the control module is connected to the current input end, the second input end of the control module is connected to the sensing end, the output end of the control module is connected to the control end of the protection module, the input end of the protection module is connected to the current input end, the output end of the protection module is connected to the field ground end through the current limiting module, the control module can compare the working current in the chip with the input current of the current input end, and output a protection opening signal when the working current is less than the input current, the protection module can turn on the current input end and the field ground end according to the protection opening signal to discharge part of the input current, and the current limiting module can limit the maximum discharge current of the protection module to be less than or equal to the threshold current, thereby reducing the risk of chip burnout caused by excessive discharge current, and in addition, the current limiting module does not generate additional power consumption when the discharge current is not needed, thereby reducing the energy consumption of the circuit. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0019] Figure 1 A circuit schematic diagram of a digital input receiver provided by the prior art.
[0020] Figure 2 A structure schematic diagram of a protection circuit provided by the embodiments of the present disclosure.
[0021] Figure 3 A circuit schematic diagram of a protection circuit provided by the embodiments of the present disclosure.
[0022] Figure 4 A circuit schematic diagram of another protection circuit provided by the embodiments of the present disclosure.
[0023] Figure 5 A circuit schematic diagram of another protection circuit provided by the embodiments of the present disclosure. DETAILED DESCRIPTION
[0024] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.
[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" together shall mean that the parts are joined directly or joined through one or more intermediate parts.
[0026] Reference to "an embodiment" or "the embodiment" in this disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" or "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiments, although they can be. It is explicitly contemplated that embodiments described with respect to one embodiment can be combined with features of another embodiment.
[0027] In addition, the terms "first", "second", and the like in the description and claims of this disclosure or the above drawings are used to distinguish different objects, and are not used to describe a particular order, and can explicitly or implicitly include one or more of the features.
[0028] The term "and / or" in the present disclosure is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the existence of A, the existence of A and B, and the existence of B. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.
[0029] In the description of the present disclosure, unless otherwise specified, the meaning of "a plurality of" and "at least two" is two or more (including two), and similarly, "a plurality of groups" and "at least two groups" means two groups or more (including two groups).
[0030] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings.
[0031] Figure 1 A circuit schematic diagram of a digital input receiver provided by the prior art is shown in Figure 1 The digital input receiver includes a sense terminal SENSE, a current input terminal IN, a field ground terminal FGND, a first field effect transistor MP0, a second field effect transistor MP1, a third field effect transistor MP2, a resistor R1, a first reference current source IB1, a second reference current source IB2, a Low Dropout Regulator (LDO), and a functional module.
[0032] The source of the first field effect transistor MP0, the source of the second field effect transistor MP1, and the input of the LDO are connected to the current input terminal IN, the source of the third field effect transistor MP2 is connected to the sense terminal SENSE through the resistor R1, the gate of the second field effect transistor MP1 is connected to the gate of the third field effect transistor MP2, the drain of the second field effect transistor MP1, and the input of the first reference current source IB1.
[0033] The drain of the third field effect transistor MP2 is connected to the input of the second reference current source IB2 and the gate of the first field effect transistor MP0, the drain of the first field effect transistor MP0, the output of the first reference current source IB1, and the output of the second reference current source IB2 are connected to the field ground terminal FGND, the output of the LDO is connected to the field ground terminal FGND through the functional module, and an off-chip resistor R0 is connected between the sense terminal SENSE and the current input terminal IN.
[0034] As shown in Figure 1 When the off-chip resistor R0 is short-circuited, for example, the resistance of the off-chip resistor R0 is small, or the sense terminal SENSE and the current input terminal IN are short-circuited, the current flowing through the first field effect transistor MP0 in the chip is very large, which may be tens or even hundreds of mA, which greatly increases the risk of chip burnout.
[0035] Therefore, the present disclosure provides a protection circuit, which includes a current input terminal, a field ground terminal, a sense terminal, a control module, a protection module, and a current limiting module. The first input terminal of the control module is connected to the current input terminal, the second input terminal of the control module is connected to the sense terminal, the output terminal of the control module is connected to the control terminal of the protection module, the input terminal of the protection module is connected to the current input terminal, and the output terminal of the protection module is connected to the field ground terminal through the current limiting module. The control module can compare the working current in the chip with the input current of the current input terminal, and output a protection enable signal when the working current is less than the input current. The protection module can conduct the current input terminal and the field ground terminal according to the protection enable signal to discharge part of the input current. The current limiting module can limit the maximum discharge current of the protection module to be less than or equal to a threshold current, which can reduce the risk of chip burnout caused by excessive discharge current. In addition, the current limiting module does not generate additional power consumption when the discharge current is not needed, which can reduce the energy consumption of the circuit.
[0036] The technical solutions provided by the present disclosure are described in detail below with several specific embodiments.
[0037] Figure 2 A structural schematic diagram of a protection circuit provided by an embodiment of the present disclosure is shown in FIG. 1. Figure 2 The protection circuit 100 includes a current input end IN, a field ground end FGND, a sensing end SENSE, a control module 110, a protection module 120, and a current limiting module 130.
[0038] The current input end IN and the sensing end SENSE are connected with an off-chip resistor R0, the first input end of the control module 110 is connected with the current input end IN, the second input end of the control module 110 is connected with the sensing end SENSE, the output end of the control module 110 is connected with the control end of the protection module 120, the input end of the protection module 120 is connected with the current input end IN, and the output end of the protection module 120 is connected with the field ground end FGND through the current limiting module 130.
[0039] The control module 110 is configured to compare the working current Iwork in the chip with the input current Iin of the current input end, and output a protection opening signal when the working current Iwork is less than the input current Iin. The protection module 120 is configured to turn on the current input end IN and the field ground end FGND according to the protection opening signal, so as to discharge part of the input current Iin. The current limiting module 130 is configured to limit the maximum discharge current of the protection module 120 to be less than or equal to a threshold current Ith.
[0040] For example, the voltage of the current input end IN is an input voltage Vin, the voltage of the sensing end SENSE is a sensing voltage Vsense, the current flowing through the off-chip resistor R0 is the input current Iin, and Iin=(Vsense-Vin) / R', where R' is the resistance of the off-chip resistor R0. The input current Iin flows into the chip through the current input end IN, and provides the working current Iwork in the chip for the subsequent circuit in the chip, and Iin=Iwork+Idisc, where Idisc is the discharge current of the protection module 120, and the subsequent circuit in the chip can include an LDO and a functional module, etc.
[0041] Figure 3 A circuit schematic diagram of a protection circuit provided by an embodiment of the present disclosure is shown in FIG. 2. Figure 3As shown, the control module 110 includes a resistor R1, a fourth transistor M4, a fifth transistor M5, a first reference current source IB1, and a second reference current source IB2. The first terminal of the fourth transistor M4 is connected to the current input terminal IN. The control terminal of the fourth transistor M4 is connected to the second terminal of the fourth transistor M4 and the control terminal of the fifth transistor M5. The second terminal of the fifth transistor M5 is connected to the first terminal of the resistor R1. The second terminal of the resistor R1 is connected to the sensing terminal SENSE. The second terminal of the fifth transistor M5 is connected to the control terminal of the protection module 120. The second terminal of the fourth transistor M4 is connected to the field ground terminal FGND through the first reference current source IB1. The second terminal of the fifth transistor M5 is connected to the field ground terminal FGND through the second reference current source IB2.
[0042] For example, such as Figure 3 As shown, the fourth transistor M4 and the fifth transistor M5 are P-type metal-oxide-semiconductor field-effect transistors (PMOS). The source of the fourth transistor M4 is connected to the current input terminal IN, the gate of the fourth transistor M4 is connected to the drain of the fourth transistor M4, the gate of the fifth transistor M5 and the first reference current source IB1, the source of the fifth transistor M5 is connected to the resistor R1, and the drain of the fifth transistor M5 is connected to the second reference current source IB2 and the control terminal of the protection module 120.
[0043] The fourth transistor M4 and the fifth transistor M5 can form a current mirror. The ratio of the width-to-length ratio of the fourth transistor M4 to the fifth transistor M5 is k1. The first reference current source IB1 provides the first current I1, and the second reference current source IB2 provides the second current I2. Both the first current I1 and the second current I2 are zero-temperature-drift (ZTC) currents. The current flowing through the fourth transistor M4 is the first current I1, and the current flowing through the fifth transistor M5 is the second current I2. I1 is set to k1*I2 to ensure the balance on both sides of the current mirror and to generate a fixed voltage I2*R” across the resistor R1, where R” is the resistance value of the resistor R1.
[0044] The threshold current Ith can be set as the ratio of the resistance R” of resistor R1 to the resistance R’ of external resistor R0 when the chip is operating normally, multiplied by the second current I2 output by the second reference current source IB2, i.e., Ith = R” * I2 / R’. For example, the threshold current Ith can be a typical value such as 2mA, 6mA, or 10mA. The sensing voltage Vsense can be detected through the sensing terminal SENSE.
[0045] In the case of normal operation of the chip, when the working current Iwork in the chip is greater than or equal to the threshold current Ith, the input current Iin becomes larger, resulting in a larger voltage difference between the sensing end SENSE and the current input end IN, so that the input voltage Vin is less than the source voltage of the fifth transistor M5, and the fifth transistor M5 enters the linear region to work. At this time, the drain voltage of the fifth transistor M5 increases to output a high-level signal, i.e., a protection closing signal, to the protection module 120.
[0046] In the case of normal operation of the chip, when the working current Iwork in the chip is less than the threshold current Ith, the input voltage Vin is equal to the source voltage of the fifth transistor M5, and the fourth transistor M4 and the fifth transistor M5 both work in the saturation region. At this time, the drain voltage of the fifth transistor M5 is floating, and can output a low-level signal, i.e., a protection opening signal, to the protection module 120.
[0047] For example, continuing to refer to Figure 3 The protection module 120 includes a third transistor M3, the control end of the third transistor M3 is connected to the output end of the control module 110, the first end of the third transistor M3 is connected to the current input end IN, and the second end of the third transistor M3 is connected to the ground end FGND through the current limiting module 130.
[0048] Specifically, the third transistor M3 is a PMOS, the source of the third transistor M3 is connected to the current input end IN, the drain of the third transistor M3 is connected to the current limiting module 130, and the gate of the third transistor M3 is connected to the drain of the fifth transistor M5.
[0049] When the protection module 120 receives the protection closing signal, the gate voltage of the third transistor M3 is high, the third transistor M3 is in the cut-off state, and the input current Iin all flows into the subsequent circuit in the chip. When the protection module 120 receives the protection opening signal, the gate voltage of the third transistor M3 is low, the third transistor M3 is in the on state, and part of the input current Iin can be discharged, wherein the discharge current Idisc of the third transistor M3 is Iin-Iwork.
[0050] Under normal circumstances, the discharge current Idisc of the protection module 120 is less than the threshold current Ith, for example, the discharge current Idisc does not exceed 6mA, however, when the external resistance R0 is short-circuited, the chip does not work normally, the input current Iin is very large, and the discharge current Idisc of the protection module 120 is very large, which may burn the chip, so in the embodiment of the present disclosure, a current limiting module 130 is connected to the output end of the protection module 120 to limit the maximum discharge current of the protection module 120.
[0051] For example, continuing to refer to Figure 3The current limiting module 130 includes a first transistor M1, a second transistor M2, and a reference current source IB0. An output terminal of the reference current source IB0 is connected to a control terminal of the first transistor M1, a second terminal of the first transistor M1, and a control terminal of the second transistor M2. A first terminal of the first transistor M1 and a first terminal of the second transistor M2 are connected to a field ground terminal FGND. A second terminal of the second transistor M2 is connected to an output terminal of the protection module 120.
[0052] Specifically, the first transistor M1 and the second transistor M2 are NMOS. A source of the first transistor M1 and a source of the second transistor M2 are connected to the field ground terminal FGND. A gate of the first transistor M1 is connected to a drain of the first transistor M1, an output terminal of the reference current source IB0, and a gate of the second transistor M2. A drain of the second transistor M2 is connected to a drain of a third transistor M3.
[0053] The first transistor M1 and the second transistor M2 constitute a current mirror. A ratio of a width-length ratio of the second transistor M2 to a width-length ratio of the first transistor M1 is k2. The reference current source IB0 provides a reference current Ibias. The second transistor M2 can mirror the reference current Ibias and output a mirror current Ibias*k2 of the reference current Ibias. Therefore, a maximum current flowing through the second transistor M2 is the mirror current Ibias*k2. In turn, a maximum discharge current of the protection module 120 is limited to Ibias*k2, where Ibias*k2≤Ith.
[0054] In this way, by connecting the current limiting module 130 between the output terminal of the protection module 120 and the field ground terminal FGND, the maximum discharge current of the protection module 120 can be limited to be less than or equal to the threshold current Ith. The risk of chip burnout caused by excessive discharge current can be reduced. In addition, when the discharge current is not needed, the current limiting module 130 does not generate additional power consumption, which can reduce the energy consumption of the circuit.
[0055] In some embodiments, Figure 4 Another circuit schematic diagram of a protection circuit provided by the embodiments of the present disclosure is shown in FIG. 2. As shown in FIG. 2, the current limiting module 130 further includes a clamping unit 131. A first terminal of the clamping unit 131 is connected to the current input terminal IN. A second terminal of the clamping unit 131 is connected to the control terminal of the protection module 120. Figure 4 As shown in FIG. 2, the clamping unit 131 includes a clamping transistor Mclp in a single-diode connection. The clamping transistor Mclp is connected between the current input terminal IN and the control terminal of the protection module 120.
[0056] Figure 4
[0057] Specifically, the clamping transistor Mclp is a PMOS, the source of the clamping transistor Mclp is connected to the current input end IN, and the gate of the clamping transistor Mclp is connected to the drain of the clamping transistor Mclp and the gate of the third transistor M3.
[0058] When the discharge current Idisc of the protection module 120 is greater than the threshold current Ith, the clamping transistor Mclp is turned on to limit the gate-source voltage of the third transistor M3, and the gate-source voltage of the third transistor M3 determines the size of the current flowing through the third transistor M3, that is, the maximum discharge current can be limited. Since the source voltage of the third transistor M3 is the input voltage Vin, the clamping transistor Mclp can limit the gate voltage of the third transistor M3, that is, limit the maximum control voltage of the protection module 120.
[0059] In other embodiments, the clamping unit 131 includes a plurality of diode-connected clamping transistors Mclp, all of which are connected in series between the current input end IN and the control end of the protection module 120, as shown in Figure 5 Figure 5 Another circuit schematic diagram of a protection circuit provided by an embodiment of the present disclosure is provided.
[0060] For example, as shown in Figure 5 The clamping unit 131 includes two diode-connected clamping transistors, respectively denoted as a first clamping transistor Mclp1 and a second clamping transistor Mclp2, and the first clamping transistor Mclp1 and the second clamping transistor Mclp2 are connected in series between the current input end IN and the control end of the protection module 120.
[0061] Specifically, the first clamping transistor Mclp1 and the second clamping transistor Mclp2 are PMOS, the source of the first clamping transistor Mclp1 is connected to the current input end IN, the gate of the first clamping transistor Mclp1 is connected to the drain of the first clamping transistor Mclp1 and the source of the second clamping transistor Mclp2, and the gate of the second clamping transistor Mclp2 is connected to the drain of the second clamping transistor Mclp2 and the gate of the third transistor M3.
[0062] When the discharge current Idisc of the protection module 120 is greater than the threshold current Ith, the first clamping transistor Mclp1 and the second clamping transistor Mclp2 are both turned on to limit the gate-source voltage of the third transistor M3, thereby limiting the gate voltage of the third transistor M3, that is, limiting the maximum control voltage of the protection module 120.
[0063] It should be noted that, Figure 5 The clamping unit 131 only exemplarily includes two clamping transistors in diode connection, and in actual applications, the clamping unit 131 can also include three or more clamping transistors in diode connection, and all the clamping transistors are connected in series between the current input end IN and the control end of the protection module 120, and the number of the clamping transistors is not specifically limited in the present disclosure.
[0064] In this way, the clamping unit 131 can limit the maximum control voltage of the protection module 120 to limit the maximum discharge current of the protection module 120, and the maximum discharge current can be further limited, thereby further reducing the risk of chip burnout caused by excessively large discharge current.
[0065] In some embodiments, continuing to refer to Figure 4 and Figure 5 , the protection circuit 100 further includes a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8, the second end of the fourth transistor M4 is connected to the first reference current source IB1 through the sixth transistor M6, the second end of the fifth transistor M5 is connected to the second reference current source IB2 through the seventh transistor M7, the second end of the third transistor M3 is connected to the second end of the second transistor M2 through the eighth transistor M8, and the control end of the sixth transistor M6, the control end of the seventh transistor M7 and the control end of the eighth transistor M8 are connected to the bias voltage V0.
[0066] In the formula, the withstand voltage values of the first transistor M1, the second transistor M2, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are less than the first preset voltage, the withstand voltage values of the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are greater than the second preset voltage, and the second preset voltage is greater than the first preset voltage. It can be understood that the first transistor M1, the second transistor M2, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are low-voltage tubes, and the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are high-voltage tubes.
[0067] For example, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are NMOS, the source of the sixth transistor M6 is connected to the first reference current source IB1, the source of the seventh transistor M7 is connected to the second reference current source IB2, the source of the eighth transistor M8 is connected to the drain of the second transistor M2, the drain of the sixth transistor M6 is connected to the drain of the fourth transistor M4, the drain of the seventh transistor M7 is connected to the drain of the fifth transistor M5, and the drain of the eighth transistor M8 is connected to the drain of the third transistor M3.
[0068] The reference current Ibias is generally a current of the order of microamperes (μA), and the maximum discharge current of the protection module 120 is a current of the order of milliamperes (mA), so k2 will be relatively large, that is, the area of the second transistor M2 is relatively large.
[0069] The sixth transistor M6 is arranged between the fourth transistor M4 and the first reference current source IB1 for low voltage clamping, the seventh transistor M7 is arranged between the fifth transistor M5 and the second reference current source IB2 for low voltage clamping, the eighth transistor M8 is arranged between the third transistor M3 and the second transistor M2 for low voltage clamping, and the gate of the sixth transistor M6, the gate of the seventh transistor M7 and the gate of the eighth transistor M8 can receive a low voltage bias voltage V0, for example, 5V.
[0070] The low voltage bias voltage V0 can be generated by an LDO or a clamping circuit, so that the first reference current source IB1, the second reference current source IB, the first transistor M1 and the second transistor M2 can all use low voltage devices, so as to divide the protection circuit 100 into a low voltage domain and a high voltage domain, and the sensing voltage Vsense detected by the sensing end SENSE can be as high as tens of volts or even hundreds of volts.
[0071] Compared with high voltage devices, low voltage devices often have smaller area, so that the use of low voltage tubes as the second transistor M2 can reduce the area of the second transistor M2, so as to reduce the area occupied by the circuit, and the use of low voltage tubes as the first transistor M1 can further reduce the area occupied by the circuit, thereby facilitating the miniaturization development of the circuit.
[0072] In addition, low voltage devices also have higher precision, so that the use of low voltage tubes as the first transistor M1 and the second transistor M2 can improve the control precision of the maximum discharge current, and can further reduce the risk of chip burning caused by excessive discharge current.
[0073] In some embodiments, the withstand voltage value of the clamping transistor Mclp is greater than the second preset voltage, that is, the clamping transistor Mclp is a high voltage tube.
[0074] In some embodiments, continuing to refer to Figure 4 and Figure 5 The protection circuit 100 further comprises a ninth transistor M9 connected between the field ground end FGND and the output end of the current limiting module 130, and the control end of the ninth transistor M9 is connected to the bias voltage V0.
[0075] For example, Figure 4 and Figure 5As shown, the ninth transistor M9 is an NMOS, the protection circuit 100 further comprises a substrate end SUB, the source of the first transistor M1 and the source of the second transistor M2 are connected to the substrate end SUB and the source of the ninth transistor M9, the drain of the ninth transistor M9 is connected to the field ground end FGND, and the gate of the ninth transistor M9 receives a low voltage bias voltage V0, wherein the ninth transistor M9 plays a role of preventing damage of reverse connection negative voltage.
[0076] The present disclosure also provides a digital input receiver circuit comprising the protection circuit 100 provided by any of the above embodiments.
[0077] The digital input receiver circuit provided by the present disclosure comprises the protection circuit 100, which has the functional modules and beneficial effects of the protection circuit 100, which will not be repeated here.
[0078] The present disclosure also provides a digital input receiver chip comprising the protection circuit 100 provided by any of the above embodiments.
[0079] The digital input receiver chip provided by the present disclosure comprises the protection circuit 100, which has the functional modules and beneficial effects of the protection circuit 100, which will not be repeated here.
[0080] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Accordingly, the use of "a," "an," and "the" will be understood to include the plural reference, unless the context clearly indicates otherwise. Similarly, the word "comprise," "comprises," and "comprising" are to be construed as meaning "including but not limited to," unless the context clearly indicates otherwise. Likewise, the terms "include," "including," "comprise," "comprising," and "containing," "containing" are not intended to be limiting and are to be construed as meaning "including but not limited to."
[0081] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for illustrative purposes only and are not intended to limit the scope of the present application.
[0082] The above has described in detail several embodiments of the present disclosure, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.
Claims
1. A protection circuit, characterized by, The protection circuit comprises a current input terminal, a field ground terminal, a sensing terminal, a control module, a protection module and a current limiting module; a first input terminal of the control module is connected to the current input terminal, a second input terminal of the control module is connected to the sensing terminal, an output terminal of the control module is connected to a control terminal of the protection module, an input terminal of the protection module is connected to the current input terminal, and an output terminal of the protection module is connected to the field ground terminal through the current limiting module; the control module is configured to compare a working current in a chip with an input current of the current input terminal, and output a protection opening signal when the working current is less than the input current; the protection module is configured to turn on the current input terminal and the field ground terminal to discharge part of the input current according to the protection opening signal; the current limiting module is configured to limit a maximum discharge current of the protection module to be less than or equal to a threshold current.
2. The protection circuit of claim 1, wherein, the current limiting module comprises a first transistor, a second transistor and a reference current source; an output terminal of the reference current source is connected to a control terminal of the first transistor, a second terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor and a first terminal of the second transistor are connected to the field ground terminal, and a second terminal of the second transistor is connected to the output terminal of the protection module.
3. The protection circuit of claim 2, wherein, the protection module comprises a third transistor; a control terminal of the third transistor is connected to the output terminal of the control module, a first terminal of the third transistor is connected to the current input terminal, and a second terminal of the third transistor is connected to the field ground terminal through the current limiting module.
4. The protection circuit of claim 2, wherein, the current limiting module further comprises a clamping unit; a first terminal of the clamping unit is connected to the current input terminal, and a second terminal of the clamping unit is connected to the control terminal of the protection module; the clamping unit is configured to limit a maximum control voltage of the protection module to limit the maximum discharge current.
5. The protection circuit of claim 4, wherein, the clamping unit comprises a single-diode-connected clamping transistor connected between the current input terminal and the control terminal of the protection module; alternatively, the clamping unit comprises a plurality of diode-connected clamping transistors connected in series between the current input terminal and the control terminal of the protection module.
6. The protection circuit of claim 3, wherein, the control module comprises a resistor, a fourth transistor, a fifth transistor, a first reference current source and a second reference current source; a first terminal of the fourth transistor is connected to the current input terminal, a control terminal of the fourth transistor is connected to a second terminal of the fourth transistor and a control terminal of the fifth transistor, a first terminal of the fifth transistor is connected to a first terminal of the resistor, a second terminal of the resistor is connected to the sensing terminal, a second terminal of the fifth transistor is connected to the control terminal of the protection module, the second terminal of the fourth transistor is connected to the field ground terminal through the first reference current source, and the second terminal of the fifth transistor is connected to the field ground terminal through the second reference current source.
7. The protection circuit of claim 6, wherein, the protection circuit further comprises a sixth transistor, a seventh transistor and an eighth transistor; A second end of the fourth transistor is connected to the first reference current source through the sixth transistor, a second end of the fifth transistor is connected to the second reference current source through the seventh transistor, a second end of the third transistor is connected to a second end of the second transistor through the eighth transistor, and control ends of the sixth transistor, the seventh transistor and the eighth transistor are connected to a bias voltage; The first transistor, the second transistor, the sixth transistor, the seventh transistor and the eighth transistor have a withstand voltage less than a first preset voltage, and the third transistor, the fourth transistor and the fifth transistor have a withstand voltage greater than a second preset voltage, the second preset voltage being greater than the first preset voltage.
8. The protection circuit according to any one of claims 1 to 7, characterized in that, The protection circuit further comprises a ninth transistor. The ninth transistor is connected between the field ground end and an output end of the current limiting module, and a control end of the ninth transistor is connected to a bias voltage.
9. A digital input receiver circuit, characterized by The protection circuit comprises any one of claims 1-8.
10. A digital input receiver chip, comprising: The protection circuit comprises any one of claims 1-8.