Circuit board, filtering device and electronic device
By setting conductor connections within vias on the dielectric layer of the circuit board to form an inductor structure, and by using multiple conductors connected in parallel, the problem of large area occupied by the inductor structure is solved, realizing the miniaturization and thinning of the inductor structure, while improving space utilization and inductance value.
Patent Information
- Application Number
- CN202422682400.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2034-11-04
AI Technical Summary
In existing circuit boards, the inductor structure occupies a large area of the conductive layer, resulting in a large circuit board size and low space utilization.
The structure employs a first conductive layer, a first dielectric layer, and a second conductive layer stacked together. An inductor structure is formed by connecting conductors within vias on the dielectric layer. Multiple conductors are connected in parallel to reduce the DC internal resistance of the inductor structure and increase the inductance value.
This effectively reduces the area occupied by the inductor structure on the conductive layer, improves the space utilization of the circuit board, and realizes the miniaturization and thinning of the inductor structure, while maintaining a high inductance value and a low DC internal resistance.
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Figure CN223666528U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of electronic devices, and in particular to a circuit board, a filtering device, and an electronic device. BACKGROUND
[0002] The circuit board generally includes conductive layers and dielectric layers arranged in a stack, and the lines on the conductive layers can be configured in a "U shape" to construct an inductance structure in a manner of winding an analog inductance coil. However, the inductance structure occupies a large area of the conductive layers by using the lines on the conductive layers as the coil of the inductance structure. CONTENT OF THE UTILITY MODEL
[0003] Embodiments of the present application provide a circuit board, a filtering device, and an electronic device, which can reduce the area of the inductance structure occupied by the conductive layers.
[0004] In a first aspect, embodiments of the present application provide a circuit board, which includes first conductive layers, first dielectric layers, and second conductive layers arranged in a stack, the first conductive layers and the second conductive layers are respectively located on two sides of the first dielectric layers, the first conductive layers include first lines and second lines, the first lines and the second lines are arranged at a distance from each other, the second conductive layers include third lines, the first dielectric layers are provided with first vias and second vias, the first vias are provided with first conductors, one end of each first conductor is connected to a third line, the other end of the first conductor is connected to a first line, the second vias are provided with second conductors, one end of each second conductor is connected to a third line, the other end of the second conductor is connected to a second line, the first vias and the first conductors are multiple, and each first conductor is arranged in a first via. The first lines, the second lines, the third lines, the first conductors, and the second conductors constitute an inductance structure.
[0005] Through the above arrangement, the inductance structure includes the first conductors and the second conductors, the first conductors are arranged in the first vias, and the second conductors are arranged in the second vias, so that at least part of the inductance structure is located in the first vias and the second vias, thereby reducing the area of the inductance structure occupied by the first conductive layers and the second conductive layers. Meanwhile, each first conductor is connected to the first lines and the third lines, so that the inductance structure is relatively compact, the space utilization rate in the circuit board is improved, and the miniaturization and thinning of the inductance structure and the circuit board are facilitated. In addition, the multiple first conductors are arranged in parallel with each other, which also reduces the direct current resistance of the inductance structure, so that the inductance structure has a relatively high inductance value and a relatively low direct current resistance.
[0006] In some embodiments that can include the above embodiments, the second vias and the second conductors are multiple, and each second conductor is arranged in a second via.
[0007] By the above arrangement, the inductance structure occupies a smaller area of the first conductive layer and the second conductive layer. At the same time, each second conductor is connected with the second circuit and the third circuit, so that the inductance structure is more compact, the space utilization in the circuit board is improved, and the miniaturization and lightness of the inductance structure and the circuit board are facilitated. Moreover, the parallel connection of the plurality of second conductors also reduces the DC resistance of the inductance structure, so that the inductance structure has both high inductance and low DC resistance.
[0008] In some embodiments that can include the above embodiments, one of the plurality of first vias is spaced apart from the second via along a first direction parallel to the first dielectric layer, and the plurality of first vias are spaced apart along a second direction; the first direction is perpendicular to the second direction.
[0009] By the above arrangement, the parallel connection of the plurality of first conductors can reduce the DC resistance of the inductance structure, so that the inductance structure has both high inductance and low DC resistance.
[0010] In some embodiments that can include the above embodiments, the second via and the plurality of first vias are spaced apart along a first direction parallel to the first dielectric layer.
[0011] By the above arrangement, the parallel connection of the plurality of first conductors can reduce the DC resistance of the inductance structure, so that the inductance structure has both high inductance and low DC resistance.
[0012] In some embodiments that can include the above embodiments, the plurality of first vias are arranged in an array. By the above arrangement, the parallel connection of the plurality of first conductors can reduce the DC resistance of the inductance structure, so that the inductance structure has both high inductance and low DC resistance.
[0013] In some embodiments that can include the above embodiments, the circuit board further comprises a second dielectric layer, the second dielectric layer is arranged in a stack with the first conductive layer, and the first conductive layer is located between the first dielectric layer and the second dielectric layer.
[0014] By the above arrangement, the first circuit and the second circuit are located in the circuit board, and the third circuit is exposed on the surface of the circuit board.
[0015] In some embodiments that can include the above embodiments, the circuit board further comprises a third dielectric layer, the third dielectric layer is arranged in a stack with the second conductive layer, and the second conductive layer is located between the first dielectric layer and the third dielectric layer.
[0016] By the above arrangement, the third circuit is located in the circuit board, and the first circuit and the second circuit are exposed on the surface of the circuit board.
[0017] In some embodiments that can include the above embodiments, at least one first via is provided with a magnetic core.
[0018] Through the above arrangement, part of the magnetic induction lines of the inductance structure can pass through the magnetic core, thereby increasing the inductance value of the inductance structure. At the same time, since the magnetic core is arranged in the first via hole, the volume of the inductance structure and the circuit board is less affected, and even the volume of the inductance structure and the space occupied by the inductance structure on the circuit board can not be increased, thereby improving the space utilization rate in the circuit board and facilitating the miniaturization and thinning of the inductance structure and the circuit board. Moreover, since the magnetic core has electrical conductivity, arranging the magnetic core in the first via hole can reduce the DC resistance of the inductance structure.
[0019] In some embodiments that can include the above embodiments, a magnetic core is arranged in the second via hole.
[0020] Through the above arrangement, part of the magnetic induction lines of the inductance structure can pass through the magnetic core, thereby increasing the inductance value of the inductance structure. At the same time, since the magnetic core is arranged in the second via hole, the volume of the inductance structure and the circuit board is less affected, and even the volume of the inductance structure and the space occupied by the inductance structure on the circuit board can not be increased, thereby improving the space utilization rate in the circuit board and facilitating the miniaturization and thinning of the inductance structure and the circuit board. Moreover, since the magnetic core has weak electrical conductivity, arranging the magnetic core in the second via hole can partially reduce the DC resistance of the inductance structure.
[0021] In some embodiments that can include the above embodiments, the magnetic core includes at least one of an iron core, a cobalt core, and a nickel core.
[0022] Through the above arrangement, the magnetic core can increase the inductance value of the inductance structure to a range of two to three times.
[0023] In a second aspect, the embodiments of the present application provide a filtering device, which includes a capacitor structure and the circuit board of any of the above embodiments, and the capacitor structure is electrically connected with the inductance structure. Through the above arrangement, the size of the circuit board is small, which is conducive to the miniaturization and thinning of the filtering device.
[0024] In a third aspect, the embodiments of the present application provide an electronic device, which includes a housing and the filtering device of any of the above embodiments, and the filtering device is arranged in the housing. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 FIG. 1 is a structural schematic diagram of a circuit board in a first embodiment;
[0026] Figure 2 FIG. 2 is a structural schematic diagram of a circuit board in a second embodiment;
[0027] Figure 3 FIG. 3 is a structural schematic diagram of a circuit board in a third embodiment;
[0028] Figure 4Fig. 10 is a structural diagram of a circuit board in a fourth embodiment;
[0029] Figure 5 Fig. 11 is a structural diagram of an inductor structure in an embodiment;
[0030] Figure 6 Fig. 12 is a structural diagram of a circuit board in a fifth embodiment;
[0031] Figure 7 Fig. 13 is a structural diagram of a first line, a second line, a third line, and a magnetic core in an embodiment;
[0032] Figure 8 Fig. 14 is a flowchart of a process of manufacturing a circuit board in an embodiment;
[0033] Figure 9 Fig. 15 is a structural diagram of a third line, a first conductor, and a second conductor in a first embodiment;
[0034] Figure 10 Fig. 16 is a structural diagram of a third line, a first conductor, and a second conductor in a second embodiment;
[0035] Figure 11 Fig. 17 is a structural diagram of a third line, a first conductor, and a second conductor in a third embodiment.
[0036] Explanation of Reference Numerals:
[0037] 10: circuit board; 11: inductor structure; 12: first printed circuit board; 13: second printed circuit board; 14: third printed circuit board;
[0038] 100: first conductive layer; 110: first line; 120: second line;
[0039] 200: second conductive layer; 210: third line;
[0040] 300: first dielectric layer; 310: first via; 320: second via;
[0041] 400: second dielectric layer; 500: third dielectric layer;
[0042] 600: first conductor; 700: second conductor;
[0043] 810: first pad; 820: second pad; 830: third pad; 840: fourth pad; 850: fifth pad; 860: sixth pad; 870: seventh pad; 880: eighth pad; 890: solder layer;
[0044] 900: magnetic core. DETAILED DESCRIPTION
[0045] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0046] The electronic device can include at least one of a mobile phone, a tablet computer, a router, a frequency converter, and the like. The embodiments of the present application do not limit the type of the electronic device.
[0047] The following will take the electronic device as a mobile phone as an example for introduction. The electronic device in the embodiments of the present application is not limited to a mobile phone. The electronic device includes a shell, a mainboard, and a controller. The mainboard is arranged in the shell. The controller can be arranged on the mainboard and can be electrically connected with the mainboard. In some implementation manners, the controller can include at least one of a central processing unit (CPU), a system on chip (SoC), and a power conversion chip.
[0048] The electronic device further includes a radio frequency device. The radio frequency device can include at least one of an antenna, a radio frequency chip, and an amplifier. The radio frequency device can be arranged on the mainboard and can be electrically connected with the mainboard. The electronic device can send or receive signals through the radio frequency device.
[0049] The electronic device further includes a filtering device. The filtering device can be arranged on the mainboard. The filtering device can be electrically connected with the radio frequency device. The filtering device can be used to screen signals of specific frequencies, or the filtering device can also be used to filter noise and interference in signals.
[0050] In an optional embodiment, the electronic device of the embodiments of the present application further includes a circuit board. The circuit board can include at least part of the mainboard. The circuit board includes an inductive structure. The inductive structure can be electrically connected with the power conversion chip.
[0051] The embodiments of the present application further provide a filtering device. The filtering device includes a capacitive structure. The capacitive structure can include at least one of a lumped capacitor and a distributed capacitor. The "lumped capacitor" can be understood as a component that presents capacitance, such as a capacitor element. The "distributed capacitor" can be understood as an equivalent capacitor formed by two conductive pieces with a certain gap.
[0052] The filtering device further includes a circuit board. The circuit board can include at least part of the mainboard. The circuit board is provided with an inductive structure. The inductive structure is electrically connected with the capacitive structure. The inductive structure can be connected in series with the capacitive structure, or the inductive structure can also be connected in parallel with the capacitive structure.
[0053] Reference is made to Figure 1 The circuit board 10 includes a plurality of conductor layers and a plurality of insulating layers which are sequentially stacked, and an insulating layer is arranged between any two adjacent conductor layers. The material of the conductor layers can include copper, and the thickness of the conductor layers can be in the range of 16 μm to 40 μm. The material of the insulating layers can include at least one of epoxy resin, glass fiber, flame retardant, etc.
[0054] The circuit board 10 further includes a plurality of connection vias which penetrate at least one insulating layer. The connection vias are provided with a copper plating layer on the wall of the connection vias, which can be used to connect different conductor layers.
[0055] The circuit board 10 includes a first conductive layer 100 and a second conductive layer 200 which are sequentially stacked, and the first conductive layer 100 and the second conductive layer 200 are spaced apart along a third direction z, which is the thickness direction of the circuit board 10. The first conductive layer 100 and the second conductive layer 200 can each include at least one conductor layer, for example, the first conductive layer 100 and the second conductive layer 200 can each include one to four conductor layers. In one example, the first conductive layer 100 and / or the second conductive layer 200 includes two conductor layers, and the thickness of the first conductive layer 100 and / or the second conductive layer 200 is in the range of 32 μm to 80 μm. In another example, the first conductive layer 100 and / or the second conductive layer 200 includes three conductor layers, and the thickness of the first conductive layer 100 and / or the second conductive layer 200 is in the range of 48 μm to 120 μm.
[0056] In the above examples, the plurality of conductor layers included in the first conductive layer 100 and / or the second conductive layer 200 can be connected through the copper plating layer on the wall of the plurality of connection vias. In an alternative embodiment, the plurality of connection vias are spaced apart from each other. In another alternative embodiment, the plurality of connection vias can be connected to each other through a thermal bar process, so that the copper plating layers are connected to each other, thereby reducing the direct current resistance of the first conductive layer 100 and / or the second conductive layer 200.
[0057] The first conductive layer 100 includes a first line 110 and a second line 120 which are spaced apart, and the second conductive layer 200 includes a third line 210. In one example, the first line 110 and the second line 120 are spaced apart along a first direction x, which is the length direction of the third line 210, and the first direction x is parallel to the first conductive layer 100 and the second conductive layer 200. In some implementations, the length direction of the first line 110 and the length direction of the second line 120 can both be parallel to the first direction x.
[0058] In some implementations, in the first direction x, the length dimension of the first line 110 and the length dimension of the second line 120 can be in a range of 50 mil to 200 mil (1270 μm to 5080 μm). For example, the length dimension of the first line 110 and the length dimension of the second line 120 can be in a range of 100 mil to 150 mil (2540 μm to 3810 μm).
[0059] In some implementations, in the first direction x, the length dimension of the third line 210 can be in a range of 50 mil to 200 mil (1270 μm to 5080 μm). For example, the length dimension of the third line 210 can be in a range of 100 mil to 150 mil (2540 μm to 3810 μm).
[0060] The width direction of the first line 110, the width direction of the second line 120, and the width direction of the third line 210 can be parallel to the second direction y, the second direction y is parallel to the first conductive layer 100 and the second conductive layer 200, and the second direction y is perpendicular to the first direction x. In some implementations, the width dimension of the first line 110, the width dimension of the second line 120, and the width dimension of the third line 210 can be in a range of 40 mil to 100 mil (1016 μm to 2540 μm). For example, the width dimension of the first line 110, the width dimension of the second line 120, and the width dimension of the third line 210 can be in a range of 50 mil to 80 mil (1270 μm to 2032 μm).
[0061] The circuit board 10 further includes a first dielectric layer 300, which can include a plurality of insulating layers. The first dielectric layer 300 is arranged in a stack with the first conductive layer 100 and the second conductive layer 200, and is located between the first conductive layer 100 and the second conductive layer 200, and is parallel to the first direction x and the second direction y. The first dielectric layer 300 is provided with a first via 310 and a second via 320, which are arranged spaced apart from each other. One end of the first via 310 faces the first line 110, and the other end of the first via 310 faces the third line 210; one end of the second via 320 faces the second line 120, and the other end of the second via 320 faces the third line 210.
[0062] The length direction of the first via hole 310 and the length direction of the second via hole 320 are both parallel to the third direction z, and the length dimension of the first via hole 310 can be equal to the length dimension of the second via hole 320. In some implementations, the length dimension of the first via hole 310 and the length dimension of the second via hole 320 can both be in the range of 400 μm to 2000 μm. For example, the length dimension of the first via hole 310 and the length dimension of the second via hole 320 can both include at least one of 400 μm, 800 μm and 2000 μm.
[0063] In some implementations, the first via hole 310 and the second via hole 320 can both be made by a mechanical drilling process, whereby the diameter dimension of the first via hole 310 and the diameter dimension of the second via hole 320 can both be in the range of 150 μm to 600 μm. In other implementations, the first via hole 310 and the second via hole 320 can also be made by a laser drilling process, whereby the diameter dimension of the first via hole 310 and the diameter dimension of the second via hole 320 can both be in the range of 10 μm to 125 μm. In an alternative embodiment, the diameter dimension of the first via hole 310 and the diameter dimension of the second via hole 320 are in the range of 6 mil to 12 mil (152.4 μm to 304.8 μm).
[0064] In the above example, the first via hole 310 and the second via hole 320 can both include at least one of a through-hole, a blind hole and a buried hole.
[0065] In an alternative embodiment, the first via hole 310 and the second via hole 320 are both through-holes. Thus, as shown in FIG. 1, the first line 110, the second line 120 and the third line 210 are all exposed on the circuit board 10. Figure 1
[0066] In an alternative embodiment, the first via hole 310 and the second via hole 320 are both blind holes.
[0067] In one example, the circuit board 10 can further include a second dielectric layer, the second dielectric layer, the first conductive layer 100 and the first dielectric layer 300 are sequentially stacked, and the first conductive layer 100 is between the second dielectric layer and the first dielectric layer 300. Thus, the first line 110 and the second line 120 are between the second dielectric layer and the first dielectric layer 300, and the third line 210 is exposed on the circuit board 10.
[0068] In another example, please refer to Figure 2 The circuit board 10 can further include a third dielectric layer 500, the first dielectric layer 300, the second conductive layer 200 and the third dielectric layer 500 are stacked in sequence, and the second conductive layer 200 is located between the first dielectric layer 300 and the third dielectric layer 500. In this way, the third line 210 is located between the third dielectric layer 500 and the first dielectric layer 300, and the first line 110 and the second line 120 are exposed on the circuit board 10.
[0069] In an alternative embodiment, referring to Figure 3 The first via 310 and the second via 320 are both buried vias. For example, the circuit board 10 further includes a second dielectric layer 400 and a third dielectric layer 500, and the second dielectric layer 400, the first conductive layer 100, the first dielectric layer 300, the second conductive layer 200 and the third dielectric layer 500 are stacked in sequence. Based on the above arrangement, the first line 110 and the second line 120 are located between the second dielectric layer 400 and the first dielectric layer 300, and the third line 210 is located between the third dielectric layer 500 and the first dielectric layer 300.
[0070] In the above embodiments, the circuit board 10 can include one printed circuit board 10. In one example, as shown in Figure 1 the printed circuit board 10 can include the first conductive layer 100, the first dielectric layer 300 and the second conductive layer 200; in another example, as shown in Figure 2 the printed circuit board 10 can include the first conductive layer 100, the first dielectric layer 300, the second conductive layer 200 and the third dielectric layer 500; and in yet another example, as shown in Figure 3 the printed circuit board 10 can include the second dielectric layer 400, the first conductive layer 100, the first dielectric layer 300, the second conductive layer 200 and the third dielectric layer 500.
[0071] Alternatively, the circuit board 10 can further include a plurality of printed circuit boards 10. For example, as shown in Figure 4As shown, in the embodiment in which the circuit board 10 includes the second dielectric layer 400 and the third dielectric layer 500, the circuit board 10 can include the first printed circuit board 12, the second printed circuit board 13 and the third printed circuit board 14 which are sequentially stacked, and the second printed circuit board 13 is located between the first printed circuit board 12 and the third printed circuit board 14. The first printed circuit board 12 includes the first conductive layer 100 and the second dielectric layer 400 which are sequentially stacked, and the first printed circuit board 12 is connected with the second printed circuit board 13 at the side of the first printed circuit board 12 provided with the first conductive layer 100. The second printed circuit board 13 includes the first dielectric layer 300. The third printed circuit board 14 includes the third dielectric layer 500 and the second conductive layer 200 which are sequentially stacked, and the third printed circuit board 14 is connected with the second printed circuit board 13 at the side of the third printed circuit board 14 provided with the second conductive layer 200. In some implementations, the first printed circuit board 12 is soldered with the second printed circuit board 13, and the second printed circuit board 13 is soldered with the third printed circuit board 14.
[0072] Please refer to Figure 1 The first via hole 310 is provided with the first conductor 600 which can be attached to the hole wall of the first via hole 310. One end of the first conductor 600 is connected with the first line 110, and the other end of the first conductor 600 is connected with the third line 210, so as to connect the first line 110 and the third line 210. Based on the above arrangement, the length of the first conductor 600 is equal to the length of the first via hole 310.
[0073] The second via hole 320 is provided with the second conductor 700 which can be attached to the hole wall of the second via hole 320. One end of the second conductor 700 is connected with the second line 120, and the other end of the second conductor 700 is connected with the third line 210, so as to connect the second line 120 and the third line 210. Based on the above arrangement, the length of the second conductor 700 is equal to the length of the second via hole 320.
[0074] In some implementations, the material of the first conductor 600 and the second conductor 700 can include copper, and the first conductor 600 can be attached to the hole wall of the first via hole 310 by copper plating process, and the second conductor 700 can be attached to the hole wall of the second via hole 320 by copper plating process.
[0075] Through the above arrangement, the first line 110, the second line 120, the third line 210, the first conductor 600 and the second conductor 700 form an inductance structure 11. The inductance structure 11 has a first port and a second port, the first port can be located on the first line 110, and the second port can be located on the second line 120. For example, the first port can be located at one end of the first line 110 close to the second line 120, and the second port can be located at one end of the second line 120 close to the first line 110.
[0076] As shown in Figure 5 , the inductance structure 11 can be connected with external circuits through the first port and the second port. Thus, the current enters the inductance structure 11 from the first port, and then sequentially passes through the first circuit, the first conductor 600, the third line 210, the second conductor 700 and the second line 120, and finally leaves the inductance structure 11 from the second port.
[0077] In the embodiment in which the plurality of connection vias are in communication with each other, the copper plating layers are connected with each other, and the DC resistance of the inductance structure 11 is also reduced.
[0078] Please refer back to Figure 1 , the circuit board 10 further includes a first pad 810 and a second pad 820, and the first pad 810 and the second pad 820 can each include at least part of the conductor layer and are each connected with the first conductor 600. The first pad 810 is located on the side of the first conductor 600 close to the first conductive layer 100, and is used to connect the first conductor 600 and the first line 110; the second pad 820 is located on the side of the first conductor 600 close to the second conductive layer 200, and is used to connect the first conductor 600 and the third line 210. In some implementations, the first pad 810 can include at least part of the first line 110, and the second pad 820 can include at least part of the third line 210.
[0079] In the above embodiment, the first pad 810 and the second pad 820 can each be circular, and the diameter of the first pad 810 and the diameter of the second pad 820 can each be in the range of 10 mil to 18 mil (254 μm to 457.2 μm); or the first pad 810 and the second pad 820 can each be rectangular, the length of the first pad 810 and the length of the second pad 820 can each be in the range of 30 mil to 80 mil (762 μm to 2032 μm), and the width of the first pad 810 and the width of the second pad 820 can each be in the range of 10 mil to 30 mil (254 μm to 762 μm).
[0080] Please refer back to Figure 1The circuit board 10 further includes a third pad 830 and a fourth pad 840, each of which can include at least part of the conductor layer and is connected to the second conductor 700. The third pad 830 is located on the side of the second conductor 700 close to the first conductive layer 100 and is used to connect the second conductor 700 and the second line 120; the fourth pad 840 is located on the side of the second conductor 700 close to the second conductive layer 200 and is used to connect the second conductor 700 and the third line 210. In some implementations, the third pad 830 can include at least part of the second line 120, and the fourth pad can include at least part of the third line 210.
[0081] In the above examples, the shape and size of the third pad 830 and the fourth pad 840 can refer to the shape and size of the first pad 810 and the second pad 820, which will not be described here.
[0082] Please refer to Figure 6 In the embodiment in which the circuit board 10 includes the first printed circuit board 12, the second printed circuit board 13 and the third printed circuit board 14, the circuit board 10 further includes a fifth pad 850, a sixth pad 860, a seventh pad 870, an eighth pad 880 and a solder layer 890, which can include solder.
[0083] The fifth pad 850 is provided on the first printed circuit board 12 and is connected to the first line 110 and can include at least part of the first line 110. The fifth pad 850 is soldered to the first pad 810, and at least part of the solder layer 890 is located between the fifth pad 850 and the first pad 810 and connects the fifth pad 850 and the first pad 810. In this way, the first line 110 and the first conductor 600 are connected, and the first printed circuit board 12 and the second printed circuit board 13 are connected.
[0084] The seventh pad 870 is provided on the first printed circuit board 12 and is connected to the second line 120 and can include at least part of the second line 120. The seventh pad 870 is soldered to the third pad 830, and at least part of the solder layer 890 is located between the seventh pad 870 and the third pad 830 and connects the seventh pad 870 and the third pad 830. In this way, the second line 120 and the second conductor 700 are connected, and the first printed circuit board 12 and the second printed circuit board 13 are connected.
[0085] The sixth pad 860 and the eighth pad 880 are both arranged on the second printed circuit board 13, and both are connected with the third line 210 and can include at least part of the third line 210. The sixth pad 860 is soldered with the second pad 820, and at least part of the solder layer 890 is arranged between the sixth pad 860 and the second pad 820 and connects the sixth pad 860 and the second pad 820; the eighth pad 880 is soldered with the fourth pad 840, and at least part of the solder layer 890 is arranged between the eighth pad 880 and the fourth pad 840 and connects the eighth pad 880 and the fourth pad 840. Through the above arrangement, the third line 210 is connected with the first conductor 600 and the second conductor 700, and the second printed circuit board 13 and the third printed circuit board 14 are connected.
[0086] The circuit board 10 in the above embodiment can be manufactured by a plated over filled via (POFV) process.
[0087] In an optional embodiment, as shown in Figure 1 The inductance structure 11 further includes a magnetic core 900 arranged in the first via 310, and the material for manufacturing the magnetic core 900 can include at least one of ferromagnetic materials such as iron, cobalt and nickel. Through the above arrangement, part of the magnetic induction lines of the inductance structure 11 can pass through the magnetic core 900, thereby increasing the inductance of the inductance structure 11. For example, the magnetic core 900 can increase the inductance of the inductance structure 11 to a range of two to three times. At the same time, since the magnetic core 900 is arranged in the first via 310, it has little effect on the volume of the inductance structure 11 and the circuit board 10, and can even not increase the volume of the inductance structure 11 and the space occupied by the inductance structure 11 on the circuit board 10, thereby improving the space utilization of the circuit board 10 and facilitating the miniaturization and lightness of the inductance structure 11, the circuit board 10 and the electronic device. In addition, please refer to Figure 1 and Figure 7 The magnetic core 900 connects the first line 110 and the third line 210, and connects the second line 120 and the third line 210. Since the magnetic core 900 has weak conductivity, it can partially reduce the direct current resistance of the inductance structure 11.
[0088] In an optional embodiment, as shown in Figure 1 The magnetic core 900 can also be arranged in the second via 320.
[0089] In some implementations, the process for manufacturing the magnetic core 900 can be added in the process for manufacturing the circuit board 10, for example, in the plated over filled via (POFV) process.
[0090] For example, as shown in Figure 8As shown, the process steps of preparing the circuit board 10 can include:
[0091] S100, making a first via and a second via on a first medium.
[0092] The way of making the first via 310 and the second via 320 can refer to the above, which will not be repeated here.
[0093] S200, making a first conductive layer, a second conductive layer, a first conductor and a second conductor on the first medium layer.
[0094] The first line 110, the second line 120, the third line 210, the first conductor 600 and the second conductor 700 can be made by at least one of the chemical copper plating process or the electroplating copper process.
[0095] S300, adding a ferromagnetic material to the first via and / or the second via.
[0096] S400, curing the ferromagnetic material.
[0097] In the embodiment in which the circuit board 10 further includes other vias in addition to the first via 310 and the second via 320, the steps of preparing the circuit board 10 can further include:
[0098] S500, adding a resin to the other vias.
[0099] S600, curing the resin.
[0100] S700, making a first line and a second line on the first conductive layer, and making a third line on the second conductive layer.
[0101] The first line 110 and the second line 120 can be formed by etching the copper on the first conductive layer 100 except the first line 110 and the second line 120 with an etching solution, and the etching solution can include at least one of a copper chloride solution and a ferric chloride solution.
[0102] S800, polishing the circuit board.
[0103] Through the above steps, the oxidation and other impurities on the first line 110, the second line 120 and the third line 210 can be removed.
[0104] S900, plating copper on the first line, the second line and the third line.
[0105] The copper plating on the first line 110, the second line 120 and the third line 210 can be made by at least one of the chemical copper plating process or the electroplating copper process. Through the above steps, the thickness dimension of the first line 110, the second line 120 and the third line 210 can be increased.
[0106] Please refer to Figure 6 , the first via hole 310 and the first conductor 600 of the embodiment of the application are each provided with a plurality of first conductors 600, each of which is arranged in a first via hole 310. Among them, one end of each first conductor 600 is connected with the first line 110, and the other end of each first conductor 600 is connected with the third line 210. Thus, as shown in the figure, each first conductor 600 is arranged in parallel with each other, and the current entering the inductive structure 11 from the first port can be transmitted to the third line 210 through different first conductors 600 respectively, and then converged in the third line 210, and then transmitted through the second conductor 700 and the second line 120, and then leaving the inductive structure 11 from the second port. Figure 5
[0107] The circuit board 10 of the embodiment of the application comprises a first conductive layer 100, a first dielectric layer 300 and a second conductive layer 200 arranged in layers, the first dielectric layer 300 is located between the first conductive layer 100 and the second conductive layer 200; the first conductive layer 100 comprises a first line 110 and a second line 120 arranged at intervals, and the second conductive layer 200 comprises a third line 210; the circuit board 10 further comprises an inductive structure 11, the inductive structure 11 comprises the first line 110, the second line 120, the third line 210, a first conductor 600 and a second conductor 700, and the first conductor 600 is a plurality of first conductors; the first dielectric layer 300 is provided with a first via hole 310 and a second via hole 320, and the first via hole 310 is a plurality of first via holes; each first conductor 600 is arranged in a first via hole 310, one end of each first conductor 600 is connected with the third line 210, and the other end of each first conductor 600 is connected with the first line 110; the second conductor 700 is arranged in the second via hole 320, one end of the second conductor 700 is connected with the third line 210, and the other end of the second conductor 700 is connected with the second line 120. Among them, the inductive structure 11 comprises the first conductor 600 and the second conductor 700, the first conductor 600 is arranged in the first via hole 310, and the second conductor 700 is arranged in the second via hole 320, so that at least part of the inductive structure 11 is located in the first via hole 310 and the second via hole 320, thereby reducing the area occupied by the inductive structure 11 in the first conductive layer 100 and the second conductive layer 200.
[0108] In the above example, each first conductor 600 is connected with the first line 110 and the third line 210, so that the inductive structure 11 is relatively compact, the space utilization rate in the circuit board 10 is improved, and the miniaturization and lightness and thinness of the inductive structure 11, the circuit board 10 and the electronic device are facilitated. At the same time, the parallel arrangement of the plurality of first conductors 600 also reduces the direct current resistance of the inductive structure 11, so that the inductive structure 11 has both a high inductance and a low direct current resistance.
[0109] In some implementations, the spacing between two adjacent first vias 310 can be in a range from 10 mil to 20 mil (254 μm to 508 μm). For example, the spacing between two adjacent first vias 310 can be in a range from 10 mil to 15 mil (254 μm to 381 μm).
[0110] In some implementations, the number of first vias 310 can be in a range from two to eight. For example, the number of first vias 310 can be in a range from three to five.
[0111] In an alternative embodiment, as shown in Figure 6 , the first vias 310 can be spaced apart along the first direction x, and the second via 320 can be spaced apart from any of the first vias 310 along the first direction x.
[0112] In another alternative embodiment, as shown in Figure 1 and Figure 9 , the first vias 310 can be spaced apart along the second direction y, and one of the first vias 310 and the second via 320 can be spaced apart along the first direction x. In some implementations, the number of first vias 310 can be three, four, or five.
[0113] In yet another alternative embodiment, the first vias 310 can be arranged in an array. For example, as shown in Figure 1 and Figure 10 , the first vias 310 can be four, and the four first vias 310 can be arranged in two rows, each row including two first vias 310, and the first vias 310 in each row can be spaced apart along the first direction x. Alternatively, as shown in Figure 1 and Figure 11 , the first vias 310 can be six, and the six first vias 310 can be arranged in three rows, each row including two first vias 310, and the first vias 310 in each row can be spaced apart along the first direction x.
[0114] In embodiments where the circuit board 10 includes the first pads 810 and the second pads 820, as shown in Figure 6 , each of the first pads 810 and the second pads 820 can be connected to the first conductors 600; or each of the first pads 810 and the second pads 820 can be provided with a plurality of pads, each of the first pads 810 being connected to a different first conductor 600, and each of the second pads 820 being connected to a different second conductor 700.
[0115] In an alternative embodiment, as shown in Figure 6As shown, multiple second vias 320 and second conductors 700 can be provided, with each second conductor 700 disposed within a second via 320. One end of each second conductor 700 is connected to the second line 120, and the other end of each second conductor 700 is connected to the third line 210. Thus, as... Figure 5 As shown, the second conductors 700 are connected in parallel. After the current enters the inductor structure 11 from the first port, it can be transmitted to the third line 210 through different first conductors 600, and then converge in the third line 210. After that, it is transmitted to the third line 210 through different second conductors 700, and then converges in the second line 120 before leaving the inductor structure 11 from the second port.
[0116] Through the above arrangement, the area occupied by the inductor structure 11 in the first conductive layer 100 and the second conductive layer 200 is relatively small; and each of the second conductors 700 is connected to the second line 120 and the third line 210, making the inductor structure 11 more compact, improving the space utilization rate within the circuit board 10, and facilitating the miniaturization and thinning of the inductor structure 11, the circuit board 10, and the electronic device; at the same time, the parallel arrangement of multiple second conductors 700 also reduces the DC internal resistance of the inductor structure 11, so that the inductor structure 11 has both high inductance and low DC internal resistance.
[0117] In the above embodiments, the arrangement of the plurality of second vias 320 and the plurality of second conductors 700 can refer to the arrangement of the plurality of first vias 310 and the plurality of first conductors 600, and will not be repeated here.
[0118] Based on the above structure, the inductance of the first line 110, the second line 120, or the third line 210 can be obtained using Formula 1:
[0119] Formula 1:
[0120] Wherein, Len is the length of the first line 110, the second line 120, or the third line 210, w is the width of the first line 110, the second line 120, or the third line 210, and t is the thickness of the first line 110, the second line 120, or the third line 210.
[0121] The DC internal resistance of the first line 110, the second line 120, or the third line 210 can be obtained by formula 2:
[0122] Formula 2:
[0123] Where ρ is the electrical conductivity of copper: 0.01851 Ω·mm 2 / m.
[0124] The inductance of the first conductor 600 or the second conductor 700 can be obtained by Formula 3:
[0125] Formula 3:
[0126] wherein d is the diameter dimension of the first pad 810 or the third pad 830, and h is the length dimension of the first conductor 600 or the second conductor 700, and the length dimension of the first conductor 600 or the second conductor 700 is directly proportional to the value of the inductance of the first conductor 600 or the second conductor 700.
[0127] The DC resistance of the first conductor 600 or the second conductor 700 can be obtained by Formula 4:
[0128] Formula 4:
[0129] wherein r is the radius dimension of the first via 310 or the second via 320.
[0130] Based on the above settings, the inductance of the inductance structure 11 can be obtained by Formula 5:
[0131] Formula 5:
[0132] wherein N is the sum of the number of the first conductor 600 and the second conductor 700, and K is the multiple value of the inductance structure 11 that can be increased by the magnetic core 900. For example, when the inductance structure 11 is doubled by the magnetic core 900, the value of K is 2; when the circuit board 10 does not have the magnetic core 900, the value of K is 1.
[0133] The inductance of the inductance structure 11 can be obtained by Formula 5 by taking the values in the above embodiments, and the inductance of the inductance structure 11 can be in the range of 1.2nH to 6nH. In an alternative embodiment, the inductance of the inductance structure 11 is in the range of 2.4nH to 4nH. For example, the inductance of the inductance structure 11 can be 3nH.
[0134] Based on the above settings, the DC resistance of the inductance structure 11 can be obtained by Formula 6:
[0135] Formula 6:
[0136] The DC resistance of the inductance structure 11 can be obtained by Formula 6 by taking the values in the above embodiments, and the value of the DC resistance of the inductance structure 11 can be in the range of 0.15mΩ to 12mΩ. In an alternative embodiment, the value of the DC resistance of the inductance structure 11 is less than 3mΩ. In another alternative embodiment, the value of the DC resistance of the inductance structure 11 is in the range of 0.8mΩ to 1.5mΩ. For example, the value of the DC resistance of the inductance structure 11 can be 1.5mΩ.
[0137] In one example, as shown in the circuit board 10, Figure 6 The first printed circuit board 12 is a main board, the thickness of the first printed circuit board 12 is 600μm; the second printed circuit board 13 is a frame board, the thickness of the second printed circuit board 13 is 800μm; the third printed circuit board 14 is a radio frequency printed circuit board (RFPCB for short), the thickness of the third printed circuit board 14 is 450μm; the first pad 810, the second pad 820, …, the eighth pad 880 are all rectangular, the length of the rectangle is 50mil (1270μm), and the width is 15mil (381μm); the first conductor 600 and the second conductor 700 are both provided with four, and each first conductor 600 and each second conductor 700 are arranged at intervals along the first direction x; the length of the first line 110, the second line 120 is 120mil (3048μm), the length of the third line 210 is 140mil (3048μm), the width of the first line 110, the second line 120 and the third line 210 is 50mil (1270μm), and the area of the first line 110, the second line 120 and the third line 210 is about 19.64mm 2 ; the first conductive layer 100 includes three conductor layers, and the second conductive layer 200 includes two conductor layers.
[0138] Based on the above data, the calculation can obtain Figure 6 The inductance of the inductance structure 11 shown in the figure is 3.03nH, and the direct current resistance is 1.7mΩ.
[0139] It should be noted that in the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood broadly, for example, it can be fixedly connected or integrally connected; it can also be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.
[0140] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or replace some or as many technical features as possible with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A circuit board, characterized by, Comprising: a first conductive layer, a first dielectric layer and a second conductive layer arranged in layers, the first dielectric layer being located between the first conductive layer and the second conductive layer; the first conductive layer comprising first and second lines arranged at intervals, the second conductive layer comprising a third line; an inductive structure comprising the first line, the second line, the third line, first conductors and second conductors, the first conductors being a plurality; a first via and a second via are arranged on the first dielectric layer, the first via being a plurality; each of the first conductors is arranged in one of the first vias, one end of each of the first conductors being connected to the third line, the other end of each of the first conductors being connected to the first line; the second conductors are arranged in the second vias, one end of each of the second conductors being connected to the third line, the other end of each of the second conductors being connected to the second line.
2. The circuit board of claim 1, wherein The second via and the second conductor are a plurality, each of the second conductors is arranged in one of the second vias.
3. The circuit board according to claim 1 or 2, characterized by One of the first vias and the second via are arranged at intervals along a first direction parallel to the first dielectric layer, a plurality of the first vias are arranged at intervals along a second direction; the first direction is perpendicular to the second direction.
4. The circuit board of claim 3, wherein The second via and a plurality of the first vias are arranged at intervals along a first direction parallel to the first dielectric layer.
5. The circuit board of claim 4, wherein, A plurality of the first vias are arranged in an array.
6. The circuit board of claim 1, wherein The circuit board further comprises a second dielectric layer, the second dielectric layer being arranged in layers with the first conductive layer, the first conductive layer being located between the first dielectric layer and the second dielectric layer.
7. The circuit board of claim 6, wherein The circuit board further comprises a third dielectric layer, the third dielectric layer being arranged in layers with the second conductive layer, the second conductive layer being located between the first dielectric layer and the third dielectric layer.
8. The circuit board of claim 1, wherein, At least one of the first vias is provided with a magnetic core; and / or, The second via is provided with a magnetic core.
9. The circuit board of claim 8, wherein, The magnetic core comprises at least one of an iron core, a cobalt core and a nickel core.
10. A filtering device, characterized in that Comprising: a capacitive structure, and the circuit board of any one of claims 1 to 9, the capacitive structure being electrically connected to the inductive structure.
11. An electronic device, comprising: Comprising: a housing, and the filtering device of claim 10, the filtering device being arranged in the housing.