Silicon carbide MOSFET device
By forming a PN junction by setting N- and PP regions outside the trench gate oxide layer, the interface electric field is reduced, which solves the early breakdown problem of trench gate silicon carbide MOSFETs and improves the reliability and on-resistance of the device.
Patent Information
- Application Number
- CN202423299997.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2034-12-31
AI Technical Summary
The electric field is concentrated at the apex of the gate oxide layer of a trench-gate silicon carbide MOSFET, leading to early breakdown failure and affecting device reliability.
An N-region and a PP region are formed outside the trench gate oxide layer to create a PN junction, thereby reducing the interfacial electric field. The design of the N-region and the Poly layer reduces interfacial state scattering and improves the channel mobility.
It effectively avoids early breakdown of the gate oxide layer, improves device reliability and on-resistance, and enhances gate control capability.
Smart Images
Figure CN223666687U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device. Background Technology
[0002] Silicon carbide, as a third-generation wide bandgap semiconductor material, has many advantages such as a large bandgap, high critical breakdown field strength, high thermal conductivity, fast carrier saturation drift velocity, and high thermal stability. Therefore, silicon carbide-based power devices are widely used in high-power, high-end applications such as high temperature, high voltage, and high frequency.
[0003] MOSFETs are one of the fundamental components of integrated circuit power devices. Compared with traditional silicon-based MOSFETs, silicon carbide MOSFETs have lower losses and higher voltage withstand capabilities. Silicon carbide MOSFETs are classified into planar gate MOSFETs and trench gate MOSFETs according to their technical approach. The biggest difference between trench gate silicon carbide MOSFETs and planar gate silicon carbide MOSFETs is that the conductive channel uses a trench gate, which increases the contact area, reduces the device size, significantly improves power density, and enhances the gate's ability to control the channel current. However, this also brings the disadvantage that the gate of trench gate silicon carbide MOSFETs withstands a higher electric field, especially at the two apex corners of the trench gate, where the electric field is concentrated, causing the gate oxide layer at the apex corners to break down prematurely, leading to device failure. Therefore, how to improve the reliability of the trench gate oxide layer is a technical problem that urgently needs to be solved in this case. Utility Model Content
[0004] To address the above problems, this invention provides a silicon carbide MOSFET device that reduces the interfacial electric field at the gate oxide, avoids early breakdown failure, and improves device reliability.
[0005] The technical solution of this utility model is:
[0006] A silicon carbide MOSFET device includes, from bottom to top, a drain metal layer, an N+ substrate layer, an N-drift layer, an N-epipolar layer, a PW region, an N+ region, an ohmic contact alloy layer, and a source metal layer;
[0007] The N-epipolar layer is provided with:
[0008] The NN region is provided in pairs, spaced apart within the N-epipolar layer;
[0009] The PP region is located between the pair of NN regions, and its bottom surface is on the same plane as the bottom surface of the NN region.
[0010] The P+ region extends downward from the top surface of the N+ region into the PW region, and is spaced apart from the bottom surface of the PW region.
[0011] The N-region has a U-shaped cross-section, extending downwards from the top surface of the N+ region to the top surface of the PP region, and its side is connected to the NN region;
[0012] The gate oxide layer has a U-shaped cross-section and extends downward along the inner sidewall of the N-region;
[0013] A poly layer is disposed within the gate oxide layer, with its top surface flush with both the gate oxide layer and the top surface of the N-region.
[0014] An isolation dielectric layer is provided on the top surface of the N+ region, N- region, gate oxide layer, and Poly layer.
[0015] Specifically, the ohmic contact alloy layer is located on the side of the isolation medium layer, and its bottom surface is connected to the top surface of the N+ region and the P+ region, respectively.
[0016] Specifically, the ohmic contact alloy layer is located on the side of the isolation medium layer, and its bottom surface is connected to the top surface of the N+ region and the P+ region, respectively.
[0017] Specifically, the thickness of the NN region ranges from 0.5 to 1.5 μm, and it is connected to the PP region.
[0018] Specifically, the thickness of the PP region is 0.4-1 μm.
[0019] Specifically, the bottom surface of the PP region and the bottom surface of the NN region are on the same plane.
[0020] Specifically, the depth of the N-region is greater than the depth of the trench gate oxide layer.
[0021] The N-region outside the trench gate oxide layer of this invention includes a bottom and sidewalls, which separate the gate oxide layer, thereby reducing the effect of interface states on channel electron scattering and improving channel mobility. The two structures at the bottom of the trench, namely a PP region and NN regions on both sides of the top corner, form a PN junction below the gate trench under reverse bias, transferring the maximum electric field strength in the gate oxide layer to the PN junction, effectively eliminating the possibility of the gate oxide layer being broken down by the electric field and improving device reliability. Attached Figure Description
[0022] Figure 1 This is a structural schematic diagram of step S100 of this utility model;
[0023] Figure 2 This is a structural schematic diagram of step S200 of this utility model;
[0024] Figure 3 This is a structural schematic diagram of step S300 of this utility model;
[0025] Figure 4 This is a structural schematic diagram of step S400 of this utility model;
[0026] Figure 5 This is a structural schematic diagram of step S500 of this utility model;
[0027] Figure 6 This is a structural schematic diagram of step S600 of this utility model;
[0028] Figure 7 This is a structural schematic diagram of step S700 of this utility model;
[0029] Figure 8 This is a structural schematic diagram of step S800 of this utility model;
[0030] Figure 9 This is a structural schematic diagram of step S900 of this utility model;
[0031] Figure 10 This is a structural schematic diagram of step S1000 of this utility model;
[0032] Figure 11 This is a structural schematic diagram of step S1100 of this utility model;
[0033] Figure 12 This is a structural schematic diagram of step S1200 of this utility model;
[0034] Figure 13 This is a structural schematic diagram of step S1300 of this utility model;
[0035] Figure 14 This is a structural schematic diagram of step S1400 of this utility model;
[0036] Figure 15 This is a structural schematic diagram of step S1500 of this utility model;
[0037] Figure 16 This is a structural schematic diagram of step S1600 of this utility model;
[0038] In the figure, 1 is the N+ substrate, 2 is the N- drift region, 3 is the NN region, 4 is the PP region, 5 is the N- epitaxial layer, 6 is the trench region, 7 is the PW region, 8 is the N+ region, 9 is the P+ region, 10 is the N- region, 11 is the gate oxide layer, 12 is the poly layer, 13 is the isolation dielectric layer, 14 is the ohmic contact alloy layer, 15 is the source metal layer, and 16 is the drain metal layer. Detailed Implementation
[0039] The present invention will now be described in detail with reference to specific practical examples. Examples of the embodiments are shown in the accompanying drawings. The illustrative embodiments and descriptions of the present invention are for explaining the present invention only and are not intended to limit the present invention.
[0040] S100, refer to Figure 1As shown, an N- drift layer 2 is epitaxially grown on an N+ substrate 1;
[0041] S200, refer to Figure 2 As shown, an N-epitaxial layer is epitaxially grown on the N-drift layer 2;
[0042] S300, refer to Figure 3 As shown, a pair of NN regions 3 are formed on the N-epitaxial layer by etching;
[0043] In step S300, a pair of NN regions 3 are formed through epitaxial growth and etching processes, with a doping concentration of 5E16-5E17 cm⁻¹. -2 The thickness ranges from 0.5 to 1.5 μm to cover the bottom corners of the trench area.
[0044] S400, refer to Figure 4 As shown, a PP region 4 located between a pair of NN regions 3 is formed on the N-drift layer 2 by Al ion implantation;
[0045] In step S400, the thickness of PP region 4 ranges from 0.4 to 1 μm, and the doping concentration is 1E17-5E18 cm⁻¹. -2 The bottom surface of PP region 4 is flush with the bottom surface of NN region 3, wrapping the bottom of groove region 6 to reduce electric field concentration.
[0046] S500, refer to Figure 5 As shown, an N-epitaxial layer 5 is epitaxially grown on the N-drift layer 2;
[0047] S600, refer to Figure 6 As shown, trench region 6 is formed on N-epitaxial layer 5 by trench etching;
[0048] S700, reference Figure 7 As shown, a PW region 7 is formed on the N-epitaxial layer 5 by Al ion implantation;
[0049] In step S700, ion implantation forms PW region 7 in N-epitaxy layer 5, with a doping concentration of 1E12-1E14 cm⁻².
[0050] S800, see reference Figure 8 As shown, an N+ region 8 is formed on the N-epilayer 5 by N-ion implantation;
[0051] S900, refer to Figure 9 As shown, P+ region 9 is formed on the top surface of N+ region 8 by Al ion implantation;
[0052] S1000, refer to Figure 10 As shown, N-region 10 is formed in trench region 6 by N-ion implantation and etching;
[0053] In step S1000, the N-region 10 doping concentration is 1E14-6E14cm. -2 The depth of N-region 10 is greater than the depth of trench gate oxide layer 11. The bottom of trench region 6 is inside PW region 7 and is interconnected with N+ region 8 and P+ region 9.
[0054] S1100, refer to Figure 11 As shown, a gate oxide layer 11 is formed in the trench region 6 by high-temperature deposition and oxidation growth;
[0055] S1200, refer to Figure 12 As shown, a poly layer 12 is formed in the trench region 6 by deposition of polysilicon, which is used as a gate electrode lead-out;
[0056] S1300, refer to Figure 13 As shown, an isolation dielectric layer 13 is formed by depositing oxide on the N-epitaxial layer 5 and the trench region 6 to serve as isolation between the device gate and source;
[0057] S1400, refer to Figure 14 As shown, a metal layer for ohmic contact is formed on the N-epitaxial layer 5 by metal sputtering. After sputtering, high-temperature annealing is used to improve lattice defects and alloy the front sputtered metal with SiC to form an ohmic contact alloy layer 14.
[0058] S1500, refer to Figure 15 As shown, a source metal layer 15 is formed on top of the isolation dielectric layer 13 and the ohmic contact alloy layer 14 by a metal sputtering process. The bottom of the source metal layer 15 is connected to the ohmic contact alloy layer 14 and the isolation dielectric layer 13 respectively, and is used as a source electrode lead-out.
[0059] S1600, refer to Figure 16 As shown, a drain metal layer 16 is formed under the N+ substrate 1 by metal sputtering and back-side thinning processes, and is led out by a drain electrode.
[0060] A silicon carbide MOSFET device includes, from bottom to top, a drain metal layer 16, an N+ substrate layer 1, an N-drift layer 2, an N-epipolar layer 5, a PW region 7, an N+ region 8, an ohmic contact alloy layer 14, and a source metal layer 15.
[0061] The N-epipolar layer 5 is provided with:
[0062] NN region 3 is provided with a pair of regions, which are spaced apart within the N-epipolar layer 5;
[0063] PP region 4 is disposed between a pair of NN regions 3, and the bottom surfaces of PP region 4 and NN region 3 are on the same plane;
[0064] P+ region 9 extends downward from the top surface of N+ region 8 into PW region 7, and is spaced apart from the bottom surface of PW region 7.
[0065] N-region 10 has a U-shaped cross-section, extending downward from the top surface of N+region 8 to the top surface of PP region 4, and its side is connected to NN region 3;
[0066] The gate oxide layer 11 has a U-shaped cross-section and extends downward along the inner sidewall of the N-region 10;
[0067] Poly layer 12 is disposed within the gate oxide layer 11, and its top surface is flush with the top surface of the gate oxide layer 11 and the top surface of the N-region 10, respectively.
[0068] An isolation dielectric layer 13 is provided on the top surface of the N+ region 8, N- region 10, gate oxide layer 11 and Poly layer 12.
[0069] The ohmic contact alloy layer 14 is located on the side of the isolation medium layer 13, and its bottom surface is connected to the top surface of the N+ region 8 and the P+ region 9, respectively.
[0070] In this case, the top surface of the ohmic contact alloy layer 14 is located below the insulating dielectric layer 13.
[0071] The bottom surface of the source metal layer 15 is connected to the ohmic contact alloy layer 14 and the isolation dielectric layer 13, respectively.
[0072] This invention forms a PN junction between the electric field confinement structure of the bottom PP region 4 of the trench region 6 and the N-drift region 2. The depletion layer of the PN junction reduces the electric field intensity in the oxide layer at the bottom of the gate trench to the level of a normal planar structure, thereby avoiding gate electric field concentration and improving device reliability.
[0073] The low-doped N-type SiC on the sidewalls of the gate trench effectively reduces the scattering effect of the SiC-SiO2 interface states on the channel electrons, improves electron mobility, and reduces the on-resistance of the device; at the same time, the P+ electric field confinement structure in the bottom region of the trench reduces the electric field strength applied to the gate trench oxide layer.
[0074] Regarding the information disclosed in this case, the following points need to be clarified:
[0075] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.
[0076] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;
[0077] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A silicon carbide MOSFET device, characterized in that, It includes, from bottom to top, a drain metal layer (16), an N+ substrate layer (1), an N- drift layer (2), an N- epitaxial layer (5), a PW region (7), an N+ region (8), an ohmic contact alloy layer (14), and a source metal layer (15). The N-epipolar layer (5) is provided with: The NN region (3) is provided with a pair of regions, which are spaced apart within the N-epipolar layer (5); PP region (4) is located between a pair of NN regions (3), and its bottom surface is on the same plane as the bottom surface of NN region (3); The P+ region (9) extends downward from the top surface of the N+ region (8) into the PW region (7); N-region (10) has a U-shaped cross-section and extends downward from the top surface of N+region (8) to the top surface of PP region (4); The gate oxide layer (11) has a U-shaped cross-section and extends downward along the inner sidewall of the N-region (10); A poly layer (12) is disposed within the gate oxide layer (11); The top surfaces of the N+ region (8), N- region (10), gate oxide layer (11) and Poly layer (12) are provided with an isolation dielectric layer (13).
2. The silicon carbide MOSFET device according to claim 1, characterized in that, The ohmic contact alloy layer (14) is located on the side of the isolation medium layer (13), and its bottom surface is connected to the top surface of the N+ region (8) and the P+ region (9), respectively.
3. A silicon carbide MOSFET device according to claim 1, characterized in that, The thickness of the NN region (3) ranges from 0.5 to 1.5 μm and is connected to the PP region (4).
4. A silicon carbide MOSFET device according to claim 1, characterized in that, The thickness of the PP region (4) is 0.4-1 μm.
5. A silicon carbide MOSFET device according to claim 1, characterized in that, The bottom surface of the PP region (4) and the bottom surface of the NN region (3) are on the same plane.
6. A silicon carbide MOSFET device according to claim 1, characterized in that, The depth of the N-region (10) is greater than the depth of the trench gate oxide layer (11).