LSI chip packaging structure
By designing low-density and high-density metal pillar groups and electrically connecting the redistribution metal layers, the problem of the inability to reduce the diameter and spacing of copper pillars in LSI chip packaging was solved, achieving ultra-thinness and performance improvement, while reducing production costs.
Patent Information
- Application Number
- CN202423296376.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-31
AI Technical Summary
In existing LSI chip packaging processes, the bridging chip cannot be thinned a second time, which prevents the diameter and spacing of the copper pillars from being reduced, hindering the improvement of product performance. At the same time, the temporary bonding and debonding process of the glass carrier is costly.
By employing a design of low-density and high-density metal pillar groups, and through thinning of the molding compound, combined with the electrical connection of the redistribution metal layer, the diameter of the copper pillars is reduced to 50 micrometers and the spacing is reduced to 100 micrometers. Through the electrical connection of the SOC and HBM chips, a multi-density integrated packaging structure is formed.
This achievement enables ultra-thin LSI chip packaging structures, improves electrical performance, reduces production costs, and meets the needs of product performance and design diversity.
Smart Images
Figure CN223680104U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of LSI chip packaging structures, belong to semiconductor packaging technical field. BACKGROUND
[0002] LSI is a kind of saying of Bridge Die. In the forming process of the existing LSI chip Bridge Die (Si bridge Die), the thickness of Bridge Die (Si bridge Die) is 50 microns~80 microns, affected by thinning, dicing process, again through the patch process to be pasted on temporary glass carrier, Bridge Die cannot be thinned twice in chip packaging process. The copper column on LSI chip is operated in the mode of copper column planting. Because LSI Bridge Die cannot be thinned twice, the copper column diameter range of current product in the industry is 60 microns to 80 microns, the pitch range is 110 microns to 140 microns, cannot form high-density layout of copper column (the diameter of copper column needs to be reduced to 50 microns, and the minimum pitch needs to be reduced to 100 microns), which hinders the market demand development of product performance. At the same time, the temporary bonding and debonding process (TB / DB process) of glass carrier uses very expensive equipment and materials, so the production cost is very high. SUMMARY
[0003] In order to overcome the shortcomings of the existing packaging process, the utility model provides a kind of LSI chip packaging structure to reduce the thickness of packaging structure and improve product performance.
[0004] The technical scheme of the utility model is as follows:
[0005] The utility model provides a kind of LSI chip packaging structure, it includes even number LSI chip body, low density metal column group, high density metal column group, first rewiring metal layer and second rewiring metal layer;
[0006] The low density metal column group is arranged at the outer side area of LSI chip body, and the low density metal column group is composed of a plurality of first metal columns, is arrayed distribution, and is parallel with LSI chip lower metal column respectively;
[0007] The high density metal column group is arranged at the inner side area of adjacent two LSI chip bodies, and the high density metal column group is composed of a plurality of second metal columns, is arrayed distribution, and is parallel with LSI chip lower metal column respectively;
[0008] The diameter range of the second metal column is less than the diameter range of the first metal column, and the pitch range of the second metal column is less than the pitch range of the first metal column;
[0009] The encapsulating material encapsulates the LSI chip body, the LSI chip lower metal column, the low-density metal column group and the high-density metal column group to form a plastic encapsulating body, and the front surface and the back surface of the plastic encapsulating body are both parallelly thinned to expose only the upper and lower ends of the first metal column, the upper and lower ends of the second metal column, the back surface of the LSI chip body and the outer end surface of the LSI chip lower metal column;
[0010] The first re-wiring metal layer is arranged on the front surface of the plastic encapsulating body, is electrically connected with the first metal column, the second metal column and the LSI chip lower metal column, and is provided with a first signal port;
[0011] The second re-wiring metal layer is arranged on the back surface of the plastic encapsulating body, is electrically connected with the first metal column, the second metal column and the back surface of the LSI chip body, and is provided with a second signal port.
[0012] As an implementable mode, the number of the LSI chip bodies is greater than or equal to 2.
[0013] As an implementable mode, the diameter of the second metal column of the high-density metal column group ranges from 50 microns to 60 microns, and the interval ranges from 100 microns to 110 microns.
[0014] As an implementable mode, the diameter of the first metal column of the low-density metal column group ranges from 60 microns to 80 microns, and the interval ranges from 110 microns to 140 microns.
[0015] As an implementable mode, the LSI chip packaging structure further comprises a plurality of SOC chips and a plurality of HBM chips, the SOC chips are distributed in the center, the HBM chips are distributed around the SOC chips, the SOC chips are electrically connected with all the LSI chip bodies through the first re-wiring metal layer and are electrically connected with the second re-wiring metal layer through the high-density metal column group, and the HBM chips are selectively electrically connected with the LSI chip bodies through the first re-wiring metal layer and are selectively electrically connected with the low-density metal column group and the second re-wiring metal layer.
[0016] Beneficial effects
[0017] The LSI chip packaging structure provided by the utility model further reduces the thickness of the LSI chip packaging structure to a target thickness, achieves the target of an ultra-thin LSI structure, and reduces the height of the low-density metal column group and the high-density metal column group on the side, so that the corresponding electrical performance is improved (because a shorter metal column height means smaller loss).
[0018] The high-density Cu Post structure of the LSI chip packaging structure can reduce the diameter of the metal column to 50 microns and the minimum interval to 100 microns, and improves the product performance.
[0019] The LSI chip packaging structure of the utility model provides a design structure of multiple metal column structure density integrated, satisfies the design demand of product multidirectional. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 It is the schematic diagram of prior art LSI chip packaging structure;
[0021] Figure 2 It is the sectional view of a kind of LSI chip packaging structure of the utility model;
[0022] Figure 3 It is Figure 2 the sectional view of further packaging structure of
[0023] Figure 4 It is Figure 3 the top view schematic diagram of
[0024] Among them, LSI chip body 101
[0025] LSI chip body front surface 110
[0026] LSI chip body back surface 130
[0027] LSI chip body 111
[0028] LSI chip lower metal column 121
[0029] LSI chip lower metal column outer end surface 123
[0030] Low-density metal column group 210
[0031] First metal column first end surface 211
[0032] First metal column second end surface 213
[0033] High-density metal column group 230
[0034] Second metal column first end surface 231
[0035] Second metal column second end surface 233
[0036] Plastic package 301
[0037] Plastic package front surface 310
[0038] Plastic package back surface 330
[0039] First rewiring metal layer 510
[0040] First signal port 511
[0041] Second rewiring metal layer 530
[0042] Second signal port 531
[0043] SOC chip 610
[0044] HBM chip 630. DETAILED DESCRIPTION
[0045] The application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related utility model, and not limit the utility model. In addition, it should be noted that, for the convenience of description, only the parts related to the utility model are shown in the drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0046] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the specific embodiments of the utility model will be described in detail below with reference to the drawings.
[0047] The utility model provides a kind of LSI chip packaging structure, as shown in Figures 2 to 4 It includes even number of LSI chip body 101, low-density metal column group 210 and high-density metal column group 230, and first rewiring metal layer 510 and second rewiring metal layer 530. The number of LSI chip body 101 is ≥2. LSI chip body 101 includes LSI chip body front 110 and the LSI chip body back 130 opposite to it, and LSI chip lower metal column 121 is arranged on LSI chip body front 110. Figure 4 Four LSI chip bodies 101 are packaged in the figure, and are arrayed. After the overall thinning process of LSI chip body 101, the ultra-thin LSI structure target of 40 microns is achieved.
[0048] Low-density metal column group 210 is arranged in the outer region of LSI chip body 101, and low-density metal column group 210 is composed of a plurality of first metal columns, is arrayed, and is distributed in parallel with LSI chip lower metal column 121. The two end faces of each first metal column are first metal column first end face 211 and first metal column second end face 213 respectively.
[0049] The high-density metal column group 230 is arranged in the inner region of two adjacent LSI chip bodies 101, and is composed of a plurality of second metal columns arranged in an array and parallel to the LSI chip lower metal columns 121. The diameter of the second metal column is smaller than that of the first metal column, and the interval of the second metal column is smaller than that of the first metal column. Each second metal column has a first end surface 231 and a second end surface 233. In this embodiment, the first metal column has a diameter of 60-80 microns and an interval of 110-140 microns, and the second metal column has a diameter of 50-60 microns and an interval of 100-110 microns, so as to reduce loss and enhance the efficiency of the via.
[0050] The encapsulating material encapsulates the LSI chip body 101, the high-density metal column group 230 and the low-density metal column group 210 to form a plastic encapsulation body 301. The front surface and the back surface of the plastic encapsulation body 301 are parallelly thinned. The back surface of the plastic encapsulation body 301 exposes the back surface 130 of the LSI chip body, the first end surface 213 of the first metal column of the low-density metal column group 210 and the second end surface 233 of the second metal column of the high-density metal column group 230. The front surface of the plastic encapsulation body 301 exposes the outer end surface 123 of the LSI chip lower metal column, the first end surface 211 of the first metal column of the low-density metal column group 210 and the first end surface 231 of the second metal column of the high-density metal column group 230.
[0051] The first re-wiring metal layer 510 is arranged on the front surface of the plastic encapsulation body 301, and includes a plurality of metal layers and dielectric layers. The dielectric layers are provided with dielectric layer openings, and the metal layers above and below are electrically connected through the dielectric layer openings. Figure 2 The metal layer is electrically connected with the first end surface 211 of the first metal column, the first end surface 231 of the second metal column and the outer end surface 123 of the LSI chip lower metal column. The outermost layer of the first re-wiring metal layer 510 is a dielectric layer, and is provided with a first signal port 511. The first signal port 511 specifically includes a signal terminal array, a pad or an opening, etc. The skilled in the art can select the module according to the need, and the specific limitation is not made. Figure 2 The pad is used to selectively and fixedly connect the functional chip with the pad through the lower metal column of the chip. The functional chip is encapsulated by the encapsulating material, and only the back surface of the functional chip is exposed. Figure 3 and Figure 4The three functional chips are inverted. The central chip is a SOC chip 610, which is provided with a metal column under the chip. Four HBM chips 630 are distributed around the SOC chip 610, which is provided with a metal column under the chip. The SOC chip 610 is electrically connected with all LSI chip bodies 101 through the first redistribution metal layer 510 and is electrically connected with the second redistribution metal layer 530 through the high-density metal column group 230. The HBM chip 630 is selectively electrically connected with the LSI chip body 101 through the first redistribution metal layer 510 and is selectively electrically connected with the low-density metal column group 210 and the second redistribution metal layer 530.
[0052] The second redistribution metal layer 530 is arranged on the back of the plastic package 301 and includes a plurality of metal layers and dielectric layers. The dielectric layers are provided with dielectric layer openings, and the metal layers arranged above and below are electrically connected through the dielectric layer openings. Figure 2 The second redistribution metal layer 530 is arranged on the back of the plastic package 301 and includes a plurality of metal layers and dielectric layers. The dielectric layers are provided with dielectric layer openings, and the metal layers arranged above and below are electrically connected through the dielectric layer openings.
[0053] The metal layer of the second redistribution metal layer 530 is electrically connected with the first metal column second end surface 213, the second metal column second end surface 233 and the back of the LSI chip body 130. The outermost layer of the second redistribution metal layer 530 is a dielectric layer and is provided with a second signal port 531 (not shown in the figure). Specifically, the second signal port 531 specifically includes a signal terminal array, a pad or an opening, etc. Those skilled in the art can select according to the modules to be connected, and no specific limitation is made. Figure 3 The second redistribution metal layer 530 is arranged on the back of the plastic package 301 and includes a plurality of metal layers and dielectric layers. The dielectric layers are provided with dielectric layer openings, and the metal layers arranged above and below are electrically connected through the dielectric layer openings.
[0054] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any changes or replacements that can be easily thought of by those skilled in the art within the technical range disclosed in the embodiments of the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. An LSI chip packaging structure, comprising an even number of LSI chip bodies (101), the LSI chip bodies (101) comprising LSI chip body front faces (110) and LSI chip body back faces (130) opposite thereto, the LSI chip body front faces (110) being provided with LSI chip lower metal pillars (121); characterized in that further comprising a low-density metal pillar group (210), a high-density metal pillar group (230), a first re-wiring metal layer (510) and a second re-wiring metal layer (530); the low-density metal pillar group (210) being arranged at an outer region of the LSI chip bodies (101), the low-density metal pillar group (210) being composed of a plurality of first metal pillars arranged in an array and parallel to the LSI chip lower metal pillars (121) respectively; the high-density metal pillar group (230) being arranged at an inner region of two adjacent LSI chip bodies (101), the high-density metal pillar group (230) being composed of a plurality of second metal pillars arranged in an array and parallel to the LSI chip lower metal pillars (121) respectively; the second metal pillars having a diameter range < the first metal pillars and a pitch range < the first metal pillars; an encapsulating material encapsulating the LSI chip bodies (101), the LSI chip lower metal pillars (121), the low-density metal pillar group (210) and the high-density metal pillar group (230) to form a plastic encapsulation body (301), the plastic encapsulation body (301) being parallelly thinned at its front face and back face, exposing only the upper and lower ends of the first metal pillars, the upper and lower ends of the second metal pillars, the back faces of the LSI chip bodies (101) and the outer end faces (123) of the LSI chip lower metal pillars; the first re-wiring metal layer (510) being arranged at the front face of the plastic encapsulation body (301) and electrically connected to the first metal pillars, the second metal pillars and the LSI chip lower metal pillars (121), and being provided with a first signal port (511); the second re-wiring metal layer (530) being arranged at the back face of the plastic encapsulation body (301) and electrically connected to the first metal pillars, the second metal pillars and the LSI chip body back faces (130), and being provided with a second signal port (531).
2. The LSI chip package structure according to claim 1, wherein The number of the LSI chip bodies (101) is ≥ 2.
3. The LSI chip package structure according to claim 1, wherein The first metal pillars of the low-density metal pillar group (210) have a diameter range of 60-80 microns and a pitch range of 110-140 microns.
4. The LSI chip package structure according to claim 1, wherein The second metal pillars of the high-density metal pillar group (230) have a diameter range of 50-60 microns and a pitch range of 100-110 microns.
5. The LSI chip package structure according to any one of claims 1 to 4, wherein It also includes a plurality of SOC chips (610) and a plurality of HBM chips (630), the SOC chips (610) are distributed in the center, the HBM chips (630) are distributed around the SOC chips (610), the SOC chips (610) are electrically connected with all LSI chip bodies (101) through the first redistribution metal layer (510), and are electrically connected with the second redistribution metal layer (530) through the high-density metal column group (230), the HBM chips (630) are selectively electrically connected with the LSI chip body (101) through the first redistribution metal layer (510), and are selectively electrically connected with the low-density metal column group (210) and the second redistribution metal layer (530).