Chip packaging structure
By setting a heat dissipation layer and thermal adhesive on the chip surface and utilizing through-silicon vias to transfer heat, the heat dissipation problem in HBM chip stacking is solved, and the thermal reliability of the chip is improved.
Patent Information
- Application Number
- CN202423029843.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-09
AI Technical Summary
Traditional HBM chip stacking processes suffer from poor heat dissipation, leading to heat buildup and affecting chip thermal reliability.
A heat dissipation layer and thermal adhesive are placed on the chip surface and connected through through-silicon vias to transfer heat from the bottom chip to the top chip and out to the outside. A heat sink and a molding compound are used in combination to enhance the heat dissipation effect.
It effectively improves the heat flux density problem of multi-layer chip stacking and enhances the thermal reliability of the chip.
Smart Images
Figure CN223680109U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of chip packaging especially relates to a chip packaging structure. BACKGROUND
[0002] High Band width Memory (HBM) is used for high-speed data transmission between a graphics processing unit (GPU) and a central processing unit (CPU). The uniqueness of HBM is mainly reflected in the stacking and interconnection. HBM vertically stacks multiple memories (DRAM) by using advanced packaging (such as through-silicon via (TSV) technology, micro bump technology), and is packaged together with the GPU through an interposer, thereby achieving high capacity, high bandwidth, low latency, and low power consumption in a small physical space.
[0003] In the HBM stacking process, some materials are usually used to protect the chips and interconnections, and to ensure the mechanical stability and electrical performance of the stacked structure. Traditional HBM uses a Thermal Compression Bonding (TC) Non-Conductive Film (NCF) process to stack, which places a layer of non-conductive adhesive film between each layer during each stacking, used to isolate the chips from each other and protect the connection points from impact.
[0004] The stacking of chips poses a great challenge to heat dissipation. There are multiple chips in a chip stacking structure, resulting in heat accumulation and a significant increase in heat flux density per unit area. If effective means are not used for heat dissipation, chip thermal reliability problems will inevitably occur.
[0005] How to improve the heat dissipation performance of the chip in the thermal compression bonding process is a problem that needs to be solved at present. SUMMARY
[0006] The technical problem to be solved by the utility model is how to improve the heat dissipation performance of the chip in the thermal compression bonding process, and a chip packaging structure is provided.
[0007] In order to solve the above problems, the utility model provides a chip packaging structure, include: base, chip stack structure is located the base surface, including the multilayer chip of stacking in turn, the chip includes upper surface and lower surface, the upper surface and lower surface all include heat dissipation area and welding area, the heat dissipation area of the upper surface of the chip between the uppermost layer chip of the chip stack structure and the base is provided with first heat dissipation layer, the heat dissipation area of the lower surface of all the chip is provided with second heat dissipation layer, the through silicon via of the heat dissipation area is connected to the first heat dissipation layer and the second heat dissipation layer, the surface of the second heat dissipation layer is provided with heat dissipation glue, and the heat dissipation glue is in contact with the first heat dissipation layer of adjacent chip, the welding area of the lower surface is provided with solder ball.
[0008] In some embodiments, the heat dissipation area is located at the center of the chip, and the welding area is located at the periphery of the heat dissipation area.
[0009] In some embodiments, the lower surface of the chip is further provided with an adhesive film, which is in the same layer as the heat dissipation glue and is provided at the periphery of the heat dissipation glue.
[0010] In some embodiments, a plurality of through silicon vias are provided in the chip, and the through silicon vias of the heat dissipation area are connected to the heat dissipation layer, and the through silicon vias of the welding area are connected to the solder ball.
[0011] In some embodiments, the chip packaging structure further comprises a plastic encapsulation layer located on the surface of the base and covering the side surface of the chip stack structure.
[0012] In some embodiments, the uppermost layer chip of the chip stack structure is exposed to the plastic encapsulation layer.
[0013] In some embodiments, a heat dissipation cover is provided above the chip stack structure, covering the chip stack structure and the plastic encapsulation layer.
[0014] In some embodiments, the heat dissipation layers on the upper and lower surfaces of the chip are of the same shape.
[0015] In some embodiments, the heat dissipation layers on the upper and lower surfaces of the chip are of different shapes.
[0016] In some embodiments, the heat dissipation layers on the lower surfaces of the plurality of chips are of different shapes.
[0017] The above technical solution can effectively improve the problem of high heat flow density of multilayer chip stacking by providing heat dissipation layers and heat dissipation glue on the surface of the chip and forming a connection through the through silicon vias of the heat dissipation area, and can improve the thermal reliability of the chip.
[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the utility model. The technology, method and equipment known to those skilled in the related art can not be discussed in detail, but under appropriate circumstances, the technology, method and equipment should be regarded as part of the authorized description. BRIEF DESCRIPTION OF DRAWINGS
[0019] In order to more clearly illustrate the technical scheme in the specific embodiment of the utility model, the drawings needed to be used in the following specific embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some specific embodiments of the utility model, and for those skilled in the art, other drawings can be obtained without creative labor on the premise of these drawings.
[0020] Figure 1 It is an embodiment of the chip packaging structure of the utility model structure schematic diagram.
[0021] Figure 2 It is another embodiment of the chip packaging structure of the utility model structure schematic diagram. SPECIFIC EMBODIMENT
[0022] The technical scheme in the embodiment of the utility model will be described clearly and completely below in combination with the drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, rather than all the embodiments. Based on the embodiment in the utility model, all other embodiments obtained by those skilled in the art without creative labor belong to the scope of the protection of the utility model.
[0023] Please refer to Figure 1 It is an embodiment of the chip packaging structure of the utility model structure schematic diagram. As Figure 1As shown, the chip packaging structure includes a substrate 11 and a chip stack structure 12. The chip stack structure 12 is located on the surface of the substrate 11 and includes a plurality of stacked chips 13. Each chip 13 includes an upper surface S1 and a lower surface S2, and each of the upper surface S1 and the lower surface S2 includes a heat dissipation region 131 and a soldering region 132. The heat dissipation region 131 of the upper surface S1 of the chip 13 between the uppermost chip of the chip stack structure 12 and the substrate 11 is provided with a first heat dissipation layer 141, and the heat dissipation region 131 of the lower surface S2 of each chip 13 is provided with a second heat dissipation layer 142. A plurality of through-silicon vias 130 are arranged in each chip 13, and the through-silicon via 130 of the heat dissipation region 131 is connected to the first heat dissipation layer 141 and the second heat dissipation layer 142. The surface of the second heat dissipation layer 142 is provided with a heat dissipation adhesive 15, and the heat dissipation adhesive 15 is in contact with the first heat dissipation layer 141 of the adjacent chip 13. The soldering region 132 of the lower surface S2 is provided with a solder ball 16.
[0024] The above technical solution can effectively improve the problem of high heat flow density of the multi-layer chip stack by arranging a heat dissipation layer and a heat dissipation adhesive on the surface of the chip and forming a connection through the through-silicon via of the heat dissipation region, and transferring the heat of the bottom chip to the upper chip and then to the outside, thereby improving the thermal reliability of the chip.
[0025] In some embodiments, the substrate 11 can be a wafer, a substrate, or a conversion board, which is used to electrically connect the chip 13 to other devices outside.
[0026] In some embodiments, the chip 13 can be obtained by separating a semiconductor substrate such as a wafer into a plurality of pieces through a die sawing process. The chip 13 can correspond to a memory chip, a logic chip (including an application-specific integrated circuit (ASIC) chip), or a system on chip (SoC). The memory chip can include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip can include a logic circuit integrated on a semiconductor substrate.
[0027] In some embodiments, the heat dissipation area 131 is located at the center of the chip 13, and the soldering area 132 is located at the periphery of the heat dissipation area 131. When the chip 13 is stacked in multiple layers, the center area of the chip 13 is more difficult to dissipate heat than the edge area. Therefore, the first heat dissipation layer 141, the second heat dissipation layer 142 and the heat dissipation glue 15 are arranged at the center of the chip 13, so as to improve the heat dissipation efficiency of the chip 13.
[0028] In some embodiments, the through silicon via 130 of the soldering area 132 is connected to the soldering ball 16.
[0029] In some embodiments, the chip packaging structure further comprises a plastic sealing layer 17 located on the surface of the substrate 11 and covering the side of the chip stacking structure 12. In this embodiment, the topmost chip 13 of the chip stacking structure 12 is exposed to the plastic sealing layer 17 to improve the heat dissipation effect. The material of the plastic sealing layer 17 is epoxy plastic sealing material (EMC), which can prevent mechanical or chemical damage to the chip 13 and ensure stable function of the chip 13. The heat dissipation glue 15 arranged in the heat dissipation area 131 at the center of the chip 13 can prevent the chip 13 from being filled with insufficient plastic sealing material.
[0030] It is worth noting that during the thermal compression bonding process, if the non-conductive adhesive film in the middle part of the chip cannot be completely extruded open, it will affect the electrical connection of the upper and lower chips. Therefore, in this embodiment, the heat dissipation glue 15 is arranged only in the heat dissipation area 131 at the center of the chip 13, and the soldering ball 16 of the soldering area 132 is exposed; the heat dissipation glue 15 can be used to preliminarily fix the upper and lower chips 13 during the stacking process of the chip 13, and the soldering ball 16 of the soldering area 132 is used for electrical connection of the upper and lower chips 13. The soldering area 132 is not provided with an adhesive film, and the soldering ball 16 is exposed, which also avoids the problem that the non-conductive adhesive film in the middle part of the chip cannot be completely extruded open in the traditional process, thereby affecting the electrical connection of the upper and lower chips.
[0031] In this embodiment, the first heat dissipation layer 141 and the second heat dissipation layer 142 of the same chip 13 have the same shape, which can reduce the complexity of the manufacturing process, improve the production efficiency and reduce the process cost. In this embodiment, the first heat dissipation layer 141 and the second heat dissipation layer 142 of the chip 13 are both in the shape of a column, and the cross-sectional shape is rectangular.
[0032] In order to further improve the heat dissipation effect, in some embodiments, a heat dissipation cover 18 is arranged above the chip stacking structure 12, which covers the chip stacking structure 12 and the plastic sealing layer 17. The heat dissipation cover 18 has a large area, which can sufficiently dissipate heat for the chip stacking structure 12.
[0033] Referring to Figure 2 , which is a structural schematic diagram of another embodiment of the chip packaging structure. Figure 2 The embodiments shown are different from Figure 1 The first heat dissipation layer 241 and the second heat dissipation layer 242 of the same chip 23 are different in shape. Taking chip 238 as an example, the shape of the second heat dissipation layer 242 of the chip 238 is a ring-shaped column, and the cross section is two rectangles separated from each other. In other chips 23, the second heat dissipation layer 242 can also be a column with a relatively thick thickness. Taking chip 239 as an example, the shape of the first heat dissipation layer 241 of the chip 239 is a column, and the cross section is a rectangle; the shape of the second heat dissipation layer 242 of the chip 239 is a cone, and the cross section is a triangle. The second heat dissipation layer 242 in the form of a cone provides a larger surface area, which can further improve the heat dissipation effect.
[0034] In addition, the second heat dissipation layer 242 with a different shape from the first heat dissipation layer 241 is arranged on the lower surface S2 of the chip 23, and the second heat dissipation layer 242 is in contact with the first heat dissipation layer 241 on the upper surface S1 of the lower chip, so as to better provide support force and heat dissipation performance.
[0035] In some embodiments, the shapes of the second heat dissipation layers 242 of the lower surfaces S2 of the plurality of chips 23 can be arranged to be the same, for example, the shapes of the first heat dissipation layers 241 of the upper surfaces S1 of the plurality of chips 23 are all columns, and the shapes of the second heat dissipation layers 242 of the lower surfaces S2 of the plurality of chips 23 are all cones, so as to reduce the complexity of the manufacturing process.
[0036] In some embodiments, the shapes of the second heat dissipation layers 242 of the lower surfaces S2 of the plurality of chips 23 can be arranged to be different.
[0037] In some embodiments, the lower surface S2 of the chip 23 is further provided with an adhesive film 29, which is in the same layer as the heat dissipation glue 25 and is arranged at the periphery of the heat dissipation glue 25. The adhesive film 29 is a non-conductive adhesive film, which is used to isolate the chips 23 from each other and protect the solder balls 26, so as to prevent collapse and adhesion, which may cause short circuit. The combination of the heat dissipation glue 25 and the adhesive film 29 can ensure heat dissipation while filling the upper and lower chips completely, so as to ensure the stability of the packaging structure.
[0038] The above technical scheme can effectively improve the problem of high heat flux density of multi-layer chip stacking by arranging heat dissipation layers and heat dissipation glue on the surface of the chip and forming a connection through the through silicon via of the heat dissipation area, and can improve the thermal reliability of the chip.
[0039] It should be noted that reference to "an embodiment", "one embodiment", "an example embodiment", "some embodiments", etc., in the specification indicates that a described embodiment can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of those in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0040] Generally, the scope of a term is to be understood commensurate with the term's scope as ordinarily used in the relevant art. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics in the plural. Similarly, terms, such as "a", "an", or "the", again, depending at least in part upon context, can be understood to take either the singular or plural sense - some examples of which follow. For example, "a" or "an" can be understood to mean one or more; "the first" can be understood to mean one or more, or one particular item; "the last" can be understood to mean one or more, or one particular item; "an amount" can be understood to mean one or more instances of an amount; "one" can be understood to mean one, or one instance of the item; "another" can be understood to mean one or more, or one or more instances of the item; "at least one" can be understood to mean one or more; "one or more" can be understood to mean one or more; and "one or the other" can be understood to mean at least one, or at least one instance of the items. In addition, it will be noted that, where appropriate, singular forms of terms are intended to include the plural forms of the terms and vice versa. Furthermore, to the extent that the terms "includes", "containing", "having", "with", and variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as an open transition term without precluding any additional or
[0041] It should be noted that the terms "comprises", "comprising", "includes", "including", "has", "having", "contains", "containing", and variants thereof, when used in this description and in the claims, are intended to specify the presence of stated features, structures, or characteristics, but do not preclude the presence or addition of one or more other features, structures, or characteristics. It should also be noted that, as used in this description and the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Furthermore, to the extent that the terms "first", "second", etc. are used in this description and the claims, such terms are used to distinguish one element from another, but do not require or imply these elements to be in a particular sequence or order. In addition, terms such as "coupled" and "connected" and variants thereof, mean any direct or indirect communication between entities, which can be interpreted in a firing sense or a software / electrical sense, not necessarily meaning direct physical or mechanical contact between entities. In addition, the terms "coupled" and "connected" and variants thereof are used synonymously with each other in the present disclosure.
[0042] The preferred embodiments of the present application have been disclosed with reference to the drawings and detailed description. It should be understood that various modifications, additions, and substitutions can be made to the embodiments disclosed herein without departing from the spirit and scope of the present application. Accordingly, the present application is not limited to the embodiments disclosed herein but is intended to cover all modifications, additions, and substitutions falling within the scope and spirit of the present application.
Claims
1. A chip packaging structure, characterized in that, include: Base; A chip stacking structure, located on the surface of the substrate, comprises multiple layers of chips stacked sequentially; The chip includes an upper surface and a lower surface, both of which include a heat dissipation area and a soldering area. The heat dissipation area on the upper surface of the chip between the topmost chip and the substrate is provided with a first heat dissipation layer, and the heat dissipation area on the lower surface of all the chips is provided with a second heat dissipation layer. The chip has a plurality of through-silicon vias that penetrate the chip, and the through-silicon vias in the heat dissipation area are connected to the first heat dissipation layer and the second heat dissipation layer. The surface of the second heat dissipation layer is provided with thermal adhesive, and the thermal adhesive is in contact with the first heat dissipation layer of the adjacent chip; The welding area on the lower surface is provided with welding balls.
2. The chip packaging structure according to claim 1, characterized in that, The heat dissipation area is located at the center of the chip, and the soldering area is located around the heat dissipation area.
3. The chip packaging structure according to claim 2, characterized in that, An adhesive film is also provided on the lower surface of the chip. The adhesive film is in the same layer as the thermal adhesive and is disposed around the thermal adhesive.
4. The chip packaging structure according to claim 1, characterized in that, The through-silicon via in the welding area is connected to the solder ball.
5. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes a molding layer located on the surface of the substrate and covering the sides of the chip stack structure.
6. The chip packaging structure according to claim 5, characterized in that, The topmost chip in the chip stack structure is exposed to the molding compound.
7. The chip packaging structure according to claim 5, characterized in that, A heat dissipation cover is provided on top of the chip stack structure, and the heat dissipation cover covers the chip stack structure and the molding layer.
8. The chip packaging structure according to claim 1, characterized in that, The first heat dissipation layer and the second heat dissipation layer of the same chip have the same shape.
9. The chip packaging structure according to claim 1, characterized in that, The first heat dissipation layer and the second heat dissipation layer of the same chip have different shapes.
10. The chip packaging structure according to claim 9, characterized in that, The second heat dissipation layer of the multiple chips has a different shape.