Voltage sampling circuit, voltage sampling system and vehicle

Abstract

The utility model relates to a voltage sampling circuit, a voltage sampling system and a vehicle, and relates to the technical field of voltage sampling. The voltage sampling circuit comprises an analog front-end chip and a voltage acquisition circuit; wherein the analog front-end chip comprises a first pin and a second pin; the first pin and / or the second pin are / is connected with a voltage sampling point through the voltage acquisition circuit, the first pin is used for acquiring an analog signal, and the second pin is a universal pin on the analog front-end chip. By using the voltage sampling circuit, the voltage sampling system and the vehicle provided by the invention, the voltage sampling of the voltage sampling point can be realized on the basis of reducing the hardware cost.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of voltage sampling, and particularly relates to a voltage sampling circuit, a voltage sampling system and a vehicle. BACKGROUND

[0002] At present, there are some voltage sampling points in the high-voltage loop of the battery system of an electric vehicle, which can be sampled by an analog front-end chip. However, when the number of voltage sampling points that need to be sampled is large, a host device (Battery Management System, BMS) is additionally arranged to sample the voltage, and the voltage is returned to a main controller (Microcontroller Unit, MCU) through a daisy chain communication, and the voltage difference between the voltage sampling points is determined by the main controller. The voltage of the voltage sampling point is collected by the additionally configured host device, which brings additional hardware cost. CONTENT OF THE UTILITY MODEL

[0003] To overcome the problems in the prior art, the present disclosure provides a voltage sampling circuit, a voltage sampling system and a vehicle.

[0004] According to a first aspect of an embodiment of the present disclosure, a voltage sampling circuit is provided, which comprises an analog front-end chip and a voltage collection circuit; wherein,

[0005] The analog front-end chip comprises a first pin and a second pin; the first pin and / or the second pin is connected to a voltage sampling point through the voltage collection circuit, the first pin is used to collect an analog signal, and the second pin is a general pin on the analog front-end chip.

[0006] Optionally, the voltage sampling point comprises a relay; the first pin and / or the second pin is connected to the relay through the voltage collection circuit.

[0007] Optionally, the voltage sampling circuit further comprises a third resistor;

[0008] The first pin and / or the second pin is connected to the voltage collection circuit through the third resistor.

[0009] Optionally, the voltage sampling point further comprises a battery cell; adjacent two first pins on the analog front-end chip are connected to the positive and negative electrodes of the battery cell, respectively.

[0010] Optionally, adjacent two first pins on the analog front-end chip are connected to the positive and negative electrodes of the battery cell through fourth resistors, respectively.

[0011] Optionally, the voltage collection circuit comprises a first resistor and a second resistor;

[0012] a first end of the first resistor is connected with a first end of the voltage sampling point, a second end of the first resistor is connected with a first end of the second resistor, a second end of the second resistor is grounded, and a second end of the voltage sampling point is grounded;

[0013] the first pin and / or the second pin is connected on a connection point of the first resistor and the second resistor.

[0014] Optionally, the second end of the voltage sampling point is grounded through at least one battery cell.

[0015] Optionally, the first pin is a VCN pin, and the second pin is a GPIO pin.

[0016] According to a second aspect of the embodiments of the present disclosure, a voltage sampling system is provided, comprising the voltage sampling circuit provided by the first aspect of the embodiments of the present disclosure, and the voltage sampling circuit is connected with a voltage sampling point

[0017] According to a third aspect of the embodiments of the present disclosure, a vehicle is provided, and the vehicle is configured with the voltage sampling system provided by the second aspect of the embodiments of the present disclosure.

[0018] The technical solutions provided by the embodiments of the present disclosure can include the following beneficial effects:

[0019] The embodiments of the present disclosure cancel the configuration of the host device, which collects the voltage of the voltage sampling point through the first pin and / or the second pin in the existing analog front-end chip, for example, collects the voltage of the voltage sampling point through the first pin and / or the second pin, so that the voltage collection of the voltage sampling point can be realized without additional configuration of the host device, and the hardware cost is reduced.

[0020] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0022] Figure 1 is a schematic diagram of communication between an analog front-end chip and a battery management unit according to an exemplary embodiment.

[0023] Figure 2 is a schematic diagram of an analog front-end chip collecting the voltage of a voltage sampling point by a host device according to an exemplary embodiment.

[0024] Figure 3is a circuit diagram of a first pin collecting voltage of a voltage sampling point according to an example embodiment.

[0025] Figure 4 is a circuit diagram of a first pin collecting voltage of a voltage sampling point according to an example embodiment.

[0026] Figure 5 is a circuit diagram of a second pin collecting voltage of a voltage sampling point according to an example embodiment.

[0027] Figure 6 is a circuit diagram of a second pin collecting voltage of a voltage sampling point according to an example embodiment.

[0028] Figure 7 is a block diagram of a vehicle according to an example embodiment.

[0029] Figure 8 is a block diagram of a chip system according to an example embodiment. DETAILED DESCRIPTION

[0030] The example embodiments will be described in detail herein with reference to the attached drawings. In the following description, same numbers refer to same elements in all figures. The following detailed description includes specific details for the purpose of providing a thorough understanding of the example embodiments. However, it will be apparent to those skilled in the art that the example embodiments can be practiced without these specific details. In some instances, well-known structures and components are not described in detail in order to avoid obscuring the example embodiments.

[0031] It should be noted that all the actions of obtaining signals, information or data in the present disclosure are carried out in compliance with the corresponding data protection regulations and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0032] Figure 5 is a voltage sampling circuit according to an example embodiment, as shown in Figure 5 The voltage sampling circuit includes an analog front end chip and a voltage collection circuit.

[0033] The analog front end chip can be an Analog Front End (AFE). The analog front end chip is applied in a battery management system, which can be used to collect battery information such as battery voltage, current and temperature, convert the collected battery information from an analog signal to a digital signal, and transmit the digital signal of the battery information to a main controller to participate in the calculation of parameters such as State of Charge (SOC), State of Health (SOH) and State of Power (SOP).

[0034] In the battery management system, the analog front-end chip has at least one, please refer to Figure 5 shown, which has AFEn~AFEm and so on multiple analog front-end chip. The analog front-end chip is configured with a variety of functions of the pin, the analog front-end chip is configured with the first pin and the second pin, the first pin is used to collect analog signal, for example, the first pin can be VCN pin, the second pin is a general pin on the analog front-end chip, for example, the second pin can be GPIO (General-Purpose Input / Output Ports, general input / output) pin, the first pin and / or the second pin is connected with the voltage sampling point through the voltage acquisition circuit.

[0035] Among them, please refer to Figure 1 shown, at least one analog front-end chip transmits voltage to the main controller through the communication bridge, and the main controller is arranged in the battery management unit (BMU).

[0036] Among them, the voltage sampling circuit is a separation circuit between the pin on the analog front-end chip and the voltage sampling point, which is used to avoid the voltage generated by the voltage sampling point from breaking through the pin on the analog front-end chip.

[0037] Among them, the voltage sampling point has various forms, which can be the battery cell in the battery, or the relay in the battery management system. Please refer to Figure 3 and Figure 5 shown, the voltage sampling point includes V0~V8 and so on multiple voltage sampling points, by collecting the voltage of these voltage sampling points, the voltage state of the battery cell and the relay and so on can be obtained. Among them, Figure 3 and Figure 5 x in the voltage sampling point Vx in

[0038] The vehicle is configured with at least one battery, for example, please refer to Figure 5 shown, which includes the first battery BANK1 and the second battery BANK2, which provides power source for vehicle driving, vehicle load and so on through at least one battery; and each battery includes at least one cell, for example, please refer to Figure 5 shown, the first battery BANK1 includes BANK1_CELLn to BANK1_CELLn+m and so on multiple cells, and the second battery BANK2 includes BANK2_CELLn to BANK2_CELLn+m and so on multiple cells.

[0039] A relay is the main switch (Main) in the high-voltage circuit of a vehicle battery system, ensuring the power-on and safe disconnection of the high-voltage circuit. Relays include the main positive relay Main+, the main negative relay Main-, and the high-voltage relay. The main positive relay Main+ connects the battery's positive terminal to the positive terminal of an external load or charging station; the main negative relay Main- connects the battery's negative terminal to the negative terminal of an external load or charging station; the high-voltage relay (not shown in the diagram) provides high-voltage isolation for the high-voltage circuit. When the vehicle is running, the high-voltage relay is closed, providing a high-voltage connection. When the vehicle's high voltage is de-energized or a fault occurs, the high-voltage relay is open, thus isolating the high-voltage circuit from the low-voltage circuit.

[0040] The working principle of the analog front-end chip and voltage acquisition circuit in the voltage sampling circuit includes: the first pin and / or the second pin of the analog front-end chip acquire the voltage of the voltage sampling point through the voltage acquisition circuit, and the analog front-end chip then transmits the voltage to the main controller for processing. The main controller calculates parameters such as the remaining battery power, health status and power status based on the acquired voltage.

[0041] For related technologies, please refer to Figure 2 As shown, the analog front-end chip collects the voltage of the battery cells, while the remaining relays ( Figure 2 The voltages on both sides (not shown in the diagram) are acquired by an additional host device. The voltage of the battery cell acquired by the analog front-end chip and the voltages on both sides of the relay acquired by the host device are transmitted to the main controller through a communication bridge such as a daisy-chain circuit, which brings additional hardware costs.

[0042] Through the above technical solution, this disclosure eliminates the need for a host device. It acquires the voltage of the voltage sampling point through the first pin and / or the second pin in the existing analog front-end chip. For example, it acquires the voltage of the voltage sampling points on both sides of the relay through the first pin and / or the second pin. Therefore, it can achieve voltage acquisition of the voltage sampling point without the need for additional host device configuration, thus reducing hardware costs.

[0043] Figures 3 to 6 These are two methods for implementing voltage sampling points. Voltage sampling points include relays and battery cells. Therefore, the voltage of voltage sampling points can be acquired using the following two methods:

[0044] (1) Please refer to Figure 3 and Figure 4 As shown, the first pin and / or the second pin are connected to the relay through a voltage acquisition circuit, so that the first pin and / or the second pin can acquire the voltage on both sides of the relay through the voltage acquisition circuit to identify the on / off state of the relay.

[0045] Each first pin for collecting a voltage sampling point (for example, a relay) is configured with a voltage collection circuit to cooperate with the first pin to collect the voltage of the voltage sampling point; similarly, each second pin for collecting a voltage sampling point is configured with a voltage collection circuit to cooperate with the second pin to collect the voltage of the voltage sampling point.

[0046] Referring to Figure 3 As shown, the voltage collection circuit corresponding to the first pin Vcn+m includes a first resistor Rpullupx and a second resistor Rpulldownx, the first resistor Rpullupx and the second resistor Rpulldownx are connected in series, a first end of the first resistor Rpullupx is connected to a first end of the voltage sampling point, a second end of the first resistor Rpullupx is connected to a first end of the second resistor Rpulldownx, a second end of the second resistor Rpulldownx is grounded, and a second end of the voltage sampling point is grounded; the first pin and / or the second pin is connected to the connection point of the first resistor Rpullupx and the second resistor Rpulldownx.

[0047] Referring to Figure 5 As shown, the voltage collection circuit corresponding to the second pin GPIO1 includes a first resistor Rpullup1 and a second resistor Rpulldown1; the voltage collection circuit corresponding to the second pin GPIO2 includes a first resistor Rpullup2 and a second resistor Rpulldown2; and the voltage collection circuit corresponding to the second pin GPIOX includes a first resistor Rpullupx and a second resistor Rpulldownx.

[0048] Through the setting of the voltage collection circuit, the voltage collected by the first pin and / or the second pin is the voltage at the connection point of the first resistor and the second resistor, so that the voltage output by the battery cell is reduced after being divided by the first resistor and the second resistor to reach the first pin and / or the second pin, avoiding damage to the first pin and / or the second pin caused by the excessive voltage output by the battery cell.

[0049] Optionally, when the voltage sampling point is a relay, a first end of the first resistor Rpullupx is connected to a first end of the relay, a second end of the first resistor Rpullupx is connected to a first end of the second resistor Rpulldownx, a second end of the second resistor Rpulldownx is grounded, and a second end of the relay is grounded; the first pin is connected to the connection point of the first resistor Rpullupx and the second resistor Rpulldownx.

[0050] Referring to Figure 4As shown, the analog front-end chip AFEm is configured with multiple first pins such as Vcn~Vcn+m, and the voltage on both sides of the main positive relay Main+ is collected by the first pin Vcn+m, for example, the first end of the first resistor Rpullupx is connected to Vx (assuming x is 0, then Vx is V0), the second end of the first resistor Rpullupx is connected to the first end of the second resistor Rpulldownx, and the second end of the second resistor Rpulldownx is connected to the ground of the battery BANK1_CELLn+2; the first end of the main positive relay Main+ is connected to the point V0, which means that the first end of the main positive relay Main+ and the first end of the first resistor Rpullupx are connected to the point V0, so that the first end of the main positive relay Main+ and the first end of the first resistor Rpullupx are connected, and the second end of the main positive relay Main+ is grounded through the battery BANK11_CELLn+m and BANK1_CELLn+2, so that the first resistor Rpullupx, the second resistor Rpulldownx, the battery BANK1_CELLn+2, the battery BANK11_CELLn+m and the main positive relay Main+ form a loop as shown by the black line, and the first pin Vcn+m is connected to the connection point between the first resistor Rpullupx and the second resistor Rpulldownx. Figure 4 The first pin Vcn+m is connected to the connection point between the first resistor Rpullupx and the second resistor Rpulldownx.

[0051] In this way, the first pin Vcn+m will collect the voltage between the first resistor Rpullupx and the second resistor Rpulldownx, when the main positive relay Main+ is open, the first pin Vcn+m cannot collect the voltage, and the analog front-end chip sends the collected 0V voltage to the host controller, and the host controller determines that the main positive relay Main+ is in an open state; when the main positive relay Main+ is closed, the first pin Vcn+m can collect the voltage, and the analog front-end chip sends the collected voltage to the host controller, and the host controller determines that the main positive relay Main+ is in a closed state.

[0052] It can be understood that the remaining first pins on the analog front-end chip AFE can be used to collect the state of the main positive relay Main+ and the state of the main negative relay Main- as described above, and will not be described here.

[0053] The setting of collecting the voltage on both sides of the relay through the first pin can use the idle first pin on the analog front-end chip to collect the voltage on both sides of the relay, which can avoid the waste of idle first pins on one hand, and can achieve the collection of the voltage on both sides of the relay without the need for additional host devices. The idle first pin refers to the first pin on the analog front-end chip that does not collect the battery voltage, for example, please refer to Figure 4As shown, the first pin Vcn~the first pin Vcn+2 are all used to collect the voltage across the battery cell, while the first pin Vcn+m is idle and does not collect the voltage across the battery cell, so the idle first pin Vcn+m can be used to collect the voltage across the relay.

[0054] Optionally, when the voltage sampling point is the relay, the first end of the first resistor is connected to the first end of the relay, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is grounded, and the second end of the relay is grounded; the second pin is connected to the connection point of the first resistor and the second resistor.

[0055] Please refer to Figure 5 and Figure 6 As shown, the analog front-end chip is configured with multiple second pins such as GPIO1~GPIOX, the second pin GPIO1 is used to collect the voltage across the main positive relay Main+, and the first resistor is Rpullup1 and the second resistor is Rpulldown1, for example, the first end of the first resistor Rpullup1 is connected to V0, the second end of the first resistor Rpullup1 is connected to the first end of the second resistor Rpulldown1, and the second end of the second resistor Rpulldown1 is grounded; the first end of the main positive relay Main+ is connected to the V0 point, which means that the first end of the main positive relay Main+ and the first end of the first resistor Rpullup1 are connected to the V0 point at the same time, so that the first end of the main positive relay Main+ and the first end of the first resistor Rpullup1 are connected, and the second end of the main positive relay Main+ is grounded through the battery cell BANK1_CELLn+m~the battery cell BANK1_CELLn, in this way, the first resistor Rpullup1, the second resistor Rpulldown1, the battery cell BANK1_CELLn, the battery cell BANK1_CELLn+1, the battery cell BANK1_CELLn+2, and the battery cell BANK1_CELLn+m and the main positive relay Main+ form a loop as shown by the black line in Figure 6 , and the second pin GPIO1 is connected to the connection point between the first resistor Rpullup1 and the second resistor Rpulldown1.

[0056] Thus, the second pin GPIO1 collects the voltage between the first resistor Rpullup1 and the second resistor Rpulldown1, when the main positive relay Main+ is disconnected, the second pin GPIO1 cannot collect the voltage, the analog front-end chip sends the collected 0V voltage to the host controller, and the host controller judges that the main positive relay Main+ is in the disconnected state; when the main positive relay Main+ is closed, the second pin GPIO1 can collect the voltage, the analog front-end chip sends the collected voltage to the host controller, and the host controller judges that the main positive relay Main+ is in the closed state.

[0057] It can be understood that the states of the main positive relay Main+ and the main negative relay Main- can be collected by using the above example for the rest of the second pins on the analog front-end chip AFE, and details are not repeated here.

[0058] By setting the second pin to collect the voltage across the relay, the second pin on the analog front-end chip used to collect the temperature can be used to collect the voltage across the relay, which can avoid the waste of the second pin on the one hand, and can achieve the collection of the voltage across the relay without the need to additionally increase the host device on the other hand.

[0059] Optionally, the first pin and / or the second pin are connected through a third resistor and a voltage collection circuit. Each first pin in the analog front-end chip is connected through a respective third resistor and a voltage collection circuit; each second pin in the analog front-end chip is connected through a respective third resistor and a voltage collection circuit.

[0060] For example, the first pin and / or the second pin are connected to the connection point between the first resistor and the second resistor through a third resistor.

[0061] Referring to Figure 3 , the first pin VCn+m is connected to the connection point between the first resistor and the second resistor through a third resistor Rm+n.

[0062] Referring to Figure 5 , the second pin GPIO1 is connected to the connection point between the first resistor Rpullup1 and the second resistor Rpulldown1 through a third resistor RS1, the second pin GPIO2 is connected to the connection point between the first resistor Rpullup2 and the second resistor Rpulldown2 through a third resistor RS2, and the second pin GPIOx is connected to the connection point between the first resistor Rpullupx and the second resistor Rpulldownx through a third resistor RSx.

[0063] Through the setting of the third resistor, the current output by the battery can be reduced in the resistance of the third resistor, avoiding the current from being too large to break the first pin and / or the second pin.

[0064] (2) The adjacent two first pins on the analog front-end chip are respectively connected with the positive and negative poles of the battery to collect the voltage on both sides of the battery.

[0065] The adjacent two first pins on the analog front-end chip are respectively used to collect the voltage of the positive and negative poles of the battery and send to the main controller, and the main controller calculates the voltage of the battery according to the collected voltage of the positive and negative poles of the battery.

[0066] Please refer to Figure 5 As shown in the figure, the analog front-end chip is provided with a plurality of first pins such as Vcn~Vcn+m, adjacent first pins Vcn+1 and Vcn+2 are used to collect the voltage of the battery BANK1_CELLn+2 in the first battery BANK1, the first pin Vcn+1 is connected to the negative pole of the battery BANK1_CELLn+2, and the first pin Vcn+1 collects the voltage of the negative pole of the battery BANK1_CELLn+2; the first pin Vcn+2 is connected to the positive pole of the battery BANK1_CELLn+2, and the first pin Vcn+2 collects the voltage of the positive pole of the battery BANK1_CELLn+2; after the analog front-end chip sends the voltage of the positive and negative poles of the battery BANK1_CELLn+2 to the main controller, the main controller will calculate the voltage of the battery BANK1_CELLn+2 according to the difference between the two voltages.

[0067] Optionally, the adjacent two first pins on the analog front-end chip are respectively connected with the positive and negative poles of the battery through the fourth resistor. For each first pin in the analog front-end chip, it is connected with the positive or negative pole of the battery through the respective fourth resistor.

[0068] Please refer to Figure 5 As shown in the figure, the first pin Vcn+m is connected between the voltage sampling points V0 and V1 through the fourth resistor Rm+n, i.e. connected between the second end of the main positive relay Main+ and the positive pole of the battery BANK1_CELLn+m, the first pin Vcn+2 is connected between the negative pole of the battery BANK1_CELLn+m and the positive pole of the battery BANK1_CELLn+2 through the fourth resistor Rm+2, the first pin Vcn+1 is connected between the negative pole of the battery BANK1_CELLn+2 and the positive pole of the battery BANK1_CELLn+1 through the fourth resistor Rm+1, and the first pin Vcn is connected between the negative pole of the battery BANK1_CELLn+1 and the positive pole of the battery BANK_CELLn through the fourth resistor Rm.

[0069] In the above scheme, the second end of the voltage sampling point is grounded through at least one battery cell. For example, the second end of the main positive relay Main+ is grounded through at least one battery cell.

[0070] Based on the same concept, the disclosure also provides a voltage sampling system, which comprises the voltage sampling circuit described above, and is connected with the voltage sampling point to collect the voltage of the voltage sampling point.

[0071] Figure 7 is a block diagram of a vehicle 700 according to an example embodiment. For example, the vehicle 700 can be a hybrid vehicle, or a non-hybrid vehicle, an electric vehicle, a fuel cell vehicle, or other types of vehicles. The vehicle 700 can be an autonomous vehicle, a semi-autonomous vehicle, or a non-autonomous vehicle. The vehicle 700 is configured with the voltage sampling system described above to collect the state of the battery cells in the battery and the state of the relays in the high-voltage loop of the vehicle 700.

[0072] Referring to Figure 7 , the vehicle 700 can include various subsystems, such as an infotainment system 710, a perception system 720, a decision control system 730, a drive system 740, and a computing platform 750. The vehicle 700 can include more or fewer subsystems, and each subsystem can include multiple components. In addition, each subsystem of the vehicle 700 and each component can be interconnected by wired or wireless means.

[0073] In some embodiments, the infotainment system 710 can include a communication system, an entertainment system, a navigation system, and the like.

[0074] The perception system 720 can include a variety of sensors for sensing information about the environment around the vehicle 700. For example, the perception system 720 can include a global positioning system (which can be a GPS system, a Beidou system, or other positioning systems), an inertial measurement unit (IMU), a laser radar, a millimeter wave radar, an ultrasonic radar, and a camera.

[0075] The decision control system 730 can include a computing system, a vehicle controller, a steering system, a throttle, and a braking system.

[0076] The drive system 740 can include components that provide power motion for the vehicle 700. In one embodiment, the drive system 740 can include an engine, an energy source, a transmission system, and wheels. The engine can be one or a combination of an internal combustion engine, an electric motor, an air compression engine. The engine can convert the energy provided by the energy source into mechanical energy.

[0077] Some or all of the functionality of the vehicle 700 is controlled by a computing platform 750. The computing platform 750 can include at least one processor 751 and a memory 752, the processor 751 can execute instructions 753 stored in the memory 752.

[0078] The processor 751 can be any conventional processor, such as commercially available CPUs. The processor can also include a Graphics Process Unit (GPU), a Field Programmable Gate Array (FPGA), a System on Chip (SOC), an Application Specific Integrated Circuit (ASIC), or a combination thereof.

[0079] The memory 752 can be implemented by any type of volatile or nonvolatile memory or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0080] In addition to the instructions 753, the memory 752 can also store data, such as road maps, route information, the position, direction, speed, etc. of the vehicle. The data stored in the memory 752 can be used by the computing platform 750.

[0081] Some embodiments of the present disclosure also provide a chip system, which includes the analog front-end chip and the like described above, such as Figure 8 As shown, the chip system includes at least one processor 801 and at least one interface circuit 802. The processor 801 and the interface circuit 802 can be interconnected by a line. For example, the interface circuit 802 can be used to receive signals from other devices (such as the memory of an electronic device). For another example, the interface circuit 802 can be used to send signals to other devices (such as the processor 801). For example, the interface circuit 802 can read instructions stored in the memory and send the instructions to the processor 801. Of course, the chip system can also include other discrete devices, which are not specifically limited by some embodiments of the present disclosure.

[0082] In some embodiments of the present disclosure, the interface circuit 802 can obtain data, program instructions and / or information, etc. in the internal storage area of the chip system; it can also obtain data, program instructions and / or information, etc. outside the chip system.

[0083] Those skilled in the art can understand that various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by electronic hardware, computer software, or a combination of both. Whether the functions are implemented by hardware or software depends on the specific application and design requirements of the whole system. Those skilled in the art can implement the functions described in various ways for each specific application, but such implementation should not be construed as beyond the scope of the embodiments of the present application.

Claims

1. A voltage sampling circuit, characterized by, The voltage sampling circuit comprises an analog front-end chip and a voltage collection circuit. The analog front-end chip comprises a first pin and a second pin; the first pin and / or the second pin is connected with a voltage sampling point through the voltage collection circuit; the first pin is used for collecting an analog signal; and the second pin is a general pin on the analog front-end chip.

2. The voltage sampling circuit of claim 1, wherein, The voltage sampling point comprises a relay; the first pin and / or the second pin is connected with the relay through the voltage collection circuit.

3. The voltage sampling circuit of claim 1, wherein, The voltage sampling circuit further comprises a third resistor. The first pin and / or the second pin is connected with the voltage collection circuit through the third resistor.

4. The voltage sampling circuit of claim 1, wherein, The voltage sampling point further comprises a battery cell; two adjacent first pins on the analog front-end chip are respectively connected with positive and negative poles of the battery cell.

5. The voltage sampling circuit of claim 4, wherein, The two adjacent first pins on the analog front-end chip are respectively connected with the positive and negative poles of the battery cell through fourth resistors.

6. The voltage sampling circuit according to any one of claims 1 to 5, characterized in that, The voltage collection circuit comprises a first resistor and a second resistor. A first end of the first resistor is connected with a first end of the voltage sampling point; a second end of the first resistor is connected with a first end of the second resistor; a second end of the second resistor is grounded; and a second end of the voltage sampling point is grounded. The first pin and / or the second pin is connected on a connection point of the first resistor and the second resistor.

7. The voltage sampling circuit of claim 6, wherein, The second end of the voltage sampling point is grounded through at least one battery cell.

8. The voltage sampling circuit according to any one of claims 1 to 5, characterized in that, The first pin is a VCN pin; and the second pin is a GPIO pin.

9. A voltage sampling system, characterized by The voltage sampling circuit comprises the voltage sampling circuit according to any one of claims 1 to 8; and the voltage sampling circuit is connected with a voltage sampling point.

10. A vehicle characterized by comprising: The vehicle is provided with the voltage sampling system according to claim 9.

Images