Watchdog control circuit, mainboard and electronic equipment

Abstract

The embodiment of the utility model provides a watchdog control circuit, a mainboard and an electronic device, which relate to the technical field of electronic devices, and enable a main control chip to close a first watchdog module inside the main control chip through a control port under the condition that a debugging interface of the main control chip is electrically connected with a debugger. The switch module is disconnected under the condition that the debugging interface is electrically connected with the debugger, so that the second watchdog module is disconnected from the main control chip, the second watchdog module fails to send a reset signal to the main control chip, the watchdog function of the electronic equipment is closed, and the situation that in the prior art, due to the fact that the debugger is used for debugging the electronic equipment, the debugging time is shortened is avoided. And the watchdog circuit triggers the electronic equipment to be restarted, so that the debugging failure is caused, and the debugging success rate is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic equipment technical field especially, and it is a watchdog control circuit, mainboard and electronic equipment. BACKGROUND

[0002] The electronic equipment is provided with the watchdog circuit, and the watchdog circuit is a kind of timer, is used to carry out periodic counting, if not receiving the dog-feeding signal within the preset time, reset signal is sent to the electronic equipment, triggers the chip restart in electronic equipment, to avoid the abnormal condition of electronic equipment to cause the problem such as shutdown, system crash, guarantee the reliability, stability and safety of electronic equipment.

[0003] However, in the case of debugger accessing electronic equipment, using the debugger to debug electronic equipment, for example, using the debugger to carry out firmware upgrade, system upgrade and fault positioning to the chip in electronic equipment, etc., causes the dog-feeding signal of watchdog circuit of electronic equipment to be interrupted, and the watchdog circuit triggers the chip restart in electronic equipment, causing debugging failure. UTILITY MODEL CONTENTS

[0004] The utility model provides a kind of watchdog control circuit, mainboard and electronic equipment to at least solve the problem of debugging failure in prior art due to the watchdog circuit triggers electronic equipment to restart in the case of debugger accessing electronic equipment, using the debugger to debug electronic equipment.

[0005] In the first aspect, the utility model embodiment provides a kind of watchdog control circuit, applied to the debugging of main control chip, including switch module and control port;

[0006] The control port is used to be electrically connected with main control chip and the debugging interface of the main control chip respectively, in the case where the debugging interface is electrically connected with debugger, so that the main control chip closes the first watchdog module in the main control chip interior;In the case where the debugging interface is vacant, so that the main control chip opens the first watchdog module;

[0007] The switch module is electrically connected with the control port, and the switch module is used to be electrically connected with the main control chip and the second watchdog module outside the main control chip respectively, in the case where the debugging interface is electrically connected with the debugger, the switch module is disconnected, so that the second watchdog module is disconnected with the main control chip;And in the case where the debugging interface is vacant and the second watchdog module outputs reset signal, the switch module is conducted, so that the second watchdog module is conducted with the main control chip.

[0008] Optionally, the switch module comprises a first switch sub-module and a second switch sub-module; a control end of the first switch sub-module is electrically connected with the control port, a first end of the first switch sub-module is electrically connected with a control end of the second switch sub-module, a second end of the first switch sub-module is grounded, the first switch sub-module is used for being turned on in the case that the debugging interface is electrically connected with the debugger, and being turned off in the case that the debugging interface is vacant; a first end of the second switch sub-module is used for being electrically connected with a reset end of the master control chip, a second end of the second switch sub-module is used for being electrically connected with an output end of the second watchdog module, the second switch sub-module is used for being turned off in the case that the first switch sub-module is turned on, and being turned on in the case that the first switch sub-module is turned off and the output end of the second watchdog module outputs the reset signal.

[0009] Optionally, the first switch sub-module comprises a first resistor, a second resistor and a first switch device; a first end of the first resistor is electrically connected with the control port, a second end of the first resistor is electrically connected with a first end of the second resistor and a control end of the first switch device respectively; a first end of the first switch device is electrically connected with the control end of the second switch sub-module, a second end of the first switch device is grounded; a second end of the second resistor is grounded.

[0010] Optionally, the second switch sub-module comprises a third resistor and a second switch device; a first end of the third resistor is used for being electrically connected with an external power supply, a second end of the third resistor is electrically connected with the first end of the first switch sub-module and a control end of the second switch device respectively; the control end of the second switch device is electrically connected with the first end of the first switch sub-module, a first end of the second switch device is used for being electrically connected with the reset end of the master control chip, a second end of the second switch device is used for being electrically connected with the output end of the second watchdog module.

[0011] Optionally, the second end of the third resistor is used for being electrically connected with the first end of the master control chip; the control end of the second switch device is used for being electrically connected with the first end of the master control chip; the control port is used for being electrically connected with the second end of the master control chip; the master control chip is used for controlling the second switch device to be turned off in the case that the debugging interface is electrically connected with the debugger.

[0012] Optionally, the switch module comprises a third switch submodule, a fourth switch submodule and a fifth switch submodule; the control end of the third switch submodule is electrically connected with the control port, the first end of the third switch submodule is electrically connected with the control end of the fourth switch submodule, the second end of the third switch submodule is grounded, and the third switch submodule is used for being turned on when the debugging interface is electrically connected with the debugger, and being turned off when the debugging interface is vacant; the first end of the fourth switch submodule is electrically connected with the control end of the fifth switch submodule, the second end of the fourth switch submodule is used for being electrically connected with an external power supply, and the fourth switch submodule is used for being turned on when the third switch submodule is turned on, and being turned off when the third switch submodule is turned off; the first end of the fifth switch submodule is used for being electrically connected with the output end of the second watchdog module, the second end of the fifth switch submodule is used for being electrically connected with the reset end of the master control chip, and the fifth switch submodule is used for being turned off when the fourth switch submodule is turned on, and being turned on when the fourth switch submodule is turned off and the output end of the second watchdog module outputs the reset signal.

[0013] Optionally, the third switch submodule comprises a fourth resistor, a fifth resistor and a third switch device; the first end of the fourth resistor is electrically connected with the control port, and the second end of the fourth resistor is respectively electrically connected with the first end of the fifth resistor and the control end of the third switch device; the first end of the third switch device is electrically connected with the control end of the fourth switch submodule, and the second end of the third switch device is grounded; and the second end of the fifth resistor is grounded.

[0014] Optionally, the fourth switch submodule comprises a sixth resistor, a seventh resistor and a fourth switch device; the first end of the sixth resistor is used for being electrically connected with an external power supply, and the second end of the sixth resistor is respectively electrically connected with the first end of the third switch submodule and the control end of the fourth switch device; the control end of the fourth switch device is electrically connected with the first end of the third switch submodule, the first end of the fourth switch device is electrically connected with the control end of the fifth switch submodule, the second end of the fourth switch device is electrically connected with the first end of the seventh resistor; and the second end of the seventh resistor is used for being electrically connected with the external power supply.

[0015] Optionally, the fifth switch sub-module comprises an eighth resistor and a fifth switch device; a first end of the eighth resistor is grounded, a second end of the eighth resistor is electrically connected with the first end of the fourth switch sub-module and a control end of the fifth switch device respectively; the control end of the fifth switch device is electrically connected with the first end of the fourth switch sub-module, a first end of the fifth switch device is used for being electrically connected with an output end of the second watchdog module, and a second end of the fifth switch device is used for being electrically connected with a reset end of the master control chip.

[0016] Optionally, the second end of the eighth resistor is used for being electrically connected with the first end of the master control chip; the control end of the fifth switch device is used for being electrically connected with the first end of the master control chip; the control port is used for being electrically connected with the second end of the master control chip; and the master control chip is used for controlling the fifth switch device to be disconnected in the case that the debugging interface is electrically connected with the debugger.

[0017] Optionally, the watchdog control circuit further comprises a ninth resistor; a first end of the ninth resistor is electrically connected with the control port, and a second end of the ninth resistor is used for being electrically connected with the second end of the master control chip.

[0018] In the second aspect, the utility model embodiment further provides a mainboard, comprising the watchdog control circuit of the first aspect.

[0019] In the third aspect, the utility model embodiment further provides an electronic device, comprising the watchdog control circuit of the first aspect or the mainboard of the second aspect.

[0020] In the utility model embodiment, the control port is used for making the master control chip close the first watchdog module inside the master control chip in the case that the debugging interface of the master control chip is electrically connected with the debugger, and the switch module is used for being disconnected in the case that the debugging interface is electrically connected with the debugger, so that the second watchdog module is disconnected with the master control chip, and then the second watchdog module fails to send the reset signal to the master control chip, thereby closing the watchdog function of the electronic device, avoiding the problem that the watchdog circuit triggers the electronic device to restart in the prior art due to the use of the debugger to debug the electronic device, leading to the debugging failure, and improving the success rate of debugging. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical scheme of the utility model embodiment, the following will briefly introduce the drawings needed to be used in the description of the utility model embodiment. Obviously, the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained according to these drawings without the creative labor of the person skilled in the art.

[0022] Figure 1It is a structure schematic view of a watchdog control circuit provided by the embodiment of the utility model;

[0023] Figure 2 It is a specific structure schematic view of the watchdog control circuit provided by the embodiment of the utility model;

[0024] Figure 3 It is another specific structure schematic view of the watchdog control circuit provided by the embodiment of the utility model.

[0025] Reference signs:

[0026] 10-switching module;11-first switching submodule;12-second switching submodule;13-third switching submodule;14-fourth switching submodule;15-fifth switching submodule;101-control port;20-second watchdog module;30-master control chip;40-debugging interface;50-debugger;60-upper computer;70-mainboard;R1-first resistor;R2-second resistor;R3-third resistor;R4-fourth resistor;R5-fifth resistor;R6-sixth resistor;R7-seventh resistor;R8-eighth resistor;R9-ninth resistor;Q1-first switching device;Q2-second switching device;Q3-third switching device;Q4-fourth switching device;Q5-fifth switching device. DETAILED DESCRIPTION

[0027] In order to make the above purpose, features and advantages of the utility model more apparent, easy to understand, the following will combine with the specific embodiment and make further detailed description to the utility model.

[0028] Reference Figure 1 The embodiment of the utility model provides a watchdog control circuit, including switching module 10 and control port 101;The control port 101 is used to be electrically connected with the master control chip 30 of electronic equipment and the debugging interface 40 of the master control chip 30 respectively, under the condition that the debugging interface 40 is electrically connected with the debugger 50, make the master control chip 30 close the first watchdog module in the master control chip 30;Under the condition that the debugging interface 40 is vacant, make the master control chip 30 open the first watchdog module;The switching module 10 is electrically connected with the control port 101, and the switching module 10 is used to be electrically connected with the master control chip 30 and the second watchdog module 20 outside the master control chip 30 respectively, under the condition that the debugging interface 40 is electrically connected with the debugger 50, the switching module 10 is disconnected, so that the second watchdog module 20 is disconnected with the master control chip 30;And under the condition that the debugging interface 40 is vacant and the second watchdog module 20 outputs reset signal, the switching module 10 is turned on, so that the second watchdog module 20 is turned on with the master control chip 30.

[0029] It should be noted that the type of the first watchdog module includes a watchdog circuit, a watchdog chip, etc.; the type of the second watchdog module 20 includes a watchdog circuit, a watchdog chip, etc.

[0030] In the case of the feeding signal interruption of the second watchdog module 20, the second watchdog module 20 outputs a reset signal, and the reset signal is used to trigger the electronic device to restart, that is, the main control chip 30 controls the electronic device to restart in the case of receiving the reset signal.

[0031] Specifically, in some embodiments, the reset signal is a low level.

[0032] The main control chip 30 can be a system on chip (SoC), a central processing unit (CPU), a microcontroller unit (MCU), or other types of chips.

[0033] The main control chip 30 is electrically connected with a debugging interface 40 of the main control chip 30, the debugging interface 40 of the main control chip 30 is used to be electrically connected with a debugger 50, and the debugger 50 is used to be electrically connected with an upper computer 60; the debugging interface 40 is arranged on a mainboard 70 of the electronic device; the debugging interface 40 is vacant, that is, the debugging interface 40 is not electrically connected with external devices such as the debugger 50.

[0034] Specifically, in some embodiments, the debugging interface 40 is a joint test action group (JTAG) debugging interface 40, the debugger 50 is a JTAG debugger 50, and the control port 101 is specifically used to be electrically connected with a JTAG_TRST end in the debugging interface 40, wherein the JTAG_TRST end is one optional signal end in the JTAG interface; in the case that the debugging interface 40 is electrically connected with the debugger 50 and the debugger 50 normally works, the debugger 50 sends a high-level JTAG_TRST signal through the JTAG_TRST end in the debugging interface 40, and the JTAG_TRST end is high level; in the case that the debugger 50 is electrically connected with the upper computer 60 and the debugger 50 normally works, it is determined that the debugger 50 normally works.

[0035] The electronic device can be an electronic device provided with the first watchdog module, or an electronic device provided with the second watchdog module 20, or an electronic device provided with the first watchdog module and the second watchdog module 20; in the case that the electronic device works, the electronic device defaults to use the first watchdog module, or the electronic device defaults to use the second watchdog module 20, or the electronic device defaults to use the first watchdog module and the second watchdog module 20.

[0036] The master chip 30 can control the opening and closing of the first watchdog module inside the master chip 30, in the case that the master chip 30 opens the first watchdog module, the first watchdog module can trigger the electronic device to restart in the case of watchdog feeding signal interruption; in the case that the master chip 30 closes the first watchdog module, the first watchdog module stops working, that is, in the case of watchdog feeding signal interruption, the first watchdog module does not trigger the electronic device to restart.

[0037] In the embodiment of the utility model, through the control port 101 in the case of the debugging interface 40 and the debugger 50 of the master chip 30 are electrically connected, the master chip 30 closes the first watchdog module inside the master chip 30, and through the switch module 10 in the case of the debugging interface 40 and the debugger 50 are electrically connected, the second watchdog module 20 is disconnected with the master chip 30, and then the second watchdog module 20 sends the reset signal to the master chip 30 fails, so as to close the watchdog function of the electronic device, avoid the prior art in the use of the debugger debugging electronic device, cause the watchdog circuit to trigger the electronic device to restart, lead to the problem of debugging failure, improve the success rate of debugging.

[0038] In addition, through the control port 101 in the case of the debugging interface 40 is vacant, the master chip 30 opens the first watchdog module, and through the switch module 10 in the case that the debugging interface 40 is vacant and the second watchdog module 20 outputs the reset signal, the second watchdog module 20 is turned on with the master chip 30, and then the second watchdog module 20 sends the reset signal to the master chip 30 successfully, so as to open the watchdog function of the electronic device in the case that the debugger 50 is not connected to the electronic device, guarantee the watchdog function of the electronic device is normal.

[0039] Optionally, refer to Figure 2In some embodiments, the switch module 10 comprises a first switch submodule 11 and a second switch submodule 12; the control end of the first switch submodule 11 is electrically connected with the control port 101, the first end of the first switch submodule 11 is electrically connected with the control end of the second switch submodule 12, the second end of the first switch submodule 11 is grounded, the first switch submodule 11 is used for being turned on when the debugging interface 40 is electrically connected with the debugger 50, and being turned off when the debugging interface 40 is vacant; the first end of the second switch submodule 12 is used for being electrically connected with the reset end of the master control chip 30, the second end of the second switch submodule 12 is used for being electrically connected with the output end of the second watchdog module 20, the second switch submodule 12 is used for being turned off when the first switch submodule 11 is turned on, and being turned on when the first switch submodule 11 is turned off and the output end of the second watchdog module 20 outputs the reset signal.

[0040] In the embodiments of the utility model, through the first switch submodule 11 is turned on when the debugging interface 40 is electrically connected with the debugger 50, and then the second switch submodule 12 is turned off when the first switch submodule 11 is turned on, the second watchdog module 20 is disconnected with the master control chip 30, and then the second watchdog module 20 fails to send the reset signal to the master control chip 30, so that the watchdog function of the electronic equipment is closed; through the first switch submodule 11 is turned off when the debugging interface 40 is vacant, and then the second switch submodule 12 is turned on when the first switch submodule 11 is turned off and the output end of the second watchdog module 20 outputs the reset signal, the second watchdog module 20 is connected with the master control chip 30, and then the second watchdog module 20 succeeds in sending the reset signal to the master control chip 30, so that the watchdog function of the electronic equipment is started when the debugger 50 is not connected to the electronic equipment, and the watchdog function of the electronic equipment is ensured to be normal.

[0041] Optionally, in some embodiments, the first switch submodule 11 comprises a first resistor R1, a second resistor R2 and a first switch device Q1; the first end of the first resistor R1 is electrically connected with the control port 101, the second end of the first resistor R1 is respectively electrically connected with the first end of the second resistor R2 and the control end of the first switch device Q1; the first end of the first switch device Q1 is electrically connected with the control end of the second switch submodule 12, and the second end of the first switch device Q1 is grounded; the second end of the second resistor R2 is grounded.

[0042] It should be noted that the first resistor R1 is a current limiting resistor, and the second resistor R2 is a pull-down resistor; in the case that the debugging interface 40 is electrically connected with the debugger 50, the control port 101 is high level, so that the control end of the first switch device Q1 is high level; in the case that the debugging interface 40 is empty, the second resistor R2 pulls down the control port 101 to low level, and the second resistor R2 pulls down the control end of the first switch device Q1 to low level.

[0043] Specifically, in some embodiments, the first switch device Q1 is an NPN triode, wherein the NPN triode is composed of three semiconductor blocks, including two N (Negative Electricity) type semiconductor blocks (electron type semiconductor) and one P (Positive Electricity) type semiconductor block (hole type semiconductor); the base of the first switch device Q1 is electrically connected with the second end of the first resistor R1 and the first end of the second resistor R2 respectively, the collector of the first switch device Q1 is electrically connected with the control end of the second switch sub-module 12, and the emitter of the first switch device Q1 is grounded.

[0044] In other embodiments, the first switch device Q1 is an NMOS tube (Negative channel-Metal-Oxide-Semiconductor), the gate of the first switch device Q1 is electrically connected with the second end of the first resistor R1 and the first end of the second resistor R2 respectively, the drain of the first switch device Q1 is electrically connected with the control end of the second switch sub-module 12, and the source of the first switch device Q1 is grounded.

[0045] In the embodiment of the utility model, under the condition that the debugging interface 40 is electrically connected with the debugger 50, the first end of the first switch device Q1 and the second end of the first switch device Q1 are turned on, and under the condition that the debugging interface 40 is empty, the first end of the first switch device Q1 and the second end of the first switch device Q1 are disconnected.

[0046] Optionally, in some embodiments, the second switch sub-module 12 includes a third resistor R3 and a second switch device Q2; the first end of the third resistor R3 is used for being electrically connected with an external power supply, the second end of the third resistor R3 is electrically connected with the first end of the first switch sub-module 11 and the control end of the second switch device Q2 respectively; the control end of the second switch device Q2 is electrically connected with the first end of the first switch sub-module 11, the first end of the second switch device Q2 is used for being electrically connected with the reset end of the master control chip 30, and the second end of the second switch device Q2 is used for being electrically connected with the output end of the second watchdog module 20.

[0047] It should be noted that, in the case of the first switch sub-module 11 being turned on, the control end of the second switch device Q2 is grounded, so that the control end of the second switch device Q2 is at a low level, and the second switch device Q2 is turned off; in the case of the first switch sub-module 11 being turned off, the control end of the second switch device Q2 is pulled up to a high level through the third resistor R3, and in the case that the output end of the second watchdog module 20 outputs a reset signal, since the reset signal is at a low level, the output end of the second watchdog module 20 is at a low level, the second end of the second switch device Q2 is at a low level, and the second switch device Q2 is turned on.

[0048] Specifically, in some embodiments, the second switch device Q2 is an NPN triode, the base of the second switch device Q2 is electrically connected with the second end of the third resistor R3 and the first end of the first switch sub-module 11 respectively, the collector of the second switch device Q2 is used for being electrically connected with the reset end of the master control chip 30, and the emitter of the second switch device Q2 is used for being electrically connected with the output end of the second watchdog module 20.

[0049] In other embodiments, the first switch device Q1 is an NMOS tube, the gate of the second switch device Q2 is electrically connected with the second end of the third resistor R3 and the first end of the first switch sub-module 11 respectively, the drain of the second switch device Q2 is used for being electrically connected with the reset end of the master control chip 30, and the source of the second switch device Q2 is used for being electrically connected with the output end of the second watchdog module 20.

[0050] In the embodiment of the utility model, through the second switch device Q2 in the case of the first switch sub-module 11 being turned on, the first end of the second switch device Q2 and the second end of the second switch device Q2 are disconnected, then the second watchdog module 20 is disconnected with the master control chip 30, and further makes the second watchdog module 20 send the reset signal to the master control chip 30 fail, so as to close the watchdog function of the electronic equipment;Through the second switch device Q2 in the case of the first switch sub-module 11 being turned off and the output end of the second watchdog module 20 outputting a reset signal, the first end of the second switch device Q2 and the second end of the second switch device Q2 are turned on, then the second watchdog module 20 is turned on with the master control chip 30, and further makes the second watchdog module 20 send the reset signal to the master control chip 30 succeed, so as to open the watchdog function of the electronic equipment in the case that the debugger 50 is not connected to the electronic equipment, guarantee the normal watchdog function of the electronic equipment.

[0051] Optionally, in some embodiments, a second end of the third resistor R3 is configured to be electrically connected to a first end of the master chip 30; a control end of the second switch device Q2 is configured to be electrically connected to the first end of the master chip 30; the control port 101 is configured to be electrically connected to a second end of the master chip 30; and the master chip 30 is configured to control the second switch device Q2 to be turned off when the debug interface 40 is electrically connected to the debugger 50.

[0052] It should be noted that the master chip 30 is further configured to control the second switch device Q2 to be turned on when the debug interface 40 is vacant.

[0053] When the debug interface 40 is electrically connected to the debugger 50, the first end of the master chip 30 is at a low level, the control end of the second switch device Q2 is pulled low, the control end of the second switch device Q2 is at a low level, the second switch device Q2 is turned off, and the second watchdog module 20 is disconnected from the master chip 30; when the debug interface 40 is vacant, the first end of the master chip 30 is at a high level, the control end of the second switch device Q2 is at a high level, in the case that the output end of the second watchdog module 20 outputs a reset signal, the reset signal is at a low level, the second end of the second switch device Q2 is at a low level, in the case that the control end of the second switch device Q2 is at a high level and the second end of the second switch device Q2 is at a low level, the second switch device Q2 is turned on, the second watchdog module 20 inputs the reset signal to the master chip 30, and the electronic device is triggered to restart.

[0054] Specifically, in some embodiments, the debug interface 40 is a Joint Test Action Group (JTAG) debug interface 40, the debugger 50 is a JTAG debugger 50, and the control port 101 is specifically configured to be electrically connected to a JTAG_TRST end in the debug interface 40; the master chip 30 is configured to make the first end of the master chip 30 be at a low level when the second end of the master chip 30 is at a high level, and make the first end of the master chip 30 be at a high level when the second end of the master chip 30 is at a low level;

[0055] In the case that the debugging interface 40 is electrically connected with the debugger 50 and the debugger 50 is normally working, the JTAG_TRST end is high, the control port 101 is high, the second end of the main control chip 30 is high, the first end of the main control chip 30 is low, the first end of the main control chip 30 pulls the control end of the second switch device Q2 to low, the second switch device Q2 is disconnected, and the second watchdog module 20 is disconnected with the main control chip 30; in the case that the debugging interface 40 is vacant, the JTAG_TRST end is vacant, the control port 101 is vacant, the second end of the main control chip 30 is pulled to low by the second resistance R2, the first end of the main control chip 30 is high, the control end of the second switch device Q2 is high, in the case that the output end of the second watchdog module 20 outputs the reset signal, the reset signal is low, the second end of the second switch device Q2 is low, in the case that the control end of the second switch device Q2 is high and the second end of the second switch device Q2 is low, the second switch device Q2 is turned on, the second watchdog module 20 inputs the reset signal to the main control chip 30, and the electronic equipment is triggered to restart.

[0056] In some embodiments, the main control chip 30 is specifically used for closing the first watchdog module inside the main control chip 30 in the case that the second end of the main control chip 30 is high, and opening the first watchdog module in the case that the second end of the main control chip 30 is low.

[0057] In the embodiment of the utility model, the main control chip 30 and the first switch submodule 11 are the redundant control structure, in the case that the first switch submodule 11 is invalid, the second switch device Q2 can be controlled to disconnect by the main control chip 30 in the case that the debugging interface 40 is electrically connected with the debugger 50, and the second switch device Q2 can be controlled to turn on by the main control chip 30 in the case that the debugging interface 40 is vacant.

[0058] Specifically, in some embodiments, the watchdog control circuit includes a switch module 10 and a control port 101, the switch module 10 includes a first switch submodule 11 and a second switch submodule 12, the first switch submodule 11 includes a first resistance R1, a second resistance R2 and a first switch device Q1, and the second switch submodule 12 includes a third resistance R3 and a second switch device Q2.

[0059] The first end of the first resistor R1 is electrically connected with the control port 101, the second end of the first resistor R1 is electrically connected with the first end of the second resistor R2 and the control end of the first switch device Q1 respectively; the first end of the first switch device Q1 is electrically connected with the second end of the third resistor R3 and the control end of the second switch device Q2 respectively, the second end of the first switch device Q1 is grounded; the second end of the second resistor R2 is grounded; the first end of the third resistor R3 is used for being electrically connected with an external power supply, the second end of the third resistor R3 is electrically connected with the control end of the second switch device Q2; the first end of the second switch device Q2 is used for being electrically connected with the reset end of the master control chip 30, the second end of the second switch device Q2 is used for being electrically connected with the output end of the second watchdog module 20; the second end of the third resistor R3 is used for being electrically connected with the first end of the master control chip 30; the control end of the second switch device Q2 is used for being electrically connected with the first end of the master control chip 30; the control port 101 is used for being electrically connected with the debugging interface 40 of the master control chip 30, and the control port 101 is used for being electrically connected with the second end of the master control chip 30.

[0060] Optionally, referring to Figure 3 In some embodiments, the switch module 10 comprises a third switch submodule 13, a fourth switch submodule 14 and a fifth switch submodule 15; the control end of the third switch submodule 13 is electrically connected with the control port 101, the first end of the third switch submodule 13 is electrically connected with the control end of the fourth switch submodule 14, the second end of the third switch submodule 13 is grounded, the third switch submodule 13 is used for being turned on in the case that the debugging interface 40 is electrically connected with the debugger 50, and being turned off in the case that the debugging interface 40 is vacant; the first end of the fourth switch submodule 14 is electrically connected with the control end of the fifth switch submodule 15, the second end of the fourth switch submodule 14 is used for being electrically connected with an external power supply, the fourth switch submodule 14 is used for being turned on in the case that the third switch submodule 13 is turned on, and being turned off in the case that the third switch submodule 13 is turned off; the first end of the fifth switch submodule 15 is used for being electrically connected with the output end of the second watchdog module 20, the second end of the fifth switch submodule 15 is used for being electrically connected with the reset end of the master control chip 30, the fifth switch submodule 15 is used for being turned off in the case that the fourth switch submodule 14 is turned on, and being turned on in the case that the fourth switch submodule 14 is turned off and the output end of the second watchdog module 20 outputs the reset signal.

[0061] In the embodiment of the utility model, through the third switch sub module 13 in the debugging interface 40 and the debugging ware 50 electric connection case conduction, again through the fourth switch sub module 14 in the third switch sub module 13 conduction case conduction, then through the fifth switch sub module 15 in the fourth switch sub module 14 conduction, and the output end of second watchdog module 20 output reset signal case conduction, make second watchdog module 20 with main control chip 30 conduction, and then make second watchdog module 20 to main control chip 30 send reset signal success, so in the debugging ware 50 not access electronic equipment case, open electronic equipment's watchdog function, guarantee electronic equipment's watchdog function normal.

[0062] Optionally, in some embodiments, the third switch sub module 13 includes a fourth resistor R4, a fifth resistor R5 and a third switch device Q3; the first end of the fourth resistor R4 is electrically connected with the control port 101, the second end of the fourth resistor R4 is respectively electrically connected with the first end of the fifth resistor R5 and the control end of the third switch device Q3; the first end of the third switch device Q3 is electrically connected with the control end of the fourth switch sub module 14, and the second end of the third switch device Q3 is grounded; and the second end of the fifth resistor R5 is grounded.

[0063] It should be noted that the fourth resistor R4 is a current-limiting resistor, and the fifth resistor R5 is a pull-down resistor; in the case that the debugging interface 40 is electrically connected with the debugging ware 50, the control port 101 is high level, so that the control end of the third switch device Q3 is high level; in the case that the debugging interface 40 is empty, the fifth resistor R5 pulls down the control port 101 to low level, and the fifth resistor R5 pulls down the control end of the third switch device Q3 to low level.

[0064] Specifically, in some embodiments, the third switch device Q3 is an NPN triode, the base of the third switch device Q3 is electrically connected with the second end of the fourth resistor R4 and the first end of the fifth resistor R5 respectively, the collector of the third switch device Q3 is electrically connected with the control end of the fourth switch sub module 14, and the emitter of the third switch device Q3 is grounded.

[0065] In some embodiments, the third switch device Q3 is an NMOS tube, the gate of the third switch device Q3 is electrically connected with the second end of the fourth resistor R4 and the first end of the fifth resistor R5 respectively, the drain of the third switch device Q3 is electrically connected with the control end of the fourth switch sub-module 14, and the source of the third switch device Q3 is grounded.

[0066] In the embodiments of the utility model, under the condition that the third switch device Q3 is electrically connected with the debugging interface 40 and the debugger 50, the first end of the third switch device Q3 and the second end of the third switch device Q3 are turned on; under the condition that the third switch device Q3 is vacant, the first end of the third switch device Q3 and the second end of the third switch device Q3 are disconnected.

[0067] Optionally, in some embodiments, the fourth switch sub-module 14 comprises a sixth resistor R6, a seventh resistor R7 and a fourth switch device Q4; the first end of the sixth resistor R6 is used for being electrically connected with an external power supply, the second end of the sixth resistor R6 is electrically connected with the first end of the third switch sub-module 13 and the control end of the fourth switch device Q4 respectively; the control end of the fourth switch device Q4 is electrically connected with the first end of the third switch sub-module 13, the first end of the fourth switch device Q4 is electrically connected with the control end of the fifth switch sub-module 15, and the second end of the fourth switch device Q4 is electrically connected with the first end of the seventh resistor R7; the second end of the seventh resistor R7 is used for being electrically connected with the external power supply.

[0068] It should be noted that the sixth resistor R6 and the seventh resistor R7 are both pull-up resistors, under the condition that the third switch sub-module 13 is turned on, the control end of the fourth switch device Q4 is grounded, the control end of the fourth switch device Q4 is pulled low to a low level, the seventh resistor R7 pulls the second end of the fourth switch device Q4 high to a high level, and the fourth switch device Q4 is turned on; under the condition that the third switch sub-module 13 is disconnected, the sixth resistor R6 pulls the control end of the fourth switch device Q4 up to a high level, the seventh resistor R7 pulls the second end of the fourth switch device Q4 high to a high level, and the fourth switch device Q4 is disconnected;

[0069] Specifically, in some embodiments, the fourth switch device Q4 is a PNP type triode, the PNP type triode is composed of three semiconductor blocks, including one N type semiconductor and two P type semiconductor blocks, the N type semiconductor is in the middle, and the two P type semiconductor blocks are on both sides; the base of the fourth switch device Q4 is electrically connected with the second end of the sixth resistor R6 and the first end of the third switch sub-module 13 respectively; the collector of the fourth switch device Q4 is electrically connected with the control end of the fifth switch sub-module 15, and the emitter of the fourth switch device Q4 is electrically connected with the first end of the seventh resistor R7.

[0070] In some embodiments, the fourth switch device Q4 is a PMOS tube, the gate of the fourth switch device Q4 is electrically connected with the second end of the sixth resistor R6 and the first end of the third switch submodule 13 respectively, the drain of the fourth switch device Q4 is electrically connected with the control end of the fifth switch submodule 15, and the source of the fourth switch device Q4 is electrically connected with the first end of the seventh resistor R7.

[0071] In the embodiment of the utility model, under the condition that the third switch submodule 13 is turned on, the first end of the fourth switch device Q4 and the second end of the fourth switch device Q4 are turned on, and under the condition that the third switch submodule 13 is turned off, the first end of the fourth switch device Q4 and the second end of the fourth switch device Q4 are turned off.

[0072] Optionally, in some embodiments, the fifth switch submodule 15 comprises an eighth resistor R8 and a fifth switch device Q5, the first end of the eighth resistor R8 is grounded, the second end of the eighth resistor R8 is electrically connected with the first end of the fourth switch submodule 14 and the control end of the fifth switch device Q5 respectively, the control end of the fifth switch device Q5 is electrically connected with the first end of the fourth switch submodule 14, the first end of the fifth switch device Q5 is used for being electrically connected with the output end of the second watchdog module 20, and the second end of the fifth switch device Q5 is used for being electrically connected with the reset end of the master control chip 30.

[0073] It should be noted that the eighth resistor R8 is a pull-down resistor, under the condition that the fourth switch submodule 14 is turned on, the control end of the fifth switch device Q5 is pulled up to high level by the seventh resistor R7, the reset end of the master control chip 30 is high level, and the fifth switch device Q5 is turned off, under the condition that the fourth switch submodule 14 is turned off and the output end of the second watchdog module 20 outputs a reset signal, the reset end of the master control chip 30 is high level, the control end of the fifth switch device Q5 is pulled down to low level by the eighth resistor R8, and the fifth switch device Q5 is turned on at this time.

[0074] Specifically, in some embodiments, the fifth switch device Q5 is a PNP type triode, the base of the fifth switch device Q5 is electrically connected with the first end of the fourth switch submodule 14 and the second end of the eighth resistor R8 respectively, the collector of the fifth switch device Q5 is used for being electrically connected with the output end of the second watchdog module 20, and the emitter of the fifth switch device Q5 is used for being electrically connected with the reset end of the master control chip 30.

[0075] In some embodiments, the fifth switch device Q5 is a PMOS tube, the gate of the fifth switch device Q5 is electrically connected with the first end of the fourth switch sub-module 14 and the second end of the eighth resistor R8 respectively, the drain of the fifth switch device Q5 is used for being electrically connected with the output end of the second watchdog module 20, and the source of the fifth switch device Q5 is used for being electrically connected with the reset end of the master control chip 30.

[0076] In the embodiments of the utility model, under the condition that the fourth switch sub-module 14 is turned on, the first end of the fifth switch device Q5 and the second end of the fifth switch device Q5 are disconnected; under the condition that the fourth switch sub-module 14 is disconnected and the output end of the second watchdog module 20 outputs the reset signal, the first end of the fifth switch device Q5 and the second end of the fifth switch device Q5 are turned on.

[0077] Optionally, in some embodiments, the second end of the eighth resistor R8 is used for being electrically connected with the first end of the master control chip 30; the control end of the fifth switch device Q5 is used for being electrically connected with the first end of the master control chip 30; the control port 101 is used for being electrically connected with the second end of the master control chip 30; the master control chip 30 is used for controlling the fifth switch device Q5 to be disconnected under the condition that the debugging interface 40 is electrically connected with the debugger 50.

[0078] It should be noted that the master control chip 30 is also used for controlling the fifth switch device Q5 to be turned on under the condition that the debugging interface 40 is vacant;

[0079] Under the condition that the debugging interface 40 is electrically connected with the debugger 50, the first end of the master control chip 30 is high level, the control end of the fifth switch device Q5 is pulled high, the control end of the fifth switch device Q5 is high level, and the reset end of the master control chip 30 is high level, so that the second end of the fifth switch device Q5 is high level; under the condition that the control end of the fifth switch device Q5 is high level and the second end of the fifth switch device Q5 is high level, the fifth switch device Q5 is disconnected, so that the second watchdog module 20 is disconnected with the master control chip 30; under the condition that the debugging interface 40 is vacant, the first end of the master control chip 30 is low level, so that the control end of the fifth switch device Q5 is low level, and the reset end of the master control chip 30 is high level, so that the second end of the fifth switch device Q5 is high level; under the condition that the control end of the fifth switch device Q5 is low level and the second end of the fifth switch device Q5 is high level, the fifth switch device Q5 is turned on, so that the second watchdog module 20 inputs the reset signal to the master control chip 30, and triggers the electronic equipment to restart.

[0080] Specifically, in some embodiments, the debugging interface 40 is a Joint Test Action Group (JTAG) debugging interface 40, the debugger 50 is a JTAG debugger 50, and the control port 101 is specifically electrically connected with the JTAG_TRST terminal in the debugging interface 40; the master control chip 30 is specifically configured to be high at the second terminal of the master control chip 30, and make the first terminal of the master control chip 30 high, and be low at the second terminal of the master control chip 30, and make the first terminal of the master control chip 30 low.

[0081] In the case that the debugging interface 40 is electrically connected with the debugger 50 and the debugger 50 works normally, the JTAG_TRST terminal is high, the control port 101 is high, the second terminal of the master control chip 30 is high, the first terminal of the master control chip 30 is high, the control terminal of the fifth switching device Q5 is high, the reset terminal of the master control chip 30 is high, the second terminal of the fifth switching device Q5 is high, the fifth switching device Q5 is off, and the second watchdog module 20 is disconnected with the master control chip 30; in the case that the debugging interface 40 is empty, the JTAG_TRST terminal is empty, the control port 101 is empty, the second terminal of the master control chip 30 is low by the fifth resistor R5, the first terminal of the master control chip 30 is low, the control terminal of the fifth switching device Q5 is low by the first terminal of the master control chip 30, the reset terminal of the master control chip 30 is high, the second terminal of the fifth switching device Q5 is high, the fifth switching device Q5 is on, and the second watchdog module 20 inputs the reset signal to the master control chip 30 to trigger the electronic device to restart.

[0082] In some embodiments, the master control chip 30 is specifically configured to close the first watchdog module inside the master control chip 30 in the case that the second terminal of the master control chip 30 is high, and open the first watchdog module in the case that the second terminal of the master control chip 30 is low.

[0083] In the embodiment of the utility model, the combination structure of the master control chip 30 and the third switching sub-module 13 and the fourth switching sub-module 14 is the redundant control structure, in the case that the third switching sub-module 13 or the fourth switching sub-module 14 is invalid, the fifth switching device Q5 can be controlled to be disconnected by the master control chip 30 in the case that the debugging interface 40 is electrically connected with the debugger 50, and the fifth switching device Q5 can be controlled to be on by the master control chip 30 in the case that the debugging interface 40 is empty.

[0084] Specifically, in some embodiments, the watchdog control circuit comprises a switch module 10 and a control port 101, the switch module 10 comprises a third switch submodule 13, a fourth switch submodule 14 and a fifth switch submodule 15; the third switch submodule 13 comprises a fourth resistor R4, a fifth resistor R5 and a third switch device Q3; the fourth switch submodule 14 comprises a sixth resistor R6, a seventh resistor R7 and a fourth switch device Q4; the fifth switch submodule 15 comprises an eighth resistor R8 and a fifth switch device Q5;

[0085] The first end of the fourth resistor R4 is electrically connected with the control port 101, and the second end of the fourth resistor R4 is electrically connected with the first end of the fifth resistor R5 and the control end of the third switch device Q3 respectively; the first end of the third switch device Q3 is electrically connected with the second end of the sixth resistor R6 and the control end of the fourth switch device Q4 respectively, and the second end of the third switch device Q3 is grounded; the second end of the fifth resistor R5 is grounded;

[0086] The first end of the sixth resistor R6 is used for being electrically connected with an external power supply, and the second end of the sixth resistor R6 is electrically connected with the control end of the fourth switch device Q4;

[0087] The first end of the fourth switch device Q4 is electrically connected with the second end of the eighth resistor R8 and the control end of the fifth switch device Q5 respectively, and the second end of the fourth switch device Q4 is electrically connected with the first end of the seventh resistor R7; the second end of the seventh resistor R7 is used for being electrically connected with an external power supply;

[0088] The first end of the eighth resistor R8 is grounded, and the second end of the eighth resistor R8 is electrically connected with the control end of the fifth switch device Q5; the first end of the fifth switch device Q5 is used for being electrically connected with the output end of the second watchdog module 20, and the second end of the fifth switch device Q5 is used for being electrically connected with the reset end of the main control chip 30;

[0089] The second end of the eighth resistor R8 is used for being electrically connected with the first end of the main control chip 30; the control end of the fifth switch device Q5 is used for being electrically connected with the first end of the main control chip 30; the control port 101 is used for being electrically connected with the debugging interface 40 of the main control chip 30, and the control port 101 is also used for being electrically connected with the second end of the main control chip 30.

[0090] Optionally, in some embodiments, the watchdog control circuit further comprises a ninth resistor R9; the first end of the ninth resistor R9 is electrically connected with the control port 101, and the second end of the ninth resistor R9 is used for being electrically connected with the second end of the main control chip 30.

[0091] In the embodiment of the utility model, ninth resistance R9 is current -limiting resistance, the second end of main control chip 30 is electrically connected with control port 101 through ninth resistance R9, to realize in the case that debugging interface 40 is electrically connected with debugger 50, control port 101 is high level, make the second end of main control chip 30 is high level, main control chip 30 closes the first watchdog module in main control chip 30, and in the case that debugging interface 40 is vacant, control port 101 is vacant, second resistance R2 or fifth resistance R5 pulls down the second end of main control chip 30 to low level, and main control chip 30 opens the first watchdog module.

[0092] The utility model embodiment further provides a kind of mainboard, including the watchdog control circuit as described above.

[0093] The implementation mode of watchdog control circuit in mainboard is similar to the implementation mode of the aforementioned watchdog control circuit, and will not be repeated here.

[0094] The utility model embodiment further provides an electronic device, including the watchdog control circuit as described above, or the mainboard as described above.

[0095] The implementation mode of watchdog control circuit in electronic device is similar to the implementation mode of the aforementioned watchdog control circuit, and will not be repeated here.

[0096] In some related technologies, after removing the watchdog circuit of the electronic device, the debugger is electrically connected with the electronic device, and then the debugger is used to debug the electronic device, to avoid the problem that the watchdog circuit triggers the electronic device to restart, resulting in debugging failure, after debugging, the watchdog circuit is reinstalled in the electronic device, however, the manual operation is complex, the work efficiency is low, and the electronic device is easily damaged.

[0097] In another related technology, the watchdog function of the electronic device is closed by software command, but the operation of software command is complex, the work efficiency is low, it is difficult to apply to electronic device that does not support software command, and the operation of software command is wrong, resulting in damage of electronic device.

[0098] In the embodiment of the utility model, through the control port 101 in the debugging interface 40 of main control chip 30 and the debugging device 50 electric connection, make the main control chip 30 close the first watchdog module in the main control chip 30, and through the switch module 10 in the debugging interface 40 and the debugging device 50 electric connection, make the second watchdog module 20 and the main control chip 30 disconnect, and then make the second watchdog module 20 send reset signal to the main control chip 30 failure, thereby closing the watchdog function of electronic equipment, without removing and installing the watchdog circuit and software command operation of electronic equipment, improve the work efficiency and the applicability to various types of electronic equipment, avoid electronic equipment damage.

[0099] In the embodiment of the utility model, through the control port 101 in the debugging interface 40 of main control chip 30 and the debugging device 50 electric connection, make the main control chip 30 close the first watchdog module in the main control chip 30, and through the switch module 10 in the debugging interface 40 and the debugging device 50 electric connection, make the second watchdog module 20 and the main control chip 30 disconnect, and then make the second watchdog module 20 send reset signal to the main control chip 30 failure, thereby closing the watchdog function of electronic equipment, avoid in prior art because of using the debugging device debugging electronic equipment, cause the watchdog circuit to trigger electronic equipment to restart, lead to the problem of debugging failure, improve the success rate of debugging.

[0100] Finally, it also needs to be explained that in this paper, such as "first" and "second" and other relational terms are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or terminal device.

[0101] The above only describes the preferred embodiments of the utility model, and does not limit the utility model, and any modification, equivalent replacement and improvement made within the spirit and principle of the utility model should be included in the protection scope of the utility model.

[0102] The above only describes the preferred embodiments of the utility model, and does not limit the utility model, and any modification, equivalent replacement and improvement made within the spirit and principle of the utility model should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be subject to the protection scope of claims.

Claims

1. A watchdog control circuit applied to debugging of a master control chip, characterized in that, The switch module (10) and the control port (101) are electrically connected with each other. The control port (101) is electrically connected with the master control chip (30) and a debugging interface (40) of the master control chip (30) respectively, and in the case that the debugging interface (40) is electrically connected with a debugger (50), the master control chip (30) is enabled to close a first watchdog module inside the master control chip (30); and in the case that the debugging interface (40) is vacant, the master control chip (30) is enabled to open the first watchdog module. The switch module (10) is electrically connected with the control port (101), and the switch module (10) is electrically connected with the master control chip (30) and a second watchdog module (20) outside the master control chip (30) respectively, in the case that the debugging interface (40) is electrically connected with the debugger (50), the switch module (10) is enabled to be disconnected, so that the second watchdog module (20) is disconnected with the master control chip (30); and in the case that the debugging interface (40) is vacant and the second watchdog module (20) outputs a reset signal, the switch module (10) is enabled to be connected, so that the second watchdog module (20) is connected with the master control chip (30).

2. The watchdog control circuit of claim 1, wherein, The switch module (10) comprises a first switch sub-module (11) and a second switch sub-module (12). The control end of the first switch sub-module (11) is electrically connected with the control port (101), the first end of the first switch sub-module (11) is electrically connected with the control end of the second switch sub-module (12), the second end of the first switch sub-module (11) is grounded, and the first switch sub-module (11) is used for being connected in the case that the debugging interface (40) is electrically connected with the debugger (50), and being disconnected in the case that the debugging interface (40) is vacant. The first end of the second switch sub-module (12) is used for being electrically connected with a reset end of the master control chip (30), the second end of the second switch sub-module (12) is used for being electrically connected with an output end of the second watchdog module (20), and the second switch sub-module (12) is used for being disconnected in the case that the first switch sub-module (11) is connected, and being connected in the case that the first switch sub-module (11) is disconnected and the output end of the second watchdog module (20) outputs the reset signal.

3. The watchdog control circuit of claim 2, wherein, The first switch sub-module (11) comprises a first resistor (R1), a second resistor (R2) and a first switch device (Q1). The first end of the first resistor (R1) is electrically connected with the control port (101), the second end of the first resistor (R1) is electrically connected with the first end of the second resistor (R2) and the control end of the first switch device (Q1) respectively. The first end of the first switch device (Q1) is electrically connected with the control end of the second switch sub-module (12), and the second end of the first switch device (Q1) is grounded. The second end of the second resistor (R2) is grounded.

4. The watchdog control circuit of claim 2, wherein, The second switch submodule (12) comprises a third resistor (R3) and a second switch device (Q2); The first end of the third resistor (R3) is electrically connected with an external power supply, and the second end of the third resistor (R3) is electrically connected with the first end of the first switch submodule (11) and the control end of the second switch device (Q2) respectively; The control end of the second switch device (Q2) is electrically connected with the first end of the first switch submodule (11), the first end of the second switch device (Q2) is electrically connected with the reset end of the main control chip (30), and the second end of the second switch device (Q2) is electrically connected with the output end of the second watchdog module (20).

5. The watchdog control circuit of claim 4, wherein, The second end of the third resistor (R3) is electrically connected with the first end of the main control chip (30); The control end of the second switch device (Q2) is electrically connected with the first end of the main control chip (30); The control port (101) is electrically connected with the second end of the main control chip (30); The main control chip (30) is configured to control the second switch device (Q2) to be disconnected when the debugging interface (40) is electrically connected with the debugger (50).

6. The watchdog control circuit of claim 1, wherein, The switch module (10) comprises a third switch submodule (13), a fourth switch submodule (14) and a fifth switch submodule (15); The control end of the third switch submodule (13) is electrically connected with the control port (101), the first end of the third switch submodule (13) is electrically connected with the control end of the fourth switch submodule (14), the second end of the third switch submodule (13) is grounded, the third switch submodule (13) is configured to be turned on when the debugging interface (40) is electrically connected with the debugger (50), and be turned off when the debugging interface (40) is vacant; The first end of the fourth switch submodule (14) is electrically connected with the control end of the fifth switch submodule (15), the second end of the fourth switch submodule (14) is electrically connected with an external power supply, and the fourth switch submodule (14) is configured to be turned on when the third switch submodule (13) is turned on, and be turned off when the third switch submodule (13) is turned off; The first end of the fifth switch submodule (15) is electrically connected with the output end of the second watchdog module (20), the second end of the fifth switch submodule (15) is electrically connected with the reset end of the main control chip (30), and the fifth switch submodule (15) is configured to be turned off when the fourth switch submodule (14) is turned on, and be turned on when the fourth switch submodule (14) is turned off and the output end of the second watchdog module (20) outputs the reset signal.

7. The watchdog control circuit of claim 6, wherein, The third switch submodule (13) comprises a fourth resistor (R4), a fifth resistor (R5) and a third switch device (Q3); A first end of the fourth resistor (R4) is electrically connected with the control port (101), and a second end of the fourth resistor (R4) is electrically connected with a first end of the fifth resistor (R5) and a control end of the third switch device (Q3) respectively; A first end of the third switch device (Q3) is electrically connected with a control end of the fourth switch sub-module (14), and a second end of the third switch device (Q3) is grounded; A second end of the fifth resistor (R5) is grounded.

8. The watchdog control circuit of claim 6, wherein, The fourth switch sub-module (14) comprises a sixth resistor (R6), a seventh resistor (R7) and a fourth switch device (Q4); A first end of the sixth resistor (R6) is configured to be electrically connected with an external power supply, and a second end of the sixth resistor (R6) is electrically connected with a first end of the third switch sub-module (13) and a control end of the fourth switch device (Q4) respectively; The control end of the fourth switch device (Q4) is electrically connected with the first end of the third switch sub-module (13), a first end of the fourth switch device (Q4) is electrically connected with a control end of the fifth switch sub-module (15), and a second end of the fourth switch device (Q4) is electrically connected with a first end of the seventh resistor (R7); A second end of the seventh resistor (R7) is configured to be electrically connected with the external power supply.

9. The watchdog control circuit of claim 6, wherein, The fifth switch sub-module (15) comprises an eighth resistor (R8) and a fifth switch device (Q5); A first end of the eighth resistor (R8) is grounded, and a second end of the eighth resistor (R8) is electrically connected with a first end of the fourth switch sub-module (14) and a control end of the fifth switch device (Q5) respectively; The control end of the fifth switch device (Q5) is electrically connected with the first end of the fourth switch sub-module (14), a first end of the fifth switch device (Q5) is configured to be electrically connected with an output end of the second watchdog module (20), and a second end of the fifth switch device (Q5) is configured to be electrically connected with a reset end of the main control chip (30).

10. The watchdog control circuit of claim 9, wherein, The second end of the eighth resistor (R8) is configured to be electrically connected with a first end of the main control chip (30); The control end of the fifth switch device (Q5) is configured to be electrically connected with the first end of the main control chip (30); The control port (101) is configured to be electrically connected with a second end of the main control chip (30); The main control chip (30) is configured to control the fifth switch device (Q5) to be disconnected in a case that the debugging interface (40) is electrically connected with the debugger (50).

11. The watchdog control circuit of claim 1, wherein, The watchdog control circuit further comprises a ninth resistor (R9); A first end of the ninth resistor (R9) is electrically connected with the control port (101), and a second end of the ninth resistor (R9) is configured to be electrically connected with a second end of the main control chip (30).

12. A main board, characterized by, The watchdog control circuit comprises any one of the watchdog control circuits according to any one of claims 1 to 11.

13. An electronic device, comprising: The mainboard comprises any one of the watchdog control circuits according to any one of claims 1 to 11 or the mainboard according to claim 12.

Images