Transistor structure

Abstract

The utility model provides a transistor structure, comprising an epitaxial layer having a first surface and a second surface opposite to each other; the first body region and the second body region are arranged in the epitaxial layer, the first body region and the second body region are oppositely arranged in a spaced mode in the first direction, and the first body region and the second body region extend in the second direction intersecting with the first direction; the reinforcing layer is located between the first body region and the second body region, and the reinforcing layer extends in the first direction; a first source region and a second source region, the first source region is embedded in the first body region, the second source region is embedded in the second body region, and the first source region and the second source region extend along the second direction; and the oxide layer extends along the second direction. According to the embodiment of the utility model, the conduction area of the epitaxial layer part is enhanced, and the channel width is not influenced, so that the reliability is improved, and the stability of the transistor structure is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field especially relates to a transistor structure. BACKGROUND

[0002] MOS structure (Metal-Oxide-Semiconductor, metal oxide semiconductor) is a kind of electronic device structure based on semiconductor material, MOS structure is composed of metal electrode, oxide layer and semiconductor layer etc. MOS structure has wide application scene, including but not limited to the following fields: integrated circuit, such as logic gate, memory and amplifier etc.;High-frequency electronic device;Communication field, such as radio frequency amplifier, signal mixer and other high-frequency electronic device;Power management, such as DC-DC converter, power inverter etc. The characteristics of MOS structure include high input impedance, low power consumption, large dynamic range, and strong integrability etc. In MOS structure device, compared with silicon MOS structure, the breakdown field of silicon carbide MOS structure can be several times of the latter, so high withstand voltage can be realized with low impedance and thin thickness. Even so, the continuous improvement of the reliability of silicon carbide MOS device is still an important research and technical development direction for the person skilled in the art. CONTENT OF UTILITY MODEL

[0003] To solve the technical problem of how to improve the reliability of transistor structure, the utility model provides a kind of transistor structure and the production method of transistor structure. The transistor structure is realized by the technical means of setting reinforcing layer, and the technical effect of enhancing the reliability of the transistor structure is realized.

[0004] The utility model discloses a kind of transistor structures, for example include: epitaxial layer, with opposite first surface and second surface;First body area and second body area, be set in the epitaxial layer, the first body area and the second body area are located in the epitaxial layer side close to the second surface, the first body area and the second body area are opposite and interval arrangement in first direction, the first body area and the second body area extend along the second direction crossing the first direction;Reinforcing layer, between the first body area and the second body area, the reinforcing layer extends along the first direction, the reinforcing layer is in contact with the first body area, the second body area and the epitaxial layer;First source area and second source area, the first source area is embedded in the first body area, the second source area is embedded in the second body area, the first source area is located in the first body area end close to the second surface, the second source area is located in the second body area end close to the second surface, the first source area and the second source area extend along the second direction;Oxidation layer, on the second surface, and extend along the second direction, the oxidation layer connects the epitaxial layer, the first body area, the second body area, the first source area, the second source area and the reinforcing layer;The first body area, the second body area and the doping concentration of the reinforcing layer are same;The first body area, the second body area and the doping type of the reinforcing layer are first doping type, the first source area, the second source area and the epitaxial layer are second doping type.

[0005] In an embodiment of the utility model, the number of reinforcing layer is multiple, and multiple reinforcing layer is arranged and interval arranged in the second direction.

[0006] In an embodiment of the utility model, further include: buffer layer, set in the epitaxial layer, the buffer layer is set between adjacent two reinforcing layers, the buffer layer is the second doping type, and the doping concentration of the buffer layer is different from the doping concentration of the epitaxial layer.

[0007] In an embodiment of the utility model, the doping concentration of the buffer layer is lower than the doping concentration of the first source area and the second source area, and the doping concentration of the epitaxial layer is lower than the doping concentration of the buffer layer.

[0008] In an embodiment of the utility model, the spacing range between adjacent two reinforcing layers is 0.1-10 microns.

[0009] In an embodiment of the utility model, the number range of impurity atoms per cubic centimeter of the buffer layer is 10 17 ~ 10 18 .

[0010] In one embodiment of the present application, the thickness of the buffer layer in the direction from the first surface to the second surface is less than the thickness of the reinforcing layer in the direction from the first surface to the second surface.

[0011] In one embodiment of the present application, the distance of the buffer layer in the direction from the first surface to the second surface ranges from 0.1 to 10 microns.

[0012] It can be seen from the above that the technical solution has at least one or more of the following beneficial effects:

[0013] The embodiment of the present application sets the reinforcing layer between the first body region and the second body region, sets the reinforcing layer to strengthen the partial conduction area of the epitaxial layer between the first body region and the second body region, does not affect the channel width, increases the distribution of the electric field, makes the electric field more uniform, reduces the electric field intensity near the channel surface, reduces the influence of the uneven electric field intensity on the transistor structure, reduces the risk of the oxide layer being broken down, improves the reliability of the transistor structure, and because the doping concentration and the doping type of the first body region, the second body region and the reinforcing layer are the same, the consistency and stability of the structure are ensured, the reliability is improved, and the stability of the transistor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 A structure diagram of a transistor structure is provided for the embodiments of the present application.

[0016] Figure 2 A three-dimensional structure diagram of a transistor structure is provided for the embodiments of the present application.

[0017] Figure 3 A three-dimensional structure diagram of an epitaxial region is provided for the embodiments of the present application. Figure 2

[0018] A top view diagram of an epitaxial region is provided for the embodiments of the present application. Figure 4 Figure 3 Another three-dimensional structure diagram of an epitaxial region is provided for the embodiments of the present application.

[0019] Figure 5 Figure 2 A three-dimensional structure diagram of an epitaxial region is provided for the embodiments of the present application.

[0020] Figure 6 A three-dimensional structure diagram of an epitaxial region is provided for the embodiments of the present application.​​Figure 5 A-A direction structure schematic view.

[0021] Figure 7 A-A direction structure schematic view. Figure 5 B-B direction structure schematic view.

[0022] Figure 8 A-A direction structure schematic view. B-B direction structure schematic view.

[0023] C-C direction structure schematic view. Figure 9 B-B direction structure schematic view. Figure 8 A-A direction structure schematic view. B-B direction structure schematic view.

[0024] C-C direction structure schematic view. Figure 10 B-B direction structure schematic view. Figure 8 C-C direction structure schematic view. B-B direction structure schematic view.

[0025] Main element number:

[0026] 10: transistor structure; 110: epitaxial layer; 101: first surface; 102: second surface; 210: first body region; 220: second body region; 121: first source region; 122: second source region; 230: reinforcing layer; 400: oxide layer; 130: buffer layer; 600: polysilicon. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0028] It should be noted that the terms "first", "second" and "one end" and the like in the specification and claims of the present application are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, products or devices.

[0029] Referring to Figure 1 , Figure 2 and Figure 3This utility model provides a transistor structure 10. The transistor structure 10 includes an epitaxial layer 110, a first body region 210 and a second body region 220, a first source region 121 and a second source region 122, an oxide layer 400 and a reinforcement layer 230.

[0030] Specifically, the epitaxial layer 110 has opposing first surfaces 101 and second surfaces 102. A first body region 210 and a second body region 220 are disposed within the epitaxial layer 110, located on the side of the epitaxial layer 110 closest to the second surface 102. The first body region 210 and the second body region 220 are disposed opposite to each other and spaced apart in a first direction, and extend along a second direction intersecting the first direction. See also... Figure 3 The reinforcing layer 230 is located between the first body region 210 and the second body region 220, and the reinforcing layer 230 extends along the first direction, see [reference needed]. Figure 4 , Figure 5 , Figure 6 and Figure 7 The reinforcing layer 230 contacts the first body region 210, the second body region 220, and the epitaxial layer 110. The first direction and the second direction are... Figure 2 The orientation is shown in the diagram. The first source region 121 and the second source region 122 are embedded in the first body region 210 and the second body region 220. The first body region 210 blocks the first source region 121 and the epitaxial layer 110, and the second body region 220 blocks the second source region 122 and the epitaxial layer 110. The first source region 121 is correspondingly disposed with the first body region 210, and the second source region 122 is correspondingly disposed with the second body region 220.

[0031] See Figure 2 An oxide layer 400 is located on the second surface 102 and extends along the second direction. The oxide layer 400 connects the epitaxial layer 110, the first body region 210, the second body region 220, the first source region 121, the second source region 122, and the reinforcing layer 230. The oxide layer 400 serves as an insulator and may be, for example, silicon dioxide. See also... Figure 1 and Figure 2 A polycrystalline silicon layer 600 is disposed above the oxide layer 400, and the polycrystalline silicon layer 600 may be, for example, polycrystalline silicon. The first body region 210, the second body region 220 and the reinforcing layer 230 have the same doping concentration. The first body region 210, the second body region 220 and the reinforcing layer 230 are doped with a first doping type, and the first source region 121, the second source region 122 and the epitaxial layer 110 are doped with a second doping type. The first doping type is, for example, P-type, and the second doping type is, for example, N-type.

[0032] The transistor structure 10 provided in this embodiment of the present invention is configured as follows: Figure 3The reinforcing layer 230 shown realizes the reinforcement of the part of the epitaxial layer 110 area which is partially conductive, without affecting the channel width, thereby improving the reliability, thereby improving the stability of the transistor structure 10.

[0033] Specifically, the channel width refers to the width of the conductive channel between the source and the drain in the structure of the silicon carbide MOS tube (such as a MOS tube), and in the embodiment of the utility model, when the channel width remains unchanged, by setting the reinforcing layer 230, the epitaxial layer 110 has a part of the area between the first body area 210 and the second body area 220 reinforced to increase the distribution of the electric field, so that the electric field is more uniform, and the electric field intensity near the channel surface is reduced, thereby reducing the influence of the non-uniform electric field intensity on the transistor structure 10. The setting of the reinforcing layer 230 makes the electric field distribution more uniform, reduces the electric field peak near the channel surface, and reduces the risk of breakdown of the oxide layer 400, thereby improving the reliability of the transistor structure 10, and since the first body area 210, the second body area 220 and the reinforcing layer 230 have the same doping concentration and the same doping type, it helps to ensure the consistency and stability of the structure, the embodiment of the utility model optimizes the electric field distribution, reduces the electric field peak, reduces the influence of the non-uniformity of the electric field intensity of the structure, and improves the reliability of the structure.

[0034] Further, referring to Figure 8 The number of reinforcing layers 230 is multiple, and the multiple reinforcing layers 230 are arranged and spaced apart in the second direction. The setting of multiple reinforcing layers 230 can disperse the electric field intensity to a larger area, and by setting multiple reinforcing layers 230, each reinforcing layer 230 can share the load of the electric field, thereby reducing the electric field intensity on a single reinforcing layer, reducing the concentration of the electric field, and the electric field can be dispersed between different layers and transmitted between them. This can reduce the intensity of the local electric field, reduce the risk of damage to the structure caused by the electric field, and reduce the electric field intensity near the channel surface, thereby reducing the influence of the non-uniform electric field intensity on the transistor structure 10, making the electric field distribution more uniform, reducing the electric field peak near the channel surface, reducing the risk of breakdown of the oxide layer 400, and further improving the reliability of the transistor structure 10.

[0035] Specifically, the spacing between two adjacent reinforcing layers 230 ranges from 0.1 to 10 microns. By adjusting the spacing, the electric field distribution between the reinforcing layers 230 can be adjusted. A smaller spacing can concentrate the electric field more, thereby improving the efficiency of current transmission, while a larger spacing can make the electric field distribution more uniform, thereby reducing the impact of the electric field on the structure. By adjusting the spacing, the electric field distribution can be optimized, improving the performance and reliability of the transistor structure 10. In addition, in high-density integrated circuits, the electric field between adjacent devices can interfere with each other, causing crosstalk effects. Setting an appropriate spacing can reduce the electric field coupling between adjacent reinforcing layers 230, thereby reducing the occurrence of crosstalk effects. This helps to improve the stability and reliability of the device. If the spacing between adjacent reinforcing layers 230 is too small, it can cause a short circuit in the structure. Proper spacing can effectively prevent such short circuit conditions from occurring, ensuring normal operation of the device. In summary, by setting the spacing between two adjacent reinforcing layers 230 in the range of 0.1 to 10 microns, the electric field distribution can be optimized, crosstalk effects can be reduced, and short circuits can be prevented. This helps to improve the performance, reliability, and stability of the transistor structure 10.

[0036] Referring to Figure 8 , Figure 9 and Figure 10 , the transistor structure 10 further comprises a buffer layer 130. The buffer layer 130 is disposed within the epitaxial layer 110, the buffer layer 130 is disposed between two adjacent reinforcing layers 230, the buffer layer 130 is of the second doping type, and the doping concentration of the buffer layer 130 is different from that of the epitaxial layer 110. By setting the buffer layer 130, the difference in electric field intensity between the epitaxial layer 110 and the reinforcing layer 230 is reduced. Since the doping concentration of the buffer layer 130 is different from that of the epitaxial layer 110, it can change the potential distribution between the epitaxial layer 110 and the reinforcing layer 230, thereby uniformizing the electric field distribution. Specifically, when there is a difference in electric field between the epitaxial layer 110 and the reinforcing layer 230, due to the presence of the buffer layer 130, the electric field will be distributed between the buffer layer 130 and the reinforcing layer 230, rather than being concentrated at the interface between the epitaxial layer 110 and the reinforcing layer 230. This reduces the electric field gradient between the epitaxial layer 110 and the reinforcing layer 230, reducing the electric field intensity, and optimizing the electric field distribution between the epitaxial layer 110 and the reinforcing layer 230, thereby improving the stability of the transistor structure 10.

[0037] Further, the doping concentration of the buffer layer 130 is lower than the doping concentration of the first source region 121 and the second source region 122, and the doping concentration of the epitaxial layer 110 is lower than the doping concentration of the buffer layer 130. Since the doping concentration of the buffer layer 130 is lower than the doping concentration of the first source region 121 and the second source region 122, the buffer layer 130 plays a buffering role in the electric field distribution. When an external voltage is applied to the structure, a gradual potential peak is formed between the epitaxial layer 110 and the buffer layer 130, and the electric field is gradually distributed in the buffer layer 130, thereby blocking the influence of the electric field on the first source region 121 and the second source region 122. In this way, the influence of the electric field strength on the source region can be reduced, and the reliability of the transistor structure 10 is improved. In addition, since the doping concentration of the epitaxial layer 110 is lower than the doping concentration of the buffer layer 130, the epitaxial layer 110 has a higher conductivity than the buffer layer 130. In this way, when an external voltage is applied to the structure, due to the higher conductivity of the epitaxial layer 110, the electric charges can flow more smoothly through the epitaxial layer 110, reducing the on-resistance and thereby reducing the heat generated when the transistor structure 10 as a power device is in forward conduction. Thus, the transistor structure 10 is more reliable. At the same time, the low doping concentration of the epitaxial layer 110 also reduces the influence of impurity concentration on the conductivity, so that such a setting not only reduces the influence of resistance, but also improves the reliability of the transistor structure 10. In summary, by setting the doping concentration of the buffer layer 130 to be lower than the doping concentration of the first source region 121 and the second source region 122, and the doping concentration of the epitaxial layer 110 to be lower than the doping concentration of the buffer layer 130, the difference in electric field strength can be reduced, thereby reducing the influence of the electric field on the source region and reducing the influence of resistance, and improving the reliability and stability of the transistor structure 10.

[0038] Specifically, the number of impurity atoms per cubic centimeter of the first body region 210 and the second body region 220 ranges from 10 17 The doping concentration of the buffer layer 130 ranges from 10 17 to 10 18 The thickness of the buffer layer 130 along the direction from the first surface 101 to the second surface 102 is, for example, less than the thickness of the reinforcing layer 230 along the direction from the first surface 101 to the second surface 102. Figure 8 , Figure 9 and Figure 10 When the reinforcing layer 230 is, for example,

[0039] The thickness of the buffer layer 130 along the direction from the first surface 101 to the second surface 102 is, for example, less than the thickness of the reinforcing layer 230 along the direction from the first surface 101 to the second surface 102.

[0040] Specifically, the doping concentration of the epitaxial layer 110 is, for example, in the order of 10 13 to 10 15 per cubic centimeter, the doping concentration of the buffer layer 130 is, for example, in the order of 10 17 to 10 19, and the doping concentration of the first source region 121 and the second source region 122 can be, for example, in the order of 10 19. By setting the buffer layer 130 with a higher doping concentration, the on-resistance of the transistor structure 10 can be reduced, thereby reducing the heat generated when the transistor structure 10 is used as a power device in a forward on-state, and thus making the transistor structure 10 more reliable.

[0041] In addition, it can be understood that the foregoing embodiments are only exemplary descriptions of the present application, and under the premise that the technical features do not conflict, are not contradictory, and do not violate the purpose of the present application, the technical solutions of each embodiment can be arbitrarily combined and used.

[0042] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present application.

Claims

1. A transistor structure (10) characterized by, The application relates to a semiconductor device, comprising: an epitaxial layer (110) having opposite first and second surfaces (101, 102); first and second body regions (210, 220) arranged in the epitaxial layer (110), the first and second body regions (210, 220) being located on a side of the epitaxial layer (110) close to the second surface (102), the first and second body regions (210, 220) being arranged opposite and spaced apart in a first direction, the first and second body regions (210, 220) extending in a second direction intersecting the first direction; a reinforcement layer (230) arranged between the first and second body regions (210, 220), the reinforcement layer (230) extending in the first direction, the reinforcement layer (230) being in contact with the first and second body regions (210, 220) and the epitaxial layer (110); first and second source regions (121, 122) embedded in the first and second body regions (210, 220), respectively, the first source region (121) being located at an end of the first body region (210) close to the second surface (102), the second source region (122) being located at an end of the second body region (220) close to the second surface (102), the first and second source regions (121, 122) extending in the second direction; an oxide layer (400) arranged on the second surface (102) and extending in the second direction, the oxide layer (400) connecting the epitaxial layer (110), the first and second body regions (210, 220), the first and second source regions (121, 122) and the reinforcement layer (230); the first and second body regions (210, 220) and the reinforcement layer (230) having the same doping concentration, the first and second body regions (210, 220) and the reinforcement layer (230) having a first doping type, and the first and second source regions (121, 122) and the epitaxial layer (110) having a second doping type.

2. The transistor structure (10) according to claim 1, characterized in that The reinforcement layer (230) has a plurality of reinforcement layers (230) arranged and spaced apart in the second direction.

3. The transistor structure (10) according to claim 2, characterized in that The application further relates to a semiconductor device, comprising: a buffer layer (130) arranged in the epitaxial layer (110), the buffer layer (130) being arranged between two adjacent reinforcement layers (230), the buffer layer (130) having the second doping type, and the buffer layer (130) having a doping concentration different from that of the epitaxial layer (110).

4. The transistor structure (10) according to claim 3, characterized in that The doping concentration of the buffer layer (130) is lower than that of the first and second source regions (121, 122), and the doping concentration of the epitaxial layer (110) is lower than that of the buffer layer (130).

5. The transistor structure (10) according to claim 2, characterized in that The interval between two adjacent reinforcing layers (230) ranges from 0.1 to 10 microns.

6. The transistor structure (10) according to claim 3, characterized in that The number of impurity atoms per cubic centimeter of the buffer layer (130) ranges from 10 17 ~ 10 18 .

7. The transistor structure (10) according to claim 3, characterized in that The thickness of the buffer layer (130) in the direction from the first surface (101) to the second surface (102) is less than the thickness of the reinforcing layer (230) in the direction from the first surface (101) to the second surface (102).

8. The transistor structure (10) according to claim 7, characterized in that The distance of the buffer layer (130) in the direction from the first surface (101) to the second surface (102) ranges from 0.1 to 10 microns.

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