Micromotor system structure

Abstract

A micro-electro-mechanical system (MEMS) structure is provided. In one embodiment, a MEMS structure includes a first fixed element, a second fixed element, a cover structure connecting the first fixed element and the second fixed element, and a movable element located between the first fixed element and the second fixed element and below the cover structure. The first spring includes a first layer exhibiting a tensile stress and a second layer exhibiting a compressive stress, and spans between the cover structure and the movable element. The second spring includes a third layer exhibiting a tensile stress and a fourth layer exhibiting a compressive stress, and spans between the first fixed element and the movable element. The first layer has a first thickness and the second layer has a second thickness of at least 50% of the first thickness.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a micro-electromechanical systems (MEMS) structure. BACKGROUND

[0002] Micro-electromechanical systems (MEMS) combine mechanical and electrical parts on a semiconductor structure. MEMS structures can be used as sensors, such as pressure sensors. SUMMARY

[0003] One aspect of the present disclosure discloses a micro-electromechanical systems (MEMS) structure. The MEMS structure includes a first fixed element, a second fixed element, a cap structure connecting the first fixed element and the second fixed element, and a movable element between the first fixed element and the second fixed element and below the cap structure. A first spring includes a first dielectric layer and a first conductive layer and the first spring spans between the cap structure and the movable element. A second spring includes a second dielectric layer and a second conductive layer and the second spring spans between the first fixed element and the movable element.

[0004] Another aspect of the present disclosure discloses a micro-electromechanical systems (MEMS) structure. The MEMS structure includes a first fixed element, a second fixed element, a cap structure connecting the first fixed element and the second fixed element, and a movable element between the first fixed element and the second fixed element and below the cap structure. A first spring includes a first tensile layer and a first compressive layer and the first spring spans between the cap structure and the movable element. A second spring includes a second tensile layer and a second compressive layer and the second spring spans between the first fixed element and the movable element. The first tensile layer has a first thickness and the first compressive layer has a second thickness that is at least 50% of the first thickness.

[0005] Yet another aspect of the present disclosure discloses a micro-electromechanical systems (MEMS) structure. The MEMS structure includes a first fixed element, a second fixed element, a cap structure connecting the first fixed element and the second fixed element, and a movable element between the first fixed element and the second fixed element and below the cap structure. A first spring includes a first dielectric layer, a first conductive layer, a buffer layer adjacent to the first conductive layer, a second dielectric layer adjacent to the buffer layer, and a second conductive layer adjacent to the second dielectric layer and the first spring spans between the cap structure and the movable element. A second spring includes a third dielectric layer and a third conductive layer and the second spring spans between the first fixed element and the movable element. BRIEF DESCRIPTION OF DRAWINGS

[0006] The various aspects of the present disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] Figures 1 to 27 Semiconductor devices are shown according to some embodiments illustrating various stages of fabrication;

[0008] Figure 28 Springs are shown according to some embodiments.

[0009] NOTATION

[0010] 100: semiconductor structure

[0011] 102: substrate layer

[0012] 104: interlayer dielectric layer

[0013] 106: bonding dielectric layer

[0014] 108: device

[0015] 110: gate dielectric layer

[0016] 112: gate electrode

[0017] 114: source / drain regions

[0018] 116: sidewall spacer

[0019] 118: gate capping layer

[0020] 119: STI structure

[0021] 120: conductive contact

[0022] 122: etch stop layer

[0023] 124: conductive structure

[0024] 126: conductive structure

[0025] 130: semiconductor layer

[0026] 132: bonding dielectric layer

[0027] 134: patterned mask

[0028] 136: cavity

[0029] 138: cavity

[0030] 140: semiconductor layer

[0031] 142: patterned mask

[0032] 144: Sacrificial isolation element

[0033] 146: Sacrificial isolation element

[0034] 146A: Sacrificial isolation element

[0035] 146B: Sacrificial isolation element

[0036] 146C: Sacrificial isolation element

[0037] 146D: Sacrificial isolation element

[0038] 148: Dielectric layer

[0039] 150: Conductive layer

[0040] 152: Conductive element

[0041] 154: Semiconductor layer

[0042] 156: Sacrificial isolation element

[0043] 158: Dielectric layer

[0044] 160: Conductive element

[0045] 162: Sacrificial isolation element

[0046] 163: Dielectric layer

[0047] 164: Semiconductor layer

[0048] 164A, 164C: Finger element, fixed element

[0049] 164B: Finger element, movable element

[0050] 164D, 164E: Finger element

[0051] 166: Dielectric layer

[0052] 168: Semiconductor layer

[0053] 170: Dielectric layer

[0054] 172: Semiconductor layer

[0055] 174, 176, 178, 179, 180: Offset structure

[0056] 182: Sidewall spacer

[0057] 184: Sidewall spacer

[0058] 186: Conductive capping structure

[0059] 188: electrically conductive covering structure

[0060] 190: electrically conductive element

[0061] 192: electrically conductive element

[0062] 194, 196, 198: spring

[0063] 199: MEMS structure

[0064] 200: spring

[0065] 202: dielectric layer

[0066] 204: electrically conductive layer

[0067] 206: buffer layer

[0068] 210: spring

[0069] 220: spring

[0070] H: height

[0071] T1, T2: thickness

[0072] X, Y, Z: axis DETAILED DESCRIPTION

[0073] The following detailed description is presented in connection with the appended drawings. Figure references have the same numerical designation and contain components throughout the drawings and the description thereof. Like reference numerals have been used to represent like elements throughout the description. The following detailed description is presented for the purposes of describing various embodiments and is not intended to limit the scope of the disclosure. For example, the following detailed description describes various embodiments in the context of a mobile device. However, the following detailed description is not intended to limit the scope of the disclosure to only mobile devices. Rather, the following detailed description is intended to apply to any device that can benefit from the disclosed subject matter. Moreover, the following detailed description is presented in the context of a number of different embodiments or examples, which are provided in the interest of clarity and for purposes of exemplification only. It is not intended to be a limitation on the scope of the disclosure. For example, the following detailed description describes a first feature on or over a second feature in the following text. This can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Additionally, the disclosure can repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0074] Furthermore, relative terms, such as "below," "lower," "bottom," "above," "upper," and the like can be used herein for ease of reference only. The terms "below," "lower," "bottom," "bottom portion," "above," "upper," and the like are used to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0075] According to some embodiments, a microelectromechanical system (MEMS) device is formed. A spring is formed between a fixed element and a movable element of the MEMS device to reduce sensitivity of the MEMS device to vibrations. In some embodiments, the spring includes alternating layers of metal and dielectric. In some embodiments, an organic layer is formed between the two sets of metal and dielectric layers. An annealing process is performed to induce stress into the layers. The dielectric layers exhibit compressive stress and the metal layers exhibit tensile stress, resulting in spring-like behavior. The spring can be formed in the x-direction, y-direction, and z-direction along the interface between the fixed element and the movable element of the MEMS device.

[0076] Figures 1 to 27 A semiconductor structure 100 is shown at various stages of fabrication according to some embodiments. Figures 1 to 27 A cross-sectional view of a semiconductor structure 100 is shown at various stages of fabrication according to some embodiments. In some embodiments, the semiconductor structure 100 is a MEMS device. The semiconductor structure 100 includes a substrate layer 102, an interlayer dielectric layer 104 over the substrate layer 102, and a bonding dielectric layer 106 over the interlayer dielectric layer 104. In some embodiments, the bonding dielectric layer 106 includes silicon dioxide. The bonding dielectric layer 106 provides an interface to bond to another semiconductor wafer.

[0077] The substrate layer 102 includes at least one epitaxial layer, a single crystalline semiconductor material, such as, but not limited to, at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, and InP, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the substrate layer 102 includes at least one of crystalline silicon or other suitable material. The substrate layer 102 can be a silicon-on-insulator (SOI) substrate that includes a layer of semiconductor material (e.g., silicon, germanium, etc.) formed over an insulator layer (e.g., buried oxide, etc.) that is formed in a silicon substrate. Other substrates that can be used include multilayer substrates, graded substrates, hybrid orientation substrates, etc., or combinations thereof. Other structures and / or configurations of the substrate layer 102 are within the scope of the present disclosure.

[0078] According to some embodiments, the semiconductor structure 100 includes devices 108 formed on or within the substrate layer 102. In some embodiments, the devices 108 each include a gate dielectric layer 110, a gate electrode 112, a source / drain region 114, a sidewall spacer 116, a gate cap layer 118, etc. According to some embodiments, the gate dielectric layer 110 and the gate electrode 112 are formed using a gate replacement process. A sacrificial gate structure is formed, where the sacrificial gate structure includes a sacrificial gate dielectric layer, a sacrificial gate electrode layer (e.g., a polysilicon layer), and a hardmask layer. In some embodiments, a patterning process is performed to pattern and a corresponding hardmask layer of the pattern of the gate structure to be formed, and an etching process is performed using the patterned hardmask layer to etch the sacrificial gate electrode layer and the sacrificial gate dielectric layer to define the sacrificial gate structure. In some embodiments, a remaining portion of the hardmask layer forms a cap layer over portions of the sacrificial gate electrode layer that remain after the etching process. The sacrificial gate structure is then replaced with a replacement gate dielectric layer (e.g., the gate dielectric layer 110) and a replacement gate electrode (e.g., the gate electrode 112).

[0079] In some embodiments, the gate dielectric layer 110 includes a high-k dielectric material. As used herein, the term "high-k dielectric" refers to a material having a dielectric constant k greater than or equal to about 3.9 (the k value of SiO2). The high-k dielectric material can be any suitable material. Examples of high-k dielectric materials include, but are not limited to, AI2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2O x N y , HfO x N y , ZrO x N y , La2O x N y , TiO x N y , HfO x N y , ZrO x N y , La2O x N y , TiO x N y , SiN x N, silicates thereof, and alloys thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. In some embodiments, an additional dielectric material layer, such as silicon dioxide, a high-k dielectric material, or other suitable material, is formed over the native oxide to form the gate dielectric layer 110.

[0080] In some embodiments, the gate electrode 112 includes a barrier layer, one or more work function material layers, a seed layer, a metal fill layer, or other appropriate layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, or other appropriate materials. In some embodiments, the gate dielectric layer 110 and one or more layers making up the gate electrode 112 are deposited by at least one of atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), molecular beam epitaxy (MBE), or other appropriate techniques. In some embodiments, the gate electrode 112 is recessed, and a gate cap layer 118 is formed in the recess.

[0081] In some embodiments, the sidewall spacers 116 are formed adjacent to the gate dielectric layer 110 and the gate electrode 112. In some embodiments, the sidewall spacers 116 are formed by depositing a spacer layer over the sacrificial gate structure, and performing an anisotropic etch process to remove horizontal portions of the spacer layer. In some embodiments, the sidewall spacers 116 include silicon nitride or other appropriate materials.

[0082] In some embodiments, the source / drain regions 114 are formed in the substrate layer 102 after the sacrificial gate structure is formed. For example, in some embodiments, portions of the substrate layer 102 are doped to form the source / drain regions 114 by a doping process. In some embodiments, an etch process is performed to recess the substrate layer 102 adjacent to the sidewall spacers 116, and an epitaxial growth process is performed to form the source / drain regions 114.

[0083] In one embodiment, one or more shallow trench isolation (STI) structures 119 are formed within the substrate layer 102. In some embodiments, the STI structures 119 are formed by forming at least one masking layer over the substrate layer 102. In some embodiments, the at least one masking layer includes an oxide material layer over the substrate layer 102 and a nitride material layer over the oxide material layer, and / or one or more other suitable layers. At least some of the at least one masking layer is removed to define an etch mask, which is used as a template to etch the substrate layer 102 to form trenches. A dielectric material is formed in the trenches to define the STI structures 119. In some embodiments, the STI structures 119 include multiple layers, such as an oxide liner, a nitride liner formed over the oxide liner, an oxide fill material formed over the nitride liner, and / or other suitable materials.

[0084] In some embodiments, the fill material, such as the oxide fill material, is formed using a high density plasma (HDP) process. The HDP process uses a precursor gas that includes at least one of silane (SiH4), oxygen, argon, or other suitable gas. The HDP process includes a deposition component that forms material on the surface defining the trenches and a sputtering component that removes or repositions the deposited material. The ratio of deposition to sputtering depends on the gas ratio employed during the deposition portion. According to some embodiments, argon and oxygen act as sputtering sources, and the specific values of the gas ratio are determined based on the aspect ratio of the trenches. After the fill material is formed, an anneal process is performed to densify the fill material. In some embodiments, the STI structures 119 generate compressive stress. In some embodiments, the STI structures 119 are formed before the devices 108. Other structures and / or configurations of the STI structures 119 are within the scope of this disclosure.

[0085] In some embodiments, the devices 108 are formed using the same materials and layer thicknesses. In some embodiments, different materials and / or thicknesses can be used due to different voltage domains. For example, the materials and / or thicknesses of the gate dielectric layers 110 can be different from one another. Although the devices 108 are shown adjacent to one another, in some embodiments, the devices 108 are formed in different regions. For example, if the thickness or material of the gate dielectric layers 110 varies, different devices 108 can be formed in different regions. In some embodiments, the materials of the gate electrodes 112 can also vary. Other structures and configurations of the devices 108 are within the scope of this disclosure. For example, the devices 108 can be fin field-effect transistors (finFET) devices, nanosheet devices, nanowire devices, or some other suitable devices.

[0086] In some embodiments, a portion of the ILD layer 104 is formed over the device 108. In some embodiments, the ILD layer 104 is formed prior to forming the replacement gate structure, if applicable. In some embodiments, the ILD layer 104 includes silicon dioxide or a low-k dielectric material. In some embodiments, the ILD layer 104 includes one or more layers of low-k dielectric material. The low-k dielectric material has a k value less than about 3.9. In some embodiments, the material of the ILD layer 104 includes at least one of Si, O, C, or H, such as SiCOH, SiOC, oxygen-doped SiC (ODC), nitrogen-doped silicon carbide (NDC), plasma-enhanced oxide (PEOX), or other suitable material. In some embodiments, the low-k dielectric material is further characterized or classified as ultra low-k (ULK), extra low-k (ELK), or extreme low-k (XLK), where the classification is generally based on the k value. For example, ULK generally refers to a material having a k value between about 2.7 and about 2.4, ELK generally refers to a material having a k value between about 2.3 and about 2.0, and XLK generally refers to a material having a k value less than about 2.0. Organic materials, such as polymers, can be used for the ILD layer 104. In some embodiments, the ILD layer 104 includes one or more layers of carbon-containing material, organosilicate glass, porogen-containing material, or a combination thereof. In some embodiments, the ILD layer 104 includes nitrogen. In some embodiments, the ILD layer 104 is formed using, for example, at least one of CVD, PECVD, LPCVD, ALCVD, spin-on techniques, or some other suitable process.

[0087] In some embodiments, the semiconductor structure 100 includes one or more conductive contacts 120 formed in the ILD layer 104. The conductive contacts 120 are formed in a variety of ways, such as through a single damascene process, a dual damascene process, a trench silicide process, or some other suitable process. In some embodiments, the conductive contacts 120 contact the gate electrode 112 and form additional contacts (not shown) to contact the source / drain regions 114 at different locations along the axial length of the device 108, such as into or out of the page. In some embodiments, the conductive contacts 120 include a barrier layer, a seed layer, a metal fill layer, or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, or other suitable material. In some embodiments, the device 108, the conductive contacts 120, and the ILD layer 104 define a device layer of the semiconductor structure 100. Other structures and configurations of the conductive contacts 120 are within the scope of the present disclosure.

[0088] In some embodiments, the semiconductor structure 100 includes one or more metallization layers in the interlayer dielectric layer 104 above the device layer. Any number of metallization layers can be contemplated. In some embodiments, different metallization layers are separated by etch stop layers 122 to allow etch control to form various conductive structures 124, 126 in the interlayer dielectric layer 104. The etch stop layers 122 include a dielectric material having a different etch selectivity than the interlayer dielectric layer 104. In some embodiments, at least one of the etch stop layers 122 includes SiN, SiCN, SiCO, CN, etc., alone or in combination. The etch stop layers 122 are formed in a variety of ways, such as through thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process.

[0089] The conductive structures extend through respective portions of the interlayer dielectric layer 104 in the associated metallization layers. In some embodiments, some of the conductive structures 124 include conductive lines, and the conductive structures 126 include conductive vias. In some embodiments, the conductive structures 124, 126 include barrier layers, seed layers, metal fill layers, or other appropriate layers. In some embodiments, the metal fill layers include tungsten, aluminum, copper, cobalt, or other appropriate materials. Other structures and configurations of the conductive structures 124, 126 are within the scope of the present disclosure.

[0090] In some embodiments, the device 108 is circuitry implemented by a portion of the semiconductor structure 100. In some embodiments, the circuitry includes sensor circuitry including at least one of an image sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS), a backside CIS, a proximity sensor, a time of flight (ToF) sensor, an indirect ToF (iToF) sensor, a backside illumination (BSI) sensor, or other types of sensors. In some embodiments, the circuitry includes logic circuitry, light-emitting diode (LED) circuitry, liquid-crystal display (LCD) circuitry, random access memory (RAM) circuitry, or other types of circuitry. Other structures and / or configurations of the semiconductor structure 100 are within the scope of the present disclosure.

[0091] Reference is made to Figure 2According to some embodiments, a semiconductor layer 130 is bonded to the bonding dielectric layer 106. The semiconductor layer 130 can be provided as a separate semiconductor wafer or die formed from a semiconductor wafer. The semiconductor layer 130 can include at least one epitaxial layer, a single crystalline semiconductor material such as, but not limited to, at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, or InP. During a bonding process to attach the semiconductor layer 130 to the bonding dielectric layer 106, heat and / or pressure can be applied to the semiconductor layer 130 such that a bond is formed between the semiconductor layer 130 and the bonding dielectric layer 106. Other substrates that can be used include multilayer substrates, graded substrates, hybrid orientation substrates, etc., or combinations thereof. Other structures and / or configurations of the semiconductor layer 130 are within the scope of the present disclosure.

[0092] Reference is made to Figure 3According to some embodiments, a bonding dielectric layer 132 is formed over the semiconductor layer 130, and a patterned mask 134 is formed over the bonding dielectric layer 132. In some embodiments, the bonding dielectric layer 132 is formed over the semiconductor layer 130 prior to bonding the semiconductor layer 130 to the bonding dielectric layer 106. Alternatively, the bonding dielectric layer 132 can be formed after bonding the semiconductor layer 130 to the bonding dielectric layer 106. The bonding dielectric layer 132 can be silicon dioxide. The patterned mask 134 can include a single layer, such as a photoresist layer, or multiple separately formed layers that collectively define the mask stack. In some embodiments, the mask stack includes at least one of a hard mask layer, a bottom antireflective coating (BARC) layer, an organic planarization layer (OPL), or a photoresist layer. The hard mask layer is formed by at least one of PVD, CVD, spin coating, growth, or other suitable technique. In some embodiments, the hard mask layer includes at least one of silicon (e.g., polysilicon), oxygen, nitrogen, or other suitable material. In some embodiments, the BARC layer is a polymer layer applied using a spin-on process. In some embodiments, the OPL includes a photosensitive organic polymer applied using a spin-on process. In some embodiments, the OPL includes a dielectric layer. In some embodiments, the photoresist layer is formed by at least one of spin coating, spray coating, or other suitable technique. The photoresist can be a negative photoresist or a positive photoresist. For a negative photoresist, when illuminated by a light source, the regions of the negative photoresist become insoluble, such that applying a solvent to the negative photoresist during a subsequent development stage removes the unilluminated regions of the negative photoresist. Thus, the pattern formed in the negative photoresist is a negative image of the pattern defined by the opaque regions of the template (e.g., mask) between the light source and the negative photoresist. In a positive photoresist, the illuminated regions of the positive photoresist become soluble and are removed by applying a solvent during a development process. Thus, the pattern formed in the positive photoresist is a positive image of the opaque regions of the template (e.g., mask) between the light source and the positive photoresist. One or more etchants are selective such that the one or more etchants remove or etch away one or more layers exposed or not covered by the photoresist at a greater rate. Thus, the openings in the photoresist allow the one or more etchants to form corresponding openings in the one or more layers beneath the photoresist, thereby transferring the pattern in the photoresist to the one or more layers beneath the photoresist. After the pattern is transferred, the photoresist is stripped or washed away. The layers of the mask stack are patterned to define the patterned mask 134. In some embodiments, a radiation source and a mask plate are used to expose the photoresist layer to define a pattern in the photoresist layer, and a portion of the photoresist layer is removed to define a patterned photoresist layer. The patterned photoresist layer is used as a template to etch the underlying OPL, BARC layer, and hard mask layer to form the patterned mask 134 and expose portions of the bonding dielectric layer 132 beneath the patterned mask 134.

[0093] Referring to Figure 4 According to some embodiments, cavities 136, 138 are formed in the bonded dielectric layer 132 and the semiconductor layer 130. The cavities 136, 138 can be formed by performing an etching process using the patterned mask 134 as an etching template. The etching process can be a timed etching process.

[0094] Referring to Figure 5 According to some embodiments, the patterned mask 134 is removed, and a semiconductor layer 140 is bonded to the bonded dielectric layer 132. The semiconductor layer 140 can be provided as a separate wafer, or die formed from a wafer. The semiconductor layer 140 can include at least one epitaxial layer, a single crystalline semiconductor material, such as, but not limited to, at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, or InP. During a bonding process to attach the semiconductor layer 140 to the bonded dielectric layer 132, heat and / or pressure can be applied to the semiconductor layer 140 such that a bond is formed between the semiconductor layer 140 and the bonded dielectric layer 132. Other substrates that can be used include multilayer substrates, graded substrates, hybrid orientation substrates, etc., or combinations thereof. Other structures and / or configurations of the semiconductor layer 140 are within the scope of the present disclosure.

[0095] Referring to Figure 6 According to some embodiments, a patterned mask 142 is formed over the semiconductor layer 140, and sacrificial isolation elements 144, 146 are formed in the semiconductor layer 140. The patterned mask 142 can be a photoresist mask or a stack of mask layers, including at least one of a hard mask layer, a BARC layer, an OPL, or a photoresist layer, including materials and formation as described herein. The sacrificial isolation elements 144, 146 can be formed by performing an etching process using the patterned mask 142 as an etching template to remove portions of the semiconductor layer 140. The etching process can be a timed etching process. The sacrificial isolation elements 144, 146 can have different widths.

[0096] Referring to Figure 7According to some embodiments, the patterned mask 142 is removed, and the height of the sacrificial isolation elements 144 is reduced. In some embodiments, a chamfering process is performed to reduce the height of the sacrificial isolation elements 144. According to some embodiments, the chamfering process includes forming a mask over the sacrificial isolation elements 146, depositing a sacrificial material between the sacrificial isolation elements 144, performing a first etching process selective to the sacrificial material to expose portions of the sacrificial isolation elements 144 to be removed, performing a second etching process to remove the exposed portions of the sacrificial isolation elements 144, and performing an etching and / or ashing process to remove the sacrificial material. Another technique for forming the sacrificial isolation elements 144 having a reduced height compared to the sacrificial isolation elements 146 is to form the sacrificial isolation elements 144 using a different mask and etching process than the mask and etching process used to form the sacrificial isolation elements 146.

[0097] Referring to Figure 8 According to some embodiments, a dielectric layer 148 is formed over the sacrificial isolation elements 144, 146. In some embodiments, the dielectric layer 148 is silicon dioxide. The dielectric layer 148 can be formed using, for example, at least one of a CVD, PECVD, LPCVD, ALCVD, spin-on technique, or some other suitable process.

[0098] Referring to Figure 9 According to some embodiments, a conductive layer 150 is formed between the sacrificial isolation elements 144, 146. In some embodiments, the conductive layer includes aluminum. The conductive layer 150 can be formed using a CVD process, a PVD process, an electroplating process, or some other suitable process.

[0099] Referring to Figure 10 According to some embodiments, the conductive layer 150 is recessed to form conductive elements 152 over the dielectric layer 148 on the sacrificial isolation elements 144. The conductive elements 152 can be formed using one or more mask and etching processes that remove a portion of the conductive layer 150 between the sacrificial isolation elements 144 while leaving the conductive elements 152.

[0100] Referring to Figure 11According to some embodiments, a semiconductor layer 154 is formed over the conductive element 152, over the dielectric layer 148, and between the sacrificial isolation elements 144, 146. The semiconductor layer 154 includes at least one epitaxial layer, a single-crystalline semiconductor material, such as, but not limited to, at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, and InP, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the semiconductor layer 154 includes at least one of crystalline silicon or other suitable material.

[0101] Referring to Figure 12 According to some embodiments, the semiconductor layer 154 is patterned to form a sacrificial isolation element 156 over the conductive element 152. In some embodiments, the sacrificial isolation element 156 is formed by planarizing the semiconductor layer 154 to remove portions of the semiconductor layer 154 over the upper surface of the dielectric layer 148, forming a patterned etch mask over a portion of the semiconductor layer 154 over the conductive element 152, and performing an etching process to remove a portion of the semiconductor layer 154 not covered by the patterned etch mask.

[0102] Referring to Figure 13 According to some embodiments, the sacrificial isolation element 156 is recessed. The sacrificial isolation element 156 can be recessed by performing a timed anisotropic etching process.

[0103] Referring to Figure 14 According to some embodiments, a dielectric layer 158 is formed over the sacrificial isolation element 156 and the conductive element 152. In some embodiments, the dielectric layer 158 is silicon dioxide. The dielectric layer 158 can be formed using, for example, at least one of CVD, PECVD, LPCVD, ALCVD, spin-on techniques, or some other suitable process. For ease of illustration, thickening of the dielectric layer 148 due to formation of the dielectric layer 158 is not shown.

[0104] According to some embodiments, referring to Figure 15 The processes shown in Figures 9 to 14 are repeated to form a conductive element 160, a sacrificial isolation element 162 over the conductive element 160, and a dielectric layer 163 over the sacrificial isolation element 162 and the conductive element 160.

[0105] According to some embodiments, referring to Figure 16semiconductor layer 164 is formed over the dielectric layers 148, 158, 163 between the sacrificial isolation elements 144, 146. In some embodiments, the semiconductor layer 164 exhibits a different etch selectivity with respect to the sacrificial isolation elements 144, 146, 156, 162. The semiconductor layer 164 can include polysilicon, and the sacrificial isolation elements 144, 146, 156, 162 can include silicon.

[0106] According to some embodiments, with reference to Figure 17 The semiconductor layer 164 is recessed and a dielectric layer 166 is formed at the recess. In some embodiments, the dielectric layer 166 is silicon dioxide. The dielectric layer 166 can be formed by using, for example, at least one of CVD, PECVD, LPCVD, ALCVD, spin-on techniques, or some other suitable process.

[0107] According to some embodiments, with reference to Figure 18 A portion of the dielectric layers 148, 163, and 166 is removed. The portion of the dielectric layers 148, 163, and 166 can be removed by performing an etching process with a patterned mask. After the removal process, the sacrificial isolation element 162 and the sacrificial isolation elements 146A, 146B are exposed.

[0108] According to some embodiments, with reference to Figure 19 A semiconductor layer 168 is formed over the dielectric layers 148, 166 and the sacrificial isolation elements 146A, 146B, 162. In some embodiments, the semiconductor layer 168 exhibits a different etch selectivity with respect to the sacrificial isolation elements 144, 146A, 146B, 156, 162. The semiconductor layer 168 can include polysilicon.

[0109] According to some embodiments, with reference to Figure 20 A dielectric layer 170 is formed over the semiconductor layer 168. In some embodiments, the dielectric layer 170 is silicon dioxide. The dielectric layer 170 can be formed by using, for example, at least one of CVD, PECVD, LPCVD, ALCVD, spin-on techniques, or some other suitable process.

[0110] According to some embodiments, with reference to Figure 21 A portion of the dielectric layer 170 not disposed over the sacrificial isolation element 146C, the sacrificial isolation element 146D is removed to expose a portion of the semiconductor layer 168, and a semiconductor layer 172 is formed over the dielectric layer 170 and the semiconductor layer 168. In some embodiments, the semiconductor layer 172 includes polysilicon.

[0111] According to some embodiments, with reference to Figure 22, a portion of the semiconductor layers 168, 172 is removed to define offset structures 174, 176, 178, 179, 180 in the remaining portions of the semiconductor layers 168, 172 and a portion of the semiconductor layer 172 over the dielectric layer 170 is removed. For ease of illustration, the semiconductor layers 168, 172 are shown merged into the offset structures 174, 176, 178, 179, 180.

[0112] According to some embodiments, referring to Figure 23 An enlarged view of a portion of the semiconductor structure 100 is shown, in which the offset structures 174, 176, 178, 179, 180 are shown. A portion of the semiconductor layer 164 adjacent to the sacrificial isolation elements 144, 146, 156, 162 defines finger elements 164A, 164B, 164C, 164D, 164E of a comb structure of the MEMS device. The offset structure 174 is over the dielectric layer 166, the offset structure 176 is over the sacrificial isolation elements 146A, 146B, the offset structures 178, 179 are over the conductive element 160, and the offset structure 180 is over the finger element 164B.

[0113] According to some embodiments, referring to Figure 24 , sidewall spacers 182, 184 are formed over the offset structures 179, 180, respectively. In some embodiments, the sidewall spacers 182, 184 are formed by depositing a layer of dielectric material and performing an etching process in the presence of a patterned mask to remove a portion of the dielectric material not disposed on sidewall surfaces of the offset structures 179, 180. In some embodiments, the sidewall spacers 182, 184 comprise silicon dioxide or another suitable dielectric material.

[0114] According to some embodiments, referring to Figure 25 , conductive cap structures 186 are formed over the offset structures 176, 178, 179, 180 and the finger elements 164A, 164B, 164C, and conductive cap structures 188 are formed over the finger elements 164D, 164E.

[0115] The conductive capping structures 186, 188 can be formed by forming a conductive layer over the dielectric layer 166, the offset structures 174, 176, 178, 179, 180, and the finger elements 164A, 164B, 164C, 164D, 164E, and performing an etching process to remove a portion of the conductive layer over the dielectric layer 166 and the offset structures 174, 176 in the presence of a patterned mask. The conductive layer can be formed using a CVD process, a PVD process, an electroplating process, or some other suitable process. In some embodiments, the conductive capping structures 186, 188 comprise aluminum. The conductive capping structure 186 includes a conductive element 190 adjacent to the sidewall spacer 182 and a conductive element 192 adjacent to the sidewall spacer 184.

[0116] According to some embodiments, with reference to Figure 26 the sacrificial isolation elements 144, 146A, 146B, 156, 162 and the offset structures 174, 176, 178, 179, 180 are removed. The sacrificial isolation elements 144, 146A, 146B, 156, 162 and the offset structures 174, 176, 178, 179, 180 can be removed using one or more selective etching processes, such as a wet etching process or an ashing process.

[0117] According to some embodiments, with reference to Figure 27 an annealing process is performed to form springs 194, 196, 198, where the spring 194 spans between the conductive capping structure 186 and the finger element 164B, the spring 196 spans between the finger elements 164A, 164B, and the spring 198 spans between the finger elements 164B, 164C. The spring 194 is formed by the conductive elements 190, 192 and the sidewall spacers 182, 184. The springs 196, 198 are formed by the conductive elements 152, 160 and the horizontal portions of the dielectric layers 148, 158 adjacent to the conductive elements 152, 160. The spacing between the springs 194 is approximately 1.0 pm, corresponding to a critical dimension (CD) of the patterning process performed to form the offset structures 179, 180 and the sidewall spacers 182, 184. The CD can be scalable.

[0118] Finger elements 164A, 164B, 164C, 164D, 164E are part of a MEMS structure 199. Finger elements 164A, 164C, which are connected to conductive cap structure 186, are fixed elements of MEMS structure 199. Finger element 164B is one of a plurality of movable elements of MEMS structure 199. Finger elements 164A, 164B, 164C, 164D, 164E can be part of a comb structure, with fixed finger elements 164A, 164C and movable finger elements 164B interleaved. Springs 196, 198 reduce the movement of movable finger element 164B in a lateral direction (x or y direction), and spring 194 reduces the movement of movable finger element 164B in a vertical direction (z direction). Additional springs can be formed using the techniques described herein to provide additional springs spanning between fixed finger elements 164A, 164C and movable finger elements 164B in a lateral direction that is not visible in Figure 27 but is perpendicular to the lateral direction shown in Figure 27 .

[0119] Referring to Figure 28 , a diagram of springs 200, 210, 220 is provided in accordance with some embodiments. Springs 194, 196, 198 can have a similar structure to any of springs 200, 210, 220. Spring 200 includes a dielectric layer 202 and a conductive layer 204, such as a metal layer (aluminum). In Figure 27During the annealing process, compressive stress is induced in the dielectric layers 202 and tensile stress is induced in the conductive layers 204. The counter stress produces a spring-like behavior for the composite structure including the dielectric layers 202 and the conductive layers 204. In some embodiments, the stress angle of the spring 200 is about 15°. The stress angle can vary as a function of the operating temperature of the device including the semiconductor structure 100, for example, the stress angle can increase with temperature. The Young’s modulus of the spring 200, 210, 220 can be at least about 70 GPa. In some embodiments, the thickness T1 of the dielectric layers 202 and the thickness T2 of the conductive layers 204 is about 0.3-0.7 μm, for example, 0.5 μm. The height H of the spring 200, 210, 220 can be about 1.4-2 μm, for example, 1.6 μm. The height H can be scalable. The thickness T1, T2 can be different. In some embodiments, the thickness T1 of the dielectric layers 202 is at least 50% of the thickness T2 of the conductive layers 204, to distinguish from any native dielectric layer that can form on the exposed conductive material of the conductive layers 204 during processing, for example, as aluminum oxide, where the conductive layers 204 include aluminum. In some embodiments, the dielectric layers 202 include silicon and oxygen. The thickness T1, T2 can be non-uniform for different dielectric layers 202, conductive layers 204 in the same spring 200, 210, 220. For example, the thickness of the end layers of the dielectric layers 202 and / or the conductive layers 204 of the springs 210, 220 can be greater than the thickness of the dielectric layers 202 and / or the conductive layers 204 between the end layers. The thickness T1, T2 can be non-uniform over the height H. For example, the ends of the dielectric layers 202, conductive layers 204 can be thicker than the middle portions of the dielectric layers 202, conductive layers 204, where the middle portions of the dielectric layers 202, conductive layers 204 can have a combined thickness of > 1 μm, and the ends of the dielectric layers 202, conductive layers 204 can have a combined thickness of > 2 μm.

[0120] The spring 210 includes a stack of alternating dielectric layers 202 and conductive layers 204. The number of layers can vary, and any number of layers can be used. The thickness and thickness profile of the dielectric layers 202 and the conductive layers 204 can vary.

[0121] The spring 220 includes a stack of alternating pairs of dielectric layers 202 and conductive layers 204 separated by a buffer layer 206. In some embodiments, the buffer layer is an organic material that adjusts the stress angle. The number of pairs of dielectric layers 202, conductive layers 204, and intervening buffer layers 206 can vary. The thickness and thickness profile of the dielectric layers 202, conductive layers 204, buffer layers 206 can vary.

[0122] Providing springs 194, 196, 198 between the fixed elements 164A, 164C and the movable element 164B of the MEMS structure 199 reduces the sensitivity of the MEMS structure 199 to vibrations. Reducing the sensitivity of the MEMS structure 199 to vibrations can increase the accuracy of the MEMS structure 199.

[0123] In some embodiments, a micro-electromechanical systems (MEMS) structure is provided. The MEMS structure includes a first fixed element, a second fixed element, a cap structure connecting the first fixed element and the second fixed element, and a movable element between the first fixed element and the second fixed element and below the cap structure. A first spring includes a first dielectric layer and a first conductive layer and spans between the cap structure and the movable element. A second spring includes a second dielectric layer and a second conductive layer and spans between the first fixed element and the movable element. The first dielectric layer and the second dielectric layer include silicon and oxygen.

[0124] In some embodiments, the MEMS structure includes a third spring including a third dielectric layer and a third conductive layer and spanning between the second fixed element and the movable element, where the third dielectric layer includes silicon and oxygen. In some embodiments, the first conductive layer has a first thickness and the first dielectric layer has a second thickness that is at least 50% of the first thickness. In some embodiments, a third spring is included adjacent to the first spring and spans between the cap structure and the movable element, and a fourth spring is included adjacent to the second spring and spans between the first fixed element and the movable element. In some embodiments, the first spring includes a third dielectric layer adjacent to the first conductive layer and a third conductive layer adjacent to the third dielectric layer. In some embodiments, the first spring includes a buffer layer adjacent to the first conductive layer, a third dielectric layer adjacent to the buffer layer, and a third conductive layer adjacent to the third dielectric layer. In some embodiments, the first conductive layer exhibits tensile stress and the first dielectric layer exhibits compressive stress.

[0125] In some embodiments, a MEMS structure is provided. The MEMS structure includes a first fixed element, a second fixed element, a cap structure connecting the first fixed element and the second fixed element, and a movable element between the first fixed element and the second fixed element and below the cap structure. A first spring includes a first tensile layer and a first compressive layer and spans between the cap structure and the movable element. A second spring includes a second tensile layer and a second compressive layer and spans between the first fixed element and the movable element. The first tensile layer has a first thickness and the first compressive layer has a second thickness that is at least 50% of the first thickness.

[0126] In some embodiments, the MEMS structure includes a third spring including a third compressive layer and a third tensile layer, and the third spring spans between the second fixed element and the movable element. In some embodiments, the MEMS structure includes a third spring adjacent to the first spring and spanning between the cap structure and the movable element, and a fourth spring adjacent to the second spring and spanning between the first fixed element and the movable element. In some embodiments, the first spring includes a third tensile layer adjacent to the first compressive layer and a third compressive layer adjacent to the third tensile layer. In some embodiments, the first spring includes a buffer layer adjacent to the first tensile layer, a third compressive layer adjacent to the buffer layer, and a third tensile layer adjacent to the third compressive layer.

[0127] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fixed element, forming a second fixed element, forming a cap structure connecting the first fixed element and the second fixed element, and forming a movable element between the first fixed element and the second fixed element and below the cap structure. A first sacrificial isolation element is formed between the first fixed element and the movable element. A first dielectric layer spanning between the cap structure and the movable element is formed. A first conductive layer adjacent to the first dielectric layer and spanning between the cap structure and the movable element is formed. A second dielectric layer is deposited over the first sacrificial isolation element and spans between the first fixed element and the movable element. A second conductive layer is formed over the second dielectric layer and spans between the first fixed element and the movable element. The first sacrificial isolation element is removed. An annealing process is performed to induce tensile stress in the first conductive layer and the second conductive layer and to induce compressive stress in the first dielectric layer and the second dielectric layer to form a first spring including the first dielectric layer and the first conductive layer and a second spring including the second dielectric layer and the second conductive layer.

[0128] In some embodiments, a second sacrificial isolation element is formed between the second fixed element and the movable element; a third dielectric layer is deposited over the second sacrificial isolation element across between the second fixed element and the movable element; and a third conductive layer is formed over the third dielectric layer and the third conductive layer is across between the second fixed element and the movable element; wherein performing the anneal process comprises: performing the anneal process to induce tensile stress in the third conductive layer and induce compressive stress in the third dielectric layer to form a third spring, wherein the third spring comprises the third conductive layer and the third dielectric layer, and the third spring is across between the second fixed element and the movable element. In some embodiments, the method comprises forming a second sacrificial isolation element over the second conductive layer; depositing a third dielectric layer over the second sacrificial isolation element; forming a third conductive layer over the third dielectric layer; and removing the second sacrificial isolation element prior to performing the anneal process; wherein performing the anneal process comprises: performing the anneal process to induce tensile stress in the third conductive layer and induce compressive stress in the third dielectric layer to form a third spring, wherein the third spring comprises the third conductive layer and the third dielectric layer, and the third spring is across between the second fixed element and the movable element. In some embodiments, depositing the first dielectric layer comprises: depositing the first dielectric layer comprising silicon and oxygen. In some embodiments, comprising forming the first conductive layer comprises forming the first conductive layer having a first thickness, and forming the first dielectric layer comprises forming the first dielectric layer having a second thickness, wherein the second thickness is at least 50% of the first thickness.

[0129] In some embodiments, a first offset structure is formed over the movable element; a first sidewall spacer is formed to define a first dielectric layer, wherein the first sidewall spacer is adjacent to the first offset structure; a cap structure is formed over the first offset structure, wherein the cap structure includes a first conductive element to define a first conductive layer, the cap structure is adjacent to the first sidewall spacer; and the first offset structure is removed before performing the annealing process. In some embodiments, a second sacrificial isolation element is formed between the second fixed element and the movable element; a second offset structure is formed over the second sacrificial isolation element; a second sidewall spacer is formed adjacent to the second offset structure; a cap structure is formed over the first offset structure and the second offset structure, the cap structure includes a second conductive element adjacent to the second sidewall spacer; and the second offset structure is removed before performing the annealing process; wherein performing the annealing process includes: performing the annealing process to induce tensile stress in the third conductive layer and induce compressive stress in the third dielectric layer to form a third spring, wherein the third spring includes the third conductive layer and the third dielectric layer, and the third spring spans between the second fixed element and the movable element. In some embodiments, forming the first conductive layer and forming the first dielectric layer includes forming a stack of alternating plurality of conductive layers and plurality of dielectric layers; and performing the annealing process includes performing the annealing process to induce tensile stress in the conductive layers in the stack, and induce compressive stress in the dielectric layers in the stack.

[0130] In some embodiments, a microelectromechanical system structure is provided. The microelectromechanical system structure includes a first fixed element, a second fixed element, a cap structure connecting the first fixed element and the second fixed element, and a movable element between the first fixed element and the second fixed element and below the cap structure. A first spring includes a first dielectric layer and a first conductive layer and spans between the cap structure and the movable element. A second spring includes a second dielectric layer and a second conductive layer and spans between the first fixed element and the movable element.

[0131] In some embodiments, the microelectromechanical system structure includes a third spring, wherein the third spring includes a third dielectric layer and a third conductive layer and spans between the second fixed element and the movable element.

[0132] In some embodiments, a micro electro mechanical system structure is provided. The micro electro mechanical system structure includes a first stationary element, a second stationary element, a cap structure connecting the first stationary element and the second stationary element, and a movable element between the first stationary element and the second stationary element and below the cap structure. A first spring includes a first dielectric layer, a first conductive layer, a buffer layer adjacent to the first conductive layer, a second dielectric layer adjacent to the buffer layer, and a second conductive layer adjacent to the second dielectric layer, and spans between the cap structure and the movable element. A second spring includes a third dielectric layer and a third conductive layer and spans between the first stationary element and the movable element.

[0133] The foregoing summary of features of several embodiments has been presented for the purposes of illustration and description. It is therefore contemplated that persons of ordinary skill in the art will readily appreciate that many other embodiments might be practiced in addition to the embodiments disclosed herein. Those skilled in the art will further appreciate that the embodiments disclosed herein are not limited to the specific embodiments described and that modifications and / or substitutions can be made without departing from the scope of the disclosure.

[0134] Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0135] Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed as a necessity or criticality unless specifically stated. Alternative ordering will be appreciated by those of ordinary skill in the art in view of this disclosure. Further, it should be appreciated that not all operations are necessarily present in every embodiment provided herein. Also, it should be appreciated that not all operations are necessarily required in some embodiments.

[0136] It should be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions and orientations relative to one another for purposes of simplicity and ease of understanding, and the same actual dimensions and orientations can differ from those depicted herein in some embodiments. Depicted layers, features, elements, etc. can also have different dimensions and / or orientations from those depicted herein in some embodiments. Depicted layers, features, elements, etc. can also be formed by a number of techniques, such as at least one of etching techniques, planarization techniques, implantation techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as CVD.

[0137] Also, "exemplary" is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, the use of "a" or "an" is intended to mean "one or more", unless otherwise indicated. Further, the use of at least one of A and B and / or the like is intended to mean A or B or both A and B. Moreover, the use of "includes", "including", "has", "having", "contains", "containing", "comprises", "comprising", "is" and / or "is including" etc., are used herein to mean comprising but can mean the more

[0138] Moreover, although this disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based on the foregoing description and accompanying drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe certain of these components are intended to correspond, unless otherwise indicated, to any component which performs the described function of the component (e.g., that is functionally equivalent), even if not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure can have been disclosed with respect to only one of several implementations, such feature can be combined with one or more other features of the other implementations as can be desired and advantageous for any given or particular application.

Claims

1. A micro-motor system structure, characterized in that, include: First fixed element; A second fixing element; A cover structure connecting the first fixing element and the second fixing element; A movable element is located between the first fixed element and the second fixed element, and is located below the cover structure; A first spring, comprising a first dielectric layer and a first conductive layer, and the first spring spanning between the cover structure and the movable element; and A second spring includes a second dielectric layer and a second conductive layer, and the second spring spans between the first fixed element and the movable element.

2. The micro-motor system structure as described in claim 1, characterized in that, include: A third spring includes a third dielectric layer and a third conductive layer, and the third spring spans between the second fixed element and the movable element.

3. The micro-motor system structure as described in claim 1, characterized in that: The first conductive layer has a first thickness, and The first dielectric layer has a second thickness, wherein the second thickness is at least 50% of the first thickness.

4. The micro-motor system structure as described in claim 1, characterized in that, include: A third spring is adjacent to the first spring and spans between the cover structure and the movable element; and A fourth spring is adjacent to the second spring and spans between the first fixed element and the movable element.

5. The micro-motor system structure as described in claim 1, characterized in that: The first spring includes a third dielectric layer adjacent to the first conductive layer and a third conductive layer adjacent to the third dielectric layer.

6. A micro-motor system structure, characterized in that, include: First fixed element; A second fixing element; A cover structure connecting the first fixing element and the second fixing element; A movable element is located between the first fixed element and the second fixed element, and is located below the cover structure; A first spring, comprising a first tension layer and a first compression layer, and the first spring spanning between the cover structure and the movable element; and A second spring includes a second tension layer and a second compression layer, and the second spring spans between the first fixed element and the movable element. The first stretching layer has a first thickness, and the first compression layer has a second thickness, wherein the second thickness is at least 50% of the first thickness.

7. The micro-motor system structure as described in claim 6, characterized in that, include: A third spring includes a third compression layer and a third tension layer, and the third spring spans between the second fixed element and the movable element.

8. The micro-motor system structure as described in claim 6, characterized in that, include: A third spring is adjacent to the first spring and spans between the cover structure and the movable element; and A fourth spring is adjacent to the second spring and spans between the first fixed element and the movable element.

9. The micro-motor system structure as described in claim 6, characterized in that: The first spring includes a third tension layer adjacent to the first compression layer and a third compression layer adjacent to the third tension layer.

10. A micro-motor system structure, characterized in that, include: First fixed element; A second fixing element; A cover structure connecting the first fixing element and the second fixing element; A movable element is located between the first fixed element and the second fixed element, and is located below the cover structure; A first spring includes a first dielectric layer, a first conductive layer, a buffer layer adjacent to the first conductive layer, a second dielectric layer adjacent to the buffer layer, and a second conductive layer adjacent to the second dielectric layer, and the first spring spans between the cover structure and the movable element; and A second spring includes a third dielectric layer and a third conductive layer, and the second spring spans between the first fixed element and the movable element.

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