Bidirectional switching circuit of signal control power supply

Abstract

The embodiment of the utility model discloses a bidirectional switching circuit of a signal control power supply, which comprises an MOS tube Q1, an MOS tube Q2, an MOS tube Q3, a resistor R1, a resistor R2 and a capacitor C2, the G pole of the MOS tube Q1 is used for receiving a control signal, the D pole of the MOS tube Q1 is connected with the G pole of the MOS tube Q2 and the G pole of the MOS tube Q3 through the resistor R1, the D pole of the MOS tube Q2 is used for connecting a peripheral function module power supply, the S pole of the MOS tube Q2 is connected with the S pole of the MOS tube Q3, the D pole of the MOS tube Q3 is connected with the positive pole of a voltage source, and the capacitor C2 is connected with the positive pole of the voltage source. The S pole of the MOS tube Q1 is connected with the GND, and the two ends of the resistor R2 and the two ends of the capacitor C2 are connected with the S pole and the G pole of the MOS tube Q2 respectively. The GPIO interface signal control circuit is used for controlling on-off of a power supply through GPIO interface signals, and is simple in structure and low in cost.

Description

TECHNICAL FIELD

[0001] The utility model relates to power control technical field especially relates to a signal control power's bidirectional switch circuit. BACKGROUND

[0002] At present, the system of some electronic equipment is all through the GPIO of CPU to control switch circuit, and then controls the opening and closing of peripheral function module power. However, the structure of the existing switch circuit is relatively complex, the cost is high, and it cannot be adjusted according to different control voltage source, power size, power ripple quality, load power-on and power-off timing requirements, etc., the application range is narrow, and it cannot meet the user demand. INVENTION CONTENT

[0003] The technical problem to be solved by the embodiment of the utility model lies in providing a signal control power's bidirectional switch circuit to simplify the structure and reduce the cost.

[0004] In order to solve the above technical problem, the embodiment of the utility model provides a signal control power's bidirectional switch circuit, which comprises MOS tube Q1, MOS tube Q2, MOS tube Q3, resistor R1, resistor R2, capacitor C2, the G pole of MOS tube Q1 is used for receiving control signal, the D pole of MOS tube Q1 is connected with the G pole of MOS tube Q2 and the G pole of MOS tube Q3 through resistor R1, the D pole of MOS tube Q2 is used for connecting peripheral function module power, the S pole of MOS tube Q2 is connected with the S pole of MOS tube Q3, the D pole of MOS tube Q3 is connected with the positive pole of voltage source, the S pole of MOS tube Q1 is connected with GND, and the two ends of resistor R2 and capacitor C2 are connected with the S pole and G pole of MOS tube Q2 respectively.

[0005] Further, it further includes capacitor C3, and the two ends of capacitor C3 are connected with the S pole of MOS tube Q1 and the D pole of MOS tube Q2 respectively.

[0006] Further, it further includes resistor R5, and the two ends of resistor R5 are connected with the S pole and G pole of MOS tube Q1 respectively.

[0007] Further, it further includes capacitor C1, one end of capacitor C1 is connected with the D pole of MOS tube Q3, and the other end is connected with GND.

[0008] Further, it further includes resistor R3, and the G pole of MOS tube Q1 receives control signal through resistor R3.

[0009] Further, MOS tube Q1 is NMOS tube, and MOS tube Q3 and MOS tube Q2 are PMOS tube.

[0010] The utility model discloses a beneficial effect is: the utility model discloses be used for GPIO port signal control power on-off, simple structure, low in cost. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 It is the principle diagram of signal control power's bidirectional switch circuit of the utility model embodiment 1.

[0012] Figure 2 It is the principle diagram of signal control power's bidirectional switch circuit of the utility model embodiment 2.

[0013] Figure 3 It is the principle diagram of signal control power's bidirectional switch circuit of the utility model embodiment 3.

[0014] Figure 4 It is the principle diagram of signal control power's bidirectional switch circuit of the utility model embodiment 4.

[0015] Figure 5 It is the principle diagram of signal control power's bidirectional switch circuit of the utility model embodiment 5.

[0016] Figure 6 It is the waveform schematic diagram of signal control power's bidirectional switch circuit of the utility model embodiment 1.

[0017] Figure 7 It is the waveform schematic diagram of signal control power's bidirectional switch circuit of the utility model embodiment 2.

[0018] Figure 8 It is the waveform schematic diagram of signal control power's bidirectional switch circuit of the utility model embodiment 3.

[0019] Figure 9 It is the waveform schematic diagram of signal control power's bidirectional switch circuit of the utility model embodiment 4.

[0020] Figure 10 It is the waveform schematic diagram of signal control power's bidirectional switch circuit of the utility model embodiment 5. DETAILED DESCRIPTION

[0021] It should be explained that the embodiment in the application and the features in the embodiment can be combined mutually in the case of no conflict, and the utility model will be explained further in detail in conjunction with the drawings and specific embodiment.

[0022] The directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the utility model are only used for explaining the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directional indications also change accordingly.

[0023] In addition, the descriptions of "first", "second", etc. in the utility model are only for the purpose of description, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first" and "second" can explicitly or implicitly include at least one of the features.

[0024] Please refer to Figures 1-10 The bidirectional switch circuit of the signal control power supply in the embodiment of the utility model includes MOS tube Q1, MOS tube Q2, MOS tube Q3, resistor R1, resistor R2, and capacitor C2.

[0025] The G pole of MOS tube Q1 is used for receiving a control signal, the D pole of MOS tube Q1 is connected to the G pole of MOS tube Q2 and the G pole of MOS tube Q3 through resistor R1, the D pole of MOS tube Q2 is used for connecting a peripheral function module power supply, the S pole of MOS tube Q2 is connected to the S pole of MOS tube Q3, the D pole of MOS tube Q3 is connected to the positive pole of a voltage source, the S pole of MOS tube Q1 is connected to GND, and the two ends of resistor R2 and capacitor C2 are respectively connected to the S pole and the G pole of MOS tube Q2.

[0026] As an implementation mode, the bidirectional switch circuit of the signal control power supply further includes capacitor C3, and the two ends of capacitor C3 are respectively connected to the S pole of MOS tube Q1 and the D pole of MOS tube Q2. Capacitor C3 can play the roles of energy storage, waveform stabilization, and filtering.

[0027] As an implementation mode, the bidirectional switch circuit of the signal control power supply further includes resistor R5, and the two ends of resistor R5 are respectively connected to the S pole and the G pole of MOS tube Q1.

[0028] As an implementation mode, the bidirectional switch circuit of the signal control power supply further includes capacitor C1, one end of capacitor C1 is connected to the D pole of MOS tube Q3, and the other end is connected to GND.

[0029] As an implementation mode, the bidirectional switch circuit of the signal control power supply further includes resistor R3, and the G pole of MOS tube Q1 receives a control signal through resistor R3.

[0030] As an implementation mode, MOS tube Q1 is an NMOS tube, MOS tube Q3 and MOS tube Q2 are both PMOS tubes.

[0031] Compared with the unidirectional switch circuit of the signal control power supply, the bidirectional switch circuit of the signal control power supply has one more PMOS tube Q3 (see Figure 1 in the PMOS tube Q3), why add one more PMOS tube Q3, because the use scene of this circuit is different, for example:

[0032] When the SOURCE source sends high level, 5V power supply flows from the D pole of PMOS tube Q3 to the D pole of PMOS tube Q2; of course, the power supply is bidirectional, if the power supply comes from the D pole of PMOS tube Q2, the power supply can also flow from the D pole of PMOS tube Q2 to the D pole of PMOS tube Q3.

[0033] When the SOURCE source sends low level, if the NMOS tube Q1 is turned off, the G pole voltage of PMOS tubes Q2 and Q3 is raised and is also turned off; if the power supply 5V comes from the D pole of PMOS tube Q3, the current flows from the D pole of PMOS tube Q3 to the S pole of PMOS tube Q3 (even if the PMOS tube is turned off, the current can also flow from the D pole of PMOS tube Q3 to the S pole of PMOS tube Q3), and cannot flow from the S pole of PMOS tube Q2 to the D pole of PMOS tube Q2, and the turn-off is formed in this way.

[0034] If the power supply 5V comes from the D pole of PMOS tube Q2, the current flows from the D pole of PMOS tube Q2 to the S pole of PMOS tube Q2 (even if the PMOS tube is turned off, the current can also flow from the D pole of PMOS tube Q2 to the S pole of PMOS tube Q2), and cannot flow from the S pole of PMOS tube Q3 to the D pole of PMOS tube Q3, and the turn-off is formed in this way; that is, whether the power supply 5V comes from the D pole of PMOS tube Q2 or the power supply 5V comes from the D pole of PMOS tube Q3, the bidirectional is turned off, these circuits will be applied in some special occasion circuits, such as the circuit of the power supply charging the battery, if it is a signal control power supply unidirectional switch circuit, when the signal is turned off, the battery electricity can flow from the battery to the adapter end, but if the signal control power supply bidirectional switch circuit is used, because the power supply is turned off, the current flow through the cut-off is bidirectional, the battery electricity will not flow back to the charging end; for example, this circuit can be applied to the signal control motor power supply on-off circuit, if it is a signal control power supply unidirectional switch circuit, when the signal is turned off, if the motor end is considered to rotate in the reverse direction, the generated electricity will flow from the motor end to the power supply end, and the backflow will cause damage to the power supply equipment; but if the signal control power supply bidirectional switch circuit is used, because the power supply is turned off, the current flow through the cut-off is bidirectional, even if the motor end is considered to rotate in the reverse direction, it will not flow to the power supply end, and the hardware of the power supply end is not damaged, effectively protecting the whole circuit system.

[0035] In order to more clearly explain how the circuit works, and demonstrate how adjusting the values of the components in the circuit affects the performance of the entire circuit, the utility model builds a circuit based on PROTEUS simulation software. As shown in Figure 1 The left side of R3 has a square wave signal generator (Note: this description mainly describes how the circuit controls the on-off of the power supply through GPIO, so the high and low levels of GPIO are simulated through the square wave signal generator. The signal generator used in this simulation has a voltage of 3.3V and a frequency of 0.5HZ).

[0036] When the G terminal of NMOS (Q1, model: 2N7002) (the pin connecting resistors R3 and R5) receives a high-level signal from the square wave on the left side of resistor R3, the G terminal of Q1 is high (V=[10K / (240R+10K)]*5V≈5V), at this time NMOS tube Q1 is turned on, 5V current passes through resistors R2, R1 and the S and D terminals of Q1, and then flows back to GND. At this time, the voltage V of the G terminal of PMOS tubes Q2 and Q3 (model: NTS4101P) is V=[10K / (10K+110K)]*5V≈0.45V; the D terminal of PMOS tube Q3 is directly connected to 5V (in order to more clearly explain the circuit, it is assumed that the power supply comes from the D terminal of PMOS tube Q3, and the load end is the D terminal of PMOS tube Q2, which will not be repeated in the following), so the VGS of PMOS tubes Q2 and Q3 is 5V-0.45V=4.55V; at this time, by querying the specification book of PMOS tubes Q2 and Q3 (model: NTS4101P), it can be known that the VGS at this time is greater than the minimum signal conduction opening voltage of PMOS tubes Q2 and Q3, so PMOS tubes Q2 and Q3 are turned on at this time, and the power supply flows from the D terminal of PMOS tube Q3 (the pin directly connected to the power supply 5V) to the D terminal of PMOS tube Q2. In the simulation circuit of Figure 1 the D terminal of PMOS tube Q2 is connected to channel A of the simulation oscilloscope.

[0037] When the G terminal of NMOS (Q1, model: 2N7002) (the pin connecting resistors R3 and R5) receives a low-level signal from the square wave on the left side of resistor R3, the G terminal of Q1 is low (V=[240R / (240R+10K)]*5V≈0V), at this time NMOS tube Q1 is turned off, at this time the voltage V of the G terminal of PMOS tubes Q2 and Q3 (model: NTS4101P) is V=5V; the D terminal of PMOS tube Q3 is directly connected to 5V, so the VGS of PMOS tubes Q2 and Q3 is 0V; so PMOS tubes Q2 and Q3 are not turned on at this time, and the power supply 5V cannot flow from the D terminal of PMOS tube Q3 to the D terminal of PMOS tube Q2, so at this time the D terminal of PMOS tube Q2 becomes low.

[0038] The utility model discloses a kind of bidirectional switch circuit of signal control power supply, which is not universal, and the power voltage controlled by GPIO control power supply is different when power supply on-off is encountered, and the load power consumption of rear end is also different, so in practical application, the size of the device value in the circuit can be adjusted according to actual situation to ensure stable operation of the circuit.

[0039] The circuit is demonstrated by simulation software before and after adjusting the device value, and the output waveform of the power supply controlled by GPIO changes.

[0040] Example 2: when adjusting Figure 2 R1=100K in the middle;R2=100K;C2=2.2uF, when the output waveform of signal generator is 3.3V, square wave, 0.5HZ, and the duty cycle is 50% (square wave located in the upper part of Figure 7 , it can be seen that the waveform at the output end of power supply (square wave located in the lower part of Figure 7 ) has the following changes:

[0041] 1. The waveform is delayed in rising time compared with the waveform of signal generator;

[0042] 2. The duty cycle is slightly greater than 50%;

[0043] 3. The falling edge of the waveform has relatively slow inclination, and is no longer a standard square wave.

[0044] Circuit application scenario: if the demand current of rear-end load is large, and the requirement for power supply ripple is high, the power supply cannot have too high convexity, and the circuit of Figure 2 can be used, such as Figure 2 C2 in the middle is 2.2uF, which can absorb the ripple of front end, and if the convexity of rear-end waveform is tested, the value can be appropriately increased, which can improve the ripple of rear end.

[0045] Example 3: when adjusting Figure 3 R1=10K in the middle;R2=100K;C2=2.2uF, when the output waveform of signal generator is 3.3V, square wave, 0.5HZ, and the duty cycle is 50% (square wave located in the upper part of Figure 8 , it can be seen that the waveform at the output end of power supply (square wave located in the lower part of Figure 8 ) has the following changes:

[0046] 1. The waveform is almost not delayed in rising time compared with the waveform of signal generator;

[0047] 2. The duty cycle is greater than 50%, and is greater than the duty cycle when R1=100K;

[0048] 3. The falling edge of the waveform has relatively slow inclination, and is no longer a standard square wave.

[0049] Reason analysis of waveform change caused by changing R1 from 100K to 10K:

[0050] Analysis change one: the waveform has almost no delay rising edge time relative to the waveform of the signal generator.

[0051] When PMOS tubes Q2 and Q3 are not turned on, the 5V power supply charges the capacitor C2 through R2, making the two ends of C2 5V. When the G terminal of NMOS (Q1, model: 2N7002) receives a high-level signal from the square wave on the left side of resistor R3, the G terminal of Q1 is high (V=[10K / (240R+10K)]*5V≈5V), at this time NMOS tube Q1 is turned on, 5V current passes through resistor R2, R1 and the S and D terminals of Q1, and then flows back to GND. At this time, the C2 pin connected to the G terminal of PMOS tubes Q2 and Q3 starts to discharge. Since R1=100K is changed to 10K, the discharge speed of the C2 pin connected to the G terminal of PMOS tubes Q2 and Q3 is faster than when R1=100K, so the G terminal voltage of PMOS tubes Q2 and Q3 drops more quickly, and PMOS tubes Q2 and Q3 turn on faster, so the waveform has almost no delay rising edge time relative to the waveform of the signal generator.

[0052] Analysis change two: the duty cycle is greater than 50%, and the duty cycle is greater than when R1=100K.

[0053] The reason why the duty cycle is greater than 50% is twofold. First, after the PMOS tubes Q2 and Q3 are turned off, there is a capacitor C3 in the back end (the size of this capacitor can be adjusted, and different value capacitors can be connected in parallel. The capacitor can store energy, stabilize the waveform, and filter). Therefore, the capacitor C3 discharges the stored energy to the load R4 (R4 simulates the load), so the voltage at the D terminal of the PMOS tube Q2 will exist for a short time. Second, when the PMOS tubes Q2 and Q3 are turned off, the G terminal voltage of the PMOS tubes Q2 and Q3 starts to rise to 5V due to the turn-off of the NMOS tube Q1. However, when R2=100K, the VGS voltage in the on state is: R1 / (R1+R2)*5V=2.5V, and when R=10K, the VGS voltage in the on state is: R1 / (R1+R2)*5V≈0.45V. Therefore, the time for the PMOS tube VGS to rise from 0.45V to 5V when R=10K is longer than the time for the PMOS tube VGS to rise from 2.5V to 5V when R=100K. Therefore, the turn-off time of the PMOS tubes Q2 and Q3 in response to the GPIO port is longer when R=10K, so the duty cycle is greater than 50%, and the duty cycle is greater than when R1=100K.

[0054] Circuit application scenario: If the back end has timing requirements and needs a certain time delay to power down, the following circuit can be used.

[0055] Example 4: When adjusting Figure 4 R1=10K; R2=100K; C2=0.1uF, when the signal generator output waveform is 3.3V, square wave, 0.5HZ, duty cycle is 50% (square wave located Figure 9 below), it can be seen that the power output waveform (square wave located Figure 9 below) has the following changes:

[0056] 1. Compared with Figure 3 C2 from 2.2uF to 0.1uF, the duty cycle changes from far greater than 50% to closer to 50%.

[0057] Analysis of changes: after changing C2 from 2.2uF to 0.1uF, the duty cycle changes from much greater than 50% to closer to 50%: when PMOS tubes Q2 and Q3 are turned off, the G voltage of PMOS tubes Q2 and Q3 starts to rise to 5V due to the turn-off of NMOS tube Q1, but since C2=2.2uF is changed to 0.1uF, PIN2 of capacitor C2 starts to charge, the voltage across capacitor C2 tends to be the same, and since the value of capacitor C2 is smaller, the charging time is smaller, so the VGS of PMOS tubes Q2 and Q3 rises from 0.3V to 5V faster, so the turn-off time of PMOS tubes Q2 and Q3 is shorter when C2=0.1uF, and the D voltage of PMOS tube Q2 falls quickly, so the duty cycle quickly decreases and tends to 50%, which is faster than when C2=2.2uF.

[0058] Circuit application scenario: if the back-end power-on speed is required to be fast, and the time required for power-on from 0V to 5V is short (some multi-power supply modules require fast power-on, and slow power-on may cause timing disorder, insufficient power supply, etc., and cannot work normally), at this time, R1 and R2 can be reduced in proportion, and the value of C2 can be adjusted appropriately to ensure faster power-on speed.

[0059] Example 5: when adjusting Figure 5 R1=10K; R2=100K; C2=0.1uF; C3=10uF, when the signal generator output waveform is 3.3V, square wave, 0.5HZ, duty cycle is 50% (square wave located Figure 10 below), it can be seen that the power output waveform (square wave located Figure 10 below) has the following changes:

[0060] 1. Compared with Figure 4 C3 from 1uF to 10uF, the D voltage of PMOS tube Q2 will appear slowly.

[0061] Analysis of changes: since PMOS tubes Q2 and Q3 are turned off, there is a capacitor C3 in the back-end (the size of this capacitor can be adjusted, and different value capacitors can be connected in parallel, and the capacitor can store energy, stabilize the waveform, and filter), so the capacitor C3 discharges the stored energy to the load R4 (R4 simulates the load), so the D voltage of PMOS tube Q2 will appear slowly, and of course the size of the load R4 will also affect the drop speed of the power supply.

[0062] Circuit application scene: if the back-end load requires fast power-down speed (when some modules are powered on and off quickly, if the power-down and power-up interval is too short, the module has not completely powered off before power-up, which will cause timing disorder and failure), a discharge resistor can be added to the power output end to speed up the voltage drop speed after power-down.

[0063] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A bidirectional switch circuit for signal-controlled power supply, characterized by The application comprises MOS tube Q1, MOS tube Q2, MOS tube Q3, resistance R1, resistance R2, capacitor C2, the G pole of MOS tube Q1 is used for receiving control signal, the D pole of MOS tube Q1 connects the G pole of MOS tube Q2 and the G pole of MOS tube Q3 through resistance R1, the D pole of MOS tube Q2 is used for connecting peripheral function module power supply, the S pole of MOS tube Q2 connects the S pole of MOS tube Q3, the D pole of MOS tube Q3 connects voltage source anode, the S pole of MOS tube Q1 connects GND, the two ends of resistance R2 and capacitor C2 are connected with the S pole and the G pole of MOS tube Q2 respectively.

2. The bi-directional switch circuit for signal controlled power supply as claimed in claim 1, wherein, It also comprises capacitor C3, the two ends of capacitor C3 are connected with the S pole of MOS tube Q1 and the D pole of MOS tube Q2 respectively.

3. The bi-directional switch circuit for signal controlled power supply as claimed in claim 1, wherein, It also comprises resistance R5, the two ends of resistance R5 are connected with the S pole and the G pole of MOS tube Q1 respectively.

4. The bi-directional switch circuit for signal controlled power supply as claimed in claim 1, wherein, It also comprises capacitor C1, one end of capacitor C1 connects the D pole of MOS tube Q3, and the other end connects GND.

5. The signal-controlled power bidirectional switch circuit of claim 1, wherein, It also comprises resistance R3, the G pole of MOS tube Q1 receives control signal through resistance R3.

6. The signal-controlled power bidirectional switch circuit of claim 1, wherein, MOS tube Q1 is NMOS tube, MOS tube Q3 and MOS tube Q2 are PMOS tubes.

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