Storage chip and electronic equipment

Abstract

The embodiment of the utility model discloses a storage chip and electronic equipment, the storage chip comprises a packaging substrate, a logic bare chip and a plurality of storage units, the packaging substrate is provided with a bearing surface, the logic bare chip and the storage units are arranged on the bearing surface, each storage unit comprises a plurality of memory bare chips, the packaging substrate is provided with a first connecting module and a second connecting module which are located on the bearing surface and electrically connected with each other, the logic bare chip is electrically connected with the first connecting module, and the memory bare chip is electrically connected with the second connecting module, so that the logic bare chip is electrically connected with the memory bare chip. According to the storage chip provided by the invention, the problems of complicated production and manufacturing process, high cost and supply chain tension of the storage chip in the related technology can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a storage chip and an electronic device. BACKGROUND

[0002] In the related art, the demand for high-bandwidth-capacity storage chips is increasing, but the production and manufacturing process of the high-bandwidth-capacity storage chips is complex, the cost is high, and the supply chain is tight. SUMMARY

[0003] Embodiments of the present application provide a storage chip and an electronic device, which are used to improve the problems of complex production and manufacturing process, high cost, and tight supply chain of the storage chip in the related art.

[0004] In a first aspect, embodiments of the present application provide a storage chip, comprising a packaging substrate, a logic die, and a plurality of storage units, the packaging substrate having a bearing surface, the logic die and the storage units being arranged on the bearing surface, and each of the storage units comprising a plurality of memory dies, wherein the packaging substrate is provided with a first connection module and a second connection module located on the bearing surface and electrically connected to each other, the logic die is electrically connected to the first connection module, and the memory dies are electrically connected to the second connection module, so as to realize electrical connection between the logic die and the memory dies.

[0005] The storage chip provided by the present application improves the bandwidth capacity of the storage chip by using a plurality of memory dies to form a storage unit. At the same time, the first connection module and the second connection module on the bearing surface of the packaging substrate are used to directly electrically connect the logic die and the memory dies, so that the interconnection structure between the logic die and the storage unit is simple, the complex wiring layer is reduced, the production and manufacturing process of the storage chip is simplified, the cycle is shortened, the cost is reduced, and the problem of tight supply chain is avoided.

[0006] In some embodiments, the projections of at least two memory dies of the plurality of memory dies of the same storage unit on the packaging substrate overlap.

[0007] Based on the above-mentioned embodiments, the area occupied by a single storage unit on the packaging substrate is small, so that a higher bandwidth capacity can be obtained within a limited size limit.

[0008] In some embodiments, the plurality of memory dies of the same storage unit are composite bonded or wire bonded. Based on the above-mentioned embodiments, the stacking structure of the plurality of memory dies of the storage unit is simple, the process difficulty is low, and the production and manufacturing of the high-bandwidth storage chip is not limited by the TSV necking technology.

[0009] In some embodiments, the storage unit includes a first die and a plurality of second dies, the first die is disposed on the bearing surface, and the plurality of second dies are stacked on a side of the first die away from the package substrate; the first die is electrically connected to the second connection module.

[0010] Based on the above embodiments, the interconnection between the storage unit and the logic die is realized through the package substrate, which simplifies the interconnection structure and reduces the process difficulty.

[0011] In some embodiments, the first die is provided with a first physical layer on a side facing the package substrate, and the logic die is provided with a second physical layer on a side facing the package substrate; the first connection module includes a plurality of first pads, and the plurality of first pads are electrically connected to the first physical layer; the second connection module includes a plurality of second pads, and the plurality of second pads are electrically connected to the second physical layer.

[0012] Based on the above embodiments, the electrical connection between the logic die and the storage unit is realized through the physical layer, thereby realizing the data transmission between the logic die and the storage unit.

[0013] In some embodiments, the plurality of first pads are arranged in rows and columns in two intersecting directions, respectively; along the row direction, the distance between adjacent two first pads is 100-150 μm; along the column direction, the distance between adjacent two first pads is 100-150 μm; and / or, the plurality of second pads are arranged in rows and columns in two intersecting directions, respectively; along the row direction, the distance between adjacent two second pads is 100-150 μm; along the column direction, the distance between adjacent two second pads is 100-150 μm.

[0014] Based on the above embodiments, the pad arrangement density on the package substrate is high, thereby making the data transmission efficiency between the storage unit and the logic die high.

[0015] In some embodiments, the storage chip includes a plurality of storage units, and at least part of the storage units are arranged around the logic die.

[0016] Based on the above embodiments, the capacity of the storage chip can be improved while the sum of the spaces occupied by the plurality of storage units and the logic die is small.

[0017] In some embodiments, the logic die comprises an artificial intelligence die; and / or, the memory unit comprises dynamic random access memory and / or static random access memory; and / or, the memory unit and the logic die communicate through D2D PHY interconnection, which comprises Universal Chiplet Interconnect (UCIe), Bunch of Wires (BOW) or Advanced Interface Bus (AIB).

[0018] Based on the above embodiments, the storage chip can meet the growing demand for AI big computing power, and the memory protocol has high selectivity.

[0019] In some embodiments, the packaging substrate has multiple layers; and / or, the packaging substrate comprises an organic packaging substrate or a glass substrate.

[0020] Based on the above embodiments, the packaging substrate can load more memory units, thereby improving the capacity of the storage chip. In a second aspect, the embodiments of the present application provide an electronic device comprising the storage chip of the above embodiments. The electronic device of the embodiments of the present application adopts the storage chip in the above embodiments, which improves the bandwidth capacity by arranging multiple memory dies to form a memory unit. On this basis, the logic die and the memory unit are respectively electrically connected with the connection module on the bearing surface of the packaging substrate to realize data transmission between the logic die and the memory unit, so that the logic die and the memory unit are directly interconnected through the packaging substrate, which has a simple structure and reduces the complex wiring layer, thereby simplifying the production and manufacturing process of the storage chip, shortening the cycle, reducing the cost, and avoiding the problem of supply chain tension, thereby improving the production capacity of the electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0022] Figure 1 A plan view of a storage chip in an embodiment of the present application is shown.

[0023] Figure 2 A cross-sectional view along the A-A direction in the above embodiment is shown. Figure 1

[0024] Figure 3 ​A schematic diagram of the arrangement structure of the first bump in an embodiment of the present application is shown.

[0025] Figure 4 A schematic diagram of the arrangement structure of the first bump in another embodiment of the present application is shown.

[0026] Legend of reference signs:

[0027] 1, memory chip;

[0028] 10, package substrate; 11, connection surface; 12, bearing surface; 121, first bump; 122, second bump; X, row direction; Y, column direction

[0029] 20, logic die; 21, second physical layer;

[0030] 30, memory unit; 31, first physical layer. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application with reference to the accompanying drawings.

[0032] The following description refers to the accompanying drawings. Unless otherwise indicated, like numbers in the different figures indicate the same or similar elements. The following example embodiments described are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0033] Before the specific solutions of the present application are described in detail, the following first explains some terms in the present application to facilitate understanding by those skilled in the art.

[0034] Die refers to a die before packaging, which is a small piece cut from a silicon wafer by laser cutting. Each Die is an independent functional chip. The Die will be packaged as a common chip. To meet the computing power requirements of artificial intelligence chips today, the industry has proposed a technical solution to package multiple Die in a chip, thereby providing greater computing power.

[0035] High Bandwidth Memory (HBM) is a standardized stacking storage technology that provides high-bandwidth channels for data within the stack and between storage and logic elements. Specifically, HBM uses stacked memory chips and different stacked storage settings through through-silicon vias to improve data transmission speed and bandwidth.

[0036] Through Silicon Via (TSV) refers to etching a through hole in a silicon substrate and filling the through hole with a metal conductor material such as copper or tungsten to form vertical interconnection of chips.

[0037] 2.5D packaging, die stacks or side-by-side are placed on top of the interposer with through silicon vias, and the dies are electrically connected through the interposer.

[0038] 3D packaging, logic dies are stacked together or logic dies are stacked together with memory dies, and the dies are electrically connected through the interposer.

[0039] Bump pitch refers to the spacing between the center points of two bump pads.

[0040] With the rise of Artificial Intelligence (AI) big computing power, the demand for memory chip bandwidth capacity is gradually increasing. Based on this, 3D / 2.5D (3D / 2.5D) integration, especially HBM, is increasingly valued by the industry. Specifically, HBM increases storage density and bandwidth through 3D stacking, and uses 2.5D packaging technology to realize die-to-die (D2D) interconnection of stacked HBM and main chips on an interposer, thereby realizing data transmission.

[0041] However, the packaging of HBM needs to use a through silicon via structure, and in the die interconnection process of HBM, memory dies and logic dies such as AI dies are interconnected through 2.5D advanced interposers, while the through silicon via structure, while realizing three-dimensional interconnection of signals, also brings expensive equipment and process costs to 2.5D packaging technology. The prices of equipment such as silicon etching machines, thermal oxidation furnace tubes, cleaning machines, magnetron sputtering machines, and electroplating machines used to make through silicon vias are very expensive, resulting in problems such as complex process, long cycle, high cost, and tight supply chain in the production and manufacturing of through silicon vias and interposers, and there is a risk of being "necked" in China.

[0042] To solve the above problems, the present application provides a storage chip, which is composed of a plurality of memory dies to improve the bandwidth capacity. On this basis, the logic dies and the storage units are respectively electrically connected with the connection modules on the bearing surface of the packaging substrate to realize data transmission between the logic dies and the storage units. In this way, the logic dies and the storage units are directly interconnected through the packaging substrate, the structure is simple, the complex wiring layer is reduced, the production and manufacturing process is simplified, the cycle is shortened, the cost is reduced, and the problem of tight supply chain is avoided.

[0043] Reference Figure 1 and Figure 2The storage chip 1 provided by an embodiment of the present application comprises a packaging substrate 10, a logic die 20, and a plurality of storage units 30. The packaging substrate 10 has two surfaces opposite to each other, one of which is a connecting surface 11 and the other is a bearing surface 12. The connecting surface 11 is used to be electrically connected with a circuit board, and the bearing surface 12 is used to bear the logic die 20, the storage units 30, and the like. The arrangement of the logic die 20 and the one or more storage units 30 on the bearing surface 12 can be flexibly adjusted according to design requirements.

[0044] Specifically, the storage unit 30 comprises a plurality of memory dies to obtain higher bandwidth capacity. The packaging substrate 10 is provided with a first connecting module and a second connecting module on the bearing surface 12, and the first connecting module and the second connecting module are electrically connected with each other. The logic die 20 is electrically connected with the first connecting module, and the memory dies are electrically connected with the second connecting module. It can be understood that in the same storage unit 30, the plurality of memory dies are electrically connected with each other, and any one of the memory dies is electrically connected with the second connecting module, so that the remaining memory dies are electrically connected with the second connecting module. In this way, the electrical connection between the logic die 20 and the memory dies is realized, so that the logic die 20 can write data to the memory dies or read data from the memory dies.

[0045] Based on the storage chip 1 provided by the embodiment of the present application, on the one hand, the storage unit 30 composed of a plurality of memory dies improves the bandwidth capacity of the storage chip 1; on the other hand, since the logic die 20 and the storage unit 30 are directly electrically connected through the first connecting module and the second connecting module on the bearing surface 12 of the packaging substrate 10, the interconnection structure between the logic die 20 and the storage unit 30 is simple, the complex wiring layer is reduced, so that the production and manufacturing process of the storage chip 1 is simplified, the cycle is shortened, the cost is reduced, and the problem of supply chain tension is avoided.

[0046] Optionally, in the plurality of storage units 30, the number of memory dies of each storage unit 30 can be the same or different, which can be selected according to the capacity requirements and process design of the storage chip 1, and is not limited herein. In some embodiments, in the plurality of memory dies of the same storage unit 30, at least two memory dies are partially overlapped in the orthographic projection on the packaging substrate 10. In other words, the plurality of memory dies of the same storage unit 30 are stacked along the thickness direction of the packaging substrate 10. Based on this, under the condition of guaranteeing high bandwidth capacity, the area occupied by a single storage unit 30 on the packaging substrate 10 is smaller, so that higher bandwidth capacity can be obtained under the limited size limit.

[0047] In some embodiments, the plurality of memory dies of the same memory unit 30 are completely overlapped in the orthographic projection on the package substrate 10. In other words, the plurality of memory dies of the same memory unit 30 are stacked along the thickness direction of the package substrate 10, and each memory die of the same memory unit 30 has the same size and the same projection position but different height in the vertical direction. Based on this, the area occupied by the single memory unit 30 on the package substrate 10 is minimized under the condition of guaranteeing high bandwidth capacity, thereby fully utilizing the space on the package substrate 10 and improving the bandwidth capacity of the memory chip 1.

[0048] Further, based on the plurality of memory dies of the same memory unit 30 being stacked along the thickness direction of the package substrate 10, the plurality of memory dies of the same memory unit 30 can be interconnected by hybrid bonding or wire bonding. Based on this, compared with the high-bandwidth-capacity memory such as HBM in the related art which needs to use Through Silicon Via (TSV) technology to realize vertical interconnection of multiple dies, the stacking structure of the plurality of memory dies of the memory unit 30 in the embodiment is simple and has low process difficulty, thereby avoiding the production and manufacturing of the high-bandwidth memory chip 1 being limited by the TSV necking technology. In some embodiments, the memory unit 30 includes a first die and a plurality of second dies, and the plurality of second dies include two second dies and more than two second dies. The first die is arranged on the bearing surface 12, and the second dies are arranged on the side of the first die away from the package substrate 10, wherein the first die is electrically connected with the second connection module, i.e., the bottom die of the memory unit 30 in the vertical direction is electrically connected with the second connection module on the package substrate 10, thereby realizing the interconnection between the memory unit 30 and the logic die 20 through the package substrate 10, simplifying the interconnection structure and reducing the process difficulty.

[0049] Optionally, the side of the memory unit 30 and the logic die 20 facing the package substrate 10 can be respectively provided with a physical layer (PHY), and the specific structure design of the PHY can refer to the PHY in the related art. On this basis, the connection between the memory unit 30 and the connection module on the package substrate 10 and the connection between the logic die 20 and the connection module on the package substrate 10 can be realized by the corresponding physical layer.

[0050] Exemplarily, the first die is provided with a first physical layer 31 on a side thereof facing the packaging substrate 10, and the logic die 20 is provided with a second physical layer 21 on a side thereof facing the packaging substrate 10. The first physical layer 31 has a smaller area of a normal projection on the packaging substrate 10 than the first die, and the second physical layer 21 has a smaller area of a normal projection on the packaging substrate 10 than the logic die 20. The first connection module includes a plurality of first pads 121, and the second connection module includes a plurality of second pads 122. The plurality of first pads 121 are electrically connected to the first physical layer 31, and the plurality of second pads 122 are electrically connected to the second physical layer 21, so as to realize electrical connection between the storage unit 30 and the logic die 20, and realize data transmission between the logic die 20 and the storage unit 30.

[0051] In other words, the storage unit 30 and the logic die 20 communicate with each other through D2D PHY interconnection. The D2D PHY interconnection complies with, but is not limited to, a universal chiplet interconnect protocol (UCIe), a bunch of wires (BOW), an advanced interface bus (AIB), and other chiplet interconnection protocols. Specifically, the UCIe standard defines a maximum wiring length of 25 mm for a 2D package. If other small chip interconnection protocols are used, longer wiring lengths can be supported. Compared with the wiring length of HBM on a silicon interposer, which is generally not more than 5 mm, the present application can load more storage units 30 to support larger capacities.

[0052] Optionally, the first physical layer 31 on the first die is located at one end of the first die close to the logic die 20, and the second physical layer 31 on the logic die 20 is located at one end of the logic die 20 close to the first die, i.e., the first physical layer 31 on the first die is arranged at an edge of the first die and located at one side close to the logic die 20, and the second physical layer 31 on the logic die 20 is arranged at an edge of the logic die 20 and located at one side close to the logic die 20. Through such design, the connection distance between the first die and the logic die 20 is shortened, which on the one hand improves the convenience of interconnection between the storage unit 30 and the logic die 20, and on the other hand shortens the wiring length and reduces the process difficulty.

[0053] In some embodiments, the plurality of bumps are arranged on the bearing surface 12 of the packaging substrate 10. The bumps can be bumps (Bump) protruding from the bearing surface 12 of the packaging substrate 10, such as spherical bumps. The plurality of bumps can be arranged uniformly on the packaging substrate 10, or arranged in specific areas according to the wiring requirements. Some of the bumps are first bumps 121, and some of the bumps are second bumps 122. The first bumps 121 are used to electrically connect with the first physical layer 31 of the storage unit 30, and the second bumps 122 are used to electrically connect with the second physical layer 21 of the logic die 20.

[0054] Optionally, the plurality of first bumps 121 are arranged in rows and columns in two intersecting directions. The distance between any two adjacent first bumps 121 in the row direction of the first bumps 121 is 100-150 μm, and the distance between any two adjacent first bumps 121 in the column direction of the first bumps 121 is 100-150 μm, i.e. the Bump pitch of the first bumps 121 is 100-150 μm, such as 110 μm, 120 μm, 130 μm, or 140 μm.

[0055] Optionally, the plurality of second bumps 122 are arranged in rows and columns in two intersecting directions. The distance between any two adjacent second bumps 122 in the row direction of the second bumps 122 is 100-150 μm, and the distance between any two adjacent second bumps 122 in the column direction of the second bumps 122 is 100-150 μm, i.e. the Bump pitch of the second bumps 122 is 100-150 μm, such as 110 μm, 120 μm, 130 μm, or 140 μm.

[0056] The angle between the row direction and the column direction of the first bumps 121 is equal to or different from the angle between the row direction and the column direction of the second bumps 122. The angle between the row direction and the column direction can be a right angle or an acute angle. Based on the above Bump pitch design, the data transmission efficiency between the storage unit 30 and the logic die 20 is high.

[0057] The following illustrates the arrangement structure of the first bumps 121.

[0058] Referring to Figure 3 In an exemplary embodiment, the angle between the row direction X and the column direction Y of the plurality of first bumps 121 is 60°, and the orthographic projection shape of each first bump 121 on the packaging substrate 10 is the same and the projection area is equal. In the same row, the distance between any two adjacent first bumps 121 is equal. In the same column, the distance between any two adjacent first bumps 121 is equal.

[0059] Based on this, for any three centers not on the same straight line, and two adjacent first pads 121, the center line shape is a right triangle T2.

[0060] In other words, any two adjacent rows of first pads 121 are staggered, for example, the first row of first pads 121 and the second row of first pads 121 are staggered, and the center of one first pad 121 in the first row is located on the perpendicular bisector of the center line of two adjacent first pads 121 in the second row.

[0061] Similarly, any two adjacent columns of first pads 121 are staggered, for example, the first column of first pads 121 and the second column of first pads 121 are staggered, and the center of one first pad 121 in the first column is located on the perpendicular bisector of the center line of two adjacent first pads 121 in the second column.

[0062] In this way, all first pads 121 are closely arranged in the entire arrangement area of the first pads 121, and the first pads 121 in any row make full use of the interval space between the adjacent two first pads 121 in the adjacent row, and the first pads 121 in any column make full use of the interval space between the adjacent two first pads 121 in the adjacent column, thereby greatly improving the data transmission efficiency between the storage unit 30 and the logic die 20.

[0063] Referring to Figure 4 In another exemplary embodiment, the angle between the row direction X and the column direction Y of the plurality of first pads 121 is 45°, and the orthographic projection shape of each first pad 121 on the packaging substrate 10 is the same and the projection area is equal. In the same row, the distance between any two adjacent first pads 121 is equal. In the same column, the distance between any two adjacent first pads 121 is equal.

[0064] Based on this, for any three centers not on the same straight line, and two adjacent first pads 121, the center line shape is an isosceles right triangle T2.

[0065] In this case, any two adjacent rows of first pads 121 are staggered, for example, the first row of first pads 121 and the second row of first pads 121 are staggered, and the center of one first pad 121 in the first row is located on the perpendicular bisector of the center line of two adjacent first pads 121 in the second row. Any two adjacent columns of first pads 121 are staggered, for example, the first column of first pads 121 and the second column of first pads 121 are staggered, and the center of one first pad 121 in the first column is located on the perpendicular bisector of the center line of two adjacent first pads 121 in the second column. In this way, the space utilization can also be improved, thereby improving the data transmission efficiency between the storage unit 30 and the logic die 20.

[0066] The arrangement structure of the second rugged pad 122 can be the same as that of the first rugged pad 121, which will not be described herein again. In some embodiments, the storage chip 1 includes a plurality of storage units 30, and at least part of the storage units 30 are arranged around the logic die 20, i.e., all the storage units 30 are arranged around the logic die 20, or part of the storage units 30 are arranged around the logic die 20, and the rest of the storage units 30 are located outside the storage units 30 arranged around the logic die 20. In this way, the capacity of the storage chip 1 can be improved while ensuring that the sum of the spaces occupied by the plurality of storage units 30 and the logic die 20 is small.

[0067] Optionally, the storage chip 1 includes a plurality of storage units 30, and the plurality of storage units 30 are arranged around the logic die 20 or around part of the sides of the logic die 20. In this way, the capacity of the storage chip 1 can be improved while ensuring that the sum of the spaces occupied by the plurality of storage units 30 and the logic die 20 is small.

[0068] Referring to Figure 1 In an exemplary embodiment, the logic die 20 has a quadrilateral shape, the plurality of storage units 30 are arranged around the logic die 20, and the number of the storage units 30 located on two opposite sides of the logic die 20 is equal. Based on this, the number of the storage units 30 on one package substrate 10 is large, so that the capacity of the storage chip 1 is large.

[0069] It should be noted that Figure 1 The two storage units 30 arranged on one side of the logic die 20 shown in FIG. 1 are only illustrative of the fact that a plurality of storage units 30 can be arranged in the region, and do not limit the region to only two storage units 30.

[0070] In some embodiments, the logic die 20 includes a system-on-a-chip (SoC), such as an artificial intelligence die (AI Die), a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), etc. In this way, the storage chip 1 provided by the present application can meet the growing demand for AI large computing power.

[0071] It should be noted that in the related art, the memory die of the HBM can only be dynamic random access memory, and the interconnection of the logic die 20, such as an AI die, and the memory die on the packaging substrate 10 needs to follow a memory protocol such as HBM, Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), and the like, and the selectivity is low.

[0072] The storage unit 30 of the present application can be either dynamic random access memory (DRAM), such as a single DRAM, a 3D stacked DRAM, a DRAM hybrid bonding, or a DRAM wire bonding, or static random access memory, and the selectivity is higher.

[0073] In addition, the maximum speed of a single trace of the current HBM is about 6.4 Gbps, the current DDR5 plans to increase the standard speed of a single trace to 8.8 Gbps, and the maximum speed of a single trace specified by the UCIe protocol is 32 Gbps. Based on this, when the bandwidth requirement in chip design is high, the storage chip 1 provided by the present application can select the interconnection between the AI die and the memory die to follow the UCIe protocol, that is, the interconnection between the logic die 20 and the storage unit 30 in the above embodiment follows the UCIe protocol.

[0074] Alternatively, the packaging substrate 10 has multiple layers, and the packaging type is a flip chip ball grid array (FCBGA) or a flip chip-chip size package (FCCSP). For example, 10L fcbga, 8L fccsp, and 6L fccsp; where 10L, 8L, and 6L represent that the packaging substrate 10 has 10 layers, 8 layers, and 6 layers. Based on design requirements, the packaging type can be flexibly selected. Compared with the HBM which needs 2.5D packaging, the production capacity is limited and the price is high. The storage chip 1 provided by the present application can use conventional 2D packaging, and the packaging production capacity supply is more reliable and stable, and the cost is lower.

[0075] In terms of the type of packaging substrate 10, the HBM in the related art is connected based on a silicon interposer, while the storage chip 1 of the present application is connected based on a substrate, such as an organic packaging substrate 10 or a glass substrate. The currently mass-produced 2D organic packaging substrate 10 in the industry has an area about 4 times larger than a silicon interposer, and can load more storage units 30 to support a larger capacity. If a glass substrate is used, the substrate area is larger and can load more storage units 30.

[0076] Exemplarily, in the prior art, the upper limit of the interposer area of the CoWoS-S based on a silicon interposer (Si interposer) has been developed to 2500 square millimeters. The size of the glass substrate of the 1st generation line is about 320 millimeters x 400 millimeters, which is much larger than the upper limit of the interposer area.

[0077] Based on the same inventive concept, the application further provides an electronic device comprising the storage chip 1 of the above embodiments.

[0078] In the description of the present application, it should be understood that the terms "first", "second" and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "a plurality of" means at least two, for example, two, three, four, and the like. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0079] The above disclosure is only the preferred embodiment of the present application, which cannot limit the scope of the right of the present application, so the equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A memory chip, characterized by, The application relates to a memory chip. The memory chip comprises: a packaging substrate having a bearing surface; a logic die arranged on the bearing surface; and a plurality of memory units arranged on the bearing surface, each of the memory units comprising a plurality of memory dies.

2. The memory chip of claim 1, wherein, The packaging substrate is provided with a first connection module and a second connection module arranged on the bearing surface and electrically connected to each other, the logic die is electrically connected to the first connection module, and the memory dies are electrically connected to the second connection module, so as to realize electrical connection between the logic die and the memory dies.

3. The memory chip of claim 2, wherein, The memory dies of the same memory unit are arranged in a composite manner.

4. The memory chip according to claim 2 or 3, characterized in that, The memory dies of the same memory unit are bonded or wire-bonded. The memory unit comprises a first die arranged on the bearing surface and a plurality of second dies stacked on a side of the first die away from the packaging substrate.

5. The memory chip of claim 4, wherein, The first die is electrically connected to the second connection module. The first die is provided with a first physical layer on a side thereof facing the packaging substrate, and the logic die is provided with a second physical layer on a side thereof facing the packaging substrate. The first connection module comprises a plurality of first bumps, and the first bumps are electrically connected to the first physical layer.

6. The memory chip of claim 5, wherein, The second connection module comprises a plurality of second bumps, and the second bumps are electrically connected to the second physical layer. The first bumps are arranged in rows and columns along two intersecting directions. The distance between two adjacent first bumps in the row direction is 100-150 mu m. The distance between two adjacent first bumps in the column direction is 100-150 mu m. The second bumps are arranged in rows and columns along two intersecting directions. The distance between two adjacent second bumps in the row direction is 100-150 mu m. The distance between two adjacent second bumps in the column direction is 100-150 mu m.

7. The memory chip of claim 1, wherein, The memory chip comprises a plurality of memory units, and at least part of the memory units are arranged around the logic die.

8. The memory chip of claim 1, wherein, The logic die comprises an artificial intelligence die. The memory unit comprises a dynamic random access memory and / or a static random access memory. The memory unit and the logic die are connected through a D2D PHY, which comprises a universal chip interconnection protocol, an on-chip write-only bus or an advanced interconnection bus. The packaging substrate has multiple layers.

9. The memory chip of claim 1, wherein, The packaging substrate comprises an organic packaging substrate or a glass substrate. The application further relates to a memory chip comprising the memory unit according to any one of claims 1-9.

10. An electronic device, comprising: ​

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