Adapter card

Abstract

The embodiment of the utility model provides an adapter card. The adapter card comprises an adapter card body, a golden finger connector, a complex programmable logic device, a retimer and a plurality of GenZ 1C connectors, the golden finger connector is in plug-in connection with a standard PCIE slot on a server mainboard so as to receive a sideband signal and a PCIE signal sent by a server; dividing the sideband signal into a plurality of sub-sideband signals through a complex programmable logic device, and sending the sub-sideband signals to a plurality of GenZ 1C connectors; dividing the PCIe signal into a plurality of sub PCIe signals through a retimer, and sending the sub PCIe signals to the GenZ 1C connector; and the GenZ1C connector is connected with the EDSFF solid state disk so as to send the plurality of sub sideband signals and the plurality of sub PCIe signals to the EDSFF solid state disk. According to the embodiment of the utility model, the adapter card supports the connection with the EDSFF hard disk while being inserted into the standard PCIE slot, so that the storage capacity of the server is expanded.

Description

TECHNICAL FIELD

[0001] The utility model relates to server expansion technical field especially relates to adapter card. BACKGROUND

[0002] In modern data centers and high-performance computing environments, the storage capacity and data transfer rate of servers are key factors in determining their overall performance. PCIe (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) expansion slots, as an important interface within the server, play a crucial role in improving storage capacity and data transfer rate.

[0003] Due to the iterative update of server platforms, the PCIe resources provided by the new generation of central processing units (CPUs) are increasingly abundant with the increase in the number of PCIe expansion slots. However, in actual applications, the PCIe expansion slots are not fully utilized, resulting in servers that are always difficult to adapt to the growing data storage needs.

[0004] In the prior art, EDSFF (Enterprise and Data Center SSD Form Factor, Enterprise and Data Center SSD Form Factor) hard drives provide greater flexibility and scalability for the diverse storage needs of data centers by defining a series of form factors and specifications. Therefore, there is an urgent need for a design that can connect with PCIe expansion slots while also supporting EDSFF hard drive connections to optimize and upgrade the storage system. SUMMARY

[0005] The utility model embodiment provides adapter card, it aims at solving the problem that the server is difficult to adapt to the growing data storage needs caused by the PCIe expansion slot on the server in prior art not being fully utilized, through the design of supporting EDSFF hard drive connection while plugging with the standard PCIE slot on the server mainboard, realize the expansion of server storage capacity.

[0006] The utility model embodiment provides an adapter card, which comprises an adapter card body, a gold finger connector, a complex programmable logic device, a re-timer and a plurality of GenZ 1C connectors; the gold finger connector, the complex programmable logic device, the re-timer and the plurality of GenZ 1C connectors are all arranged on the adapter card body;

[0007] The gold finger connector is plugged with a standard PCIE slot on a server mainboard to receive the sideband signal and PCIe signal sent by the server, and send the sideband signal to the complex programmable logic device and send the PCIe signal to the re-timer; the sideband signal is divided into several sub-sideband signals by the complex programmable logic device and the several sub-sideband signals are sent to the several GenZ 1C connectors respectively; the PCIe signal is divided into several sub-PCIe signals by the re-timer and the several sub-PCIe signals are sent to the several GenZ 1C connectors; the several GenZ 1C connectors are connected with EDSFF solid state disks to send the several sub-sideband signals and the several sub-PCIe signals to the EDSFF solid state disks.

[0008] In some embodiments, the PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, the PERp / n3 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin and the PERp / n7 pin of the gold finger connector are connected with the re-timer to transmit PCIe x8 signal to the re-timer.

[0009] In some embodiments, the SMCLK / SMDAT pin on the gold finger connector is connected with the re-timer and the complex programmable logic device to transmit I2C signal to the re-timer and the complex programmable logic device respectively, wherein the I2C signal is used for the BMC on the mainboard to configure the re-timer, and the I2C signal is transmitted to the complex programmable logic device for data reading.

[0010] In some embodiments, the complex programmable logic device is connected with the gold finger connector, receives the sideband signal transmitted by the gold finger connector, and divides the sideband signal into a first sub-sideband signal and a second sub-sideband signal after processing the sideband signal; the sideband signal includes a PERST# signal and a gold finger B12-RSVD signal.

[0011] In some embodiments, the several GenZ 1C connectors include a first GenZ 1C connector and a second GenZ 1C connector; the first GenZ 1C connector receives the first sub-sideband signal, and the second GenZ 1C connector receives the second sub-sideband signal.

[0012] In some embodiments, the PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, and the PERp / n3 pin on the first GenZ 1C connector receive the first PCIe x4 signal transmitted from the retimer.

[0013] In some embodiments, the PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin, and the PERp / n7 pin on the second GenZ 1C connector receive the second PCIe x4 signal transmitted from the retimer.

[0014] In some embodiments, a buffer chip is disposed on the adapter card body; the buffer chip is used to receive the 100Mhz clock signal transmitted by the gold finger connector, and divide the 100Mhz clock signal into a first clock signal, a second clock signal, and a third clock signal; a first end of the buffer chip is connected with the REFCLK + / - pin on the gold finger connector to receive the 100Mhz clock signal, a second end of the buffer chip transmits the third clock signal to the retimer, and a third end of the buffer chip transmits the first clock signal to the REFCLKp / n0 pin on the first GenZ 1C connector, and transmits the second clock signal to the REFCLKp / n0 pin on the second GenZ 1C connector.

[0015] In some embodiments, an electrically erasable programmable read-only memory is further disposed on the adapter card body; the electrically erasable programmable read-only memory is connected with the retimer through a 12C bus, and is used to store configuration information of the retimer.

[0016] In some embodiments, the gold finger connector transmits a 12V power supply to the first GenZ 1C connector and the second GenZ 1C connector, and transmits a 3V3 power supply to the complex programmable logic device and the second GenZ 1C connector through the gold finger pin# pin.

[0017] The utility model embodiment provides a switching card, including switching card body, gold finger connector, complex programmable logic device, re -timer and a plurality of GenZ 1C connector, gold finger connector, complex programmable logic device, re -timer and a plurality of GenZ 1C connector all set up on switching card body, gold finger connector is inserted with the standard PCIE slot on the server mainboard, to receive the server transmission's sideband signal and PCIe signal, and the sideband signal is sent to complex programmable logic device, and the PCIe signal is sent to re -timer, through complex programmable logic device will the sideband signal be divided into a plurality of sub sideband signal and the plurality of sub sideband signal is sent to a plurality of GenZ 1C connector, through re -timer will the PCIe signal be divided into a plurality of sub PCIe signal and the plurality of sub PCIe signal is sent to a plurality of GenZ 1C connector, a plurality of GenZ 1C connector is connected with EDSFF solid state hard disk, to the plurality of sub sideband signal and the plurality of sub PCIe signal are sent to EDSFF solid state hard disk, the switching card of embodiment of the utility model is inserted with the standard PCIE slot simultaneously support and EDSFF hard disk connection, realizes the expansion of server storage capacity. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical scheme of the utility model embodiment, the following will be briefly introduced the drawings needed to be used in the embodiment description, obviously, the drawings in the following description is some embodiments of the utility model, for those skilled in the art, without creative labor, according to these drawings, other drawings can also be obtained.

[0019] Figure 1 The switching card provided in the embodiment of the utility model is schematically shown in the block diagram.

[0020] Figure 2 Another schematic block diagram of the switching card provided in the embodiment of the utility model is provided.

[0021] Figure 3 The schematic block diagram of the switching card connected with the server mainboard provided in the embodiment of the utility model is provided. DETAILED DESCRIPTION

[0022] The technical scheme in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model, obviously, the described embodiment is a part of the embodiment of the utility model, rather than all the embodiments. Based on the embodiment in the utility model, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the utility model.

[0023] It should be understood that the terms "comprises" and "comprising," when used in this specification and the following claims, indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] It should also be understood that the terms used in the specification and the appended claims are intended to describe particular embodiments and do not intend to limit the present application. As used in the specification and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0025] It should further be understood that the term "and / or" used in the specification and the appended claims means one or more of the associated listed items as well as all possible combinations of the items and includes the combinations.

[0026] Please refer to Figures 1 to 3 , Figure 1 a schematic block diagram of the adapter card provided by the present application; Figure 2 another schematic block diagram of the adapter card provided by the present application; Figure 3 a schematic block diagram of the adapter card and the server mainboard provided by the present application.

[0027] Please refer to Figure 1 and Figure 2 The adapter card provided by the present application comprises an adapter card body 100, a golden finger connector 200, a complex programmable logic device 300, a re-timer 400 and a plurality of GenZ 1C connectors 500; the golden finger connector 200, the complex programmable logic device 300, the re-timer 400 and the plurality of GenZ 1C connectors 500 are all arranged on the adapter card body 100;

[0028] The gold finger connector 200 is plugged with the standard PCIE slot on the server mainboard to receive the sideband signal and PCIe signal sent by the server, and send the sideband signal to the complex programmable logic device 300 and send the PCIe signal to the re-timer 400; the complex programmable logic device 300 divides the sideband signal into several sub-sideband signals and sends the several sub-sideband signals to the several GenZ 1C connectors 500 respectively; the re-timer 400 divides the PCIe signal into several sub-PCIe signals and sends the several sub-PCIe signals to the several GenZ 1C connectors 500; the several GenZ 1C connectors 500 are connected with the EDSFF solid state disk to send the several sub-sideband signals and the several sub-PCIe signals to the EDSFF solid state disk.

[0029] In the embodiment, EDSFF (Enterprise and Data Center SSD Form Factor) is a solid state disk (SSD) standard specially designed for data center and enterprise-level storage systems. It provides greater flexibility and scalability for the diverse storage needs of data centers by defining a series of form factors and specifications. GenZ 1C (Gen-Z 1 Channel Connector) connector, referred to as GenZ single-channel connector, is designed to meet the needs of high bandwidth, low latency and high efficiency in the data center and server market, and is mainly used to connect EDSFF solid state disks. PCIE (Peripheral Component Interconnect Express) slot is a computer bus interface standard used to connect data transmission between expansion cards and computer mainboards.

[0030] Specifically, the adapter card body 100 is provided with a gold finger connector 200, a complex programmable logic device 300, a re-timer 400 and several GenZ 1C connectors 500. The PCIe bandwidth of the standard PCIe slot in the embodiment is x8, and the gold finger connector 200 is used to butt joint with the standard PCIe slot on the server mainboard to receive the sideband signal and PCIe signal transmitted by the server mainboard, and send the sideband signal to the complex programmable logic device 300 and send the PCIe signal to the re-timer 400. That is, the gold finger connector 200 receives the PCIe x8 signal and the sideband signal transmitted by the server mainboard, and sends the sideband signal to the complex programmable logic device 300 and sends the PCIe x8 signal to the re-timer 400.

[0031] The complex programmable logic device 300 is used for managing sideband signals, and the retimer 400 is used for enhancing PCIe signals. Specifically, the complex programmable logic device 300 divides the sideband signals into several sub-sideband signals and sends these sub-sideband signals to several GenZ 1C connectors 500 respectively; the retimer 400 divides the PCIe signals into several sub-PCIe signals (i.e., PCIe x4 signals) and sends these sub-PCIe signals to several GenZ 1C connectors 500. Since the several GenZ 1C connectors 500 are connected to the EDSFF solid-state drive, it is possible to send several sub-sideband signals and several sub-PCIe signals to the EDSFF solid-state drive, ultimately expanding the server's storage capacity.

[0032] Specifically, in one embodiment, such as Figure 3 As shown, the server motherboard 600 is equipped with a complex programmable logic device (CPL) 610 and a central processing unit (CPU) 620. When the CPL 300 on the adapter card detects that an EDSFF solid-state drive (SSD) is inserted / not inserted, a signal is transmitted through a reserved pin (i.e., the RSVD pin, which can use a baud rate of 115200bps) to the CPL 300 on the server motherboard 600 to indicate the presence status of the EDSFF SSD. If the CPL 300 detects a change in the presence status of the EDSFF SSD, it sends an interrupt signal to the CPU 620 via the I2C bus. After receiving the interrupt signal, the CPU 620 reads the CPL 300 on the motherboard via the I2C bus to obtain the specific hard drive insertion / non-insertion event and processes the corresponding PCIe information.

[0033] For example, when the EDSFF solid state hard disk is connected to the adapter card, the A12 pin signal PRSNT0# of the GenZ 1C connector 500 is in a low state; at this time, the complex programmable logic device 300 sends the in-place information of the EDSFF solid state hard disk to the mainboard complex programmable logic device 610 on the server mainboard 600 through the RSVD signal of the B12 pin of the gold finger connector 200; the mainboard complex programmable logic device 610 detects the in-place information of the EDSFF solid state hard disk and sends an interrupt information to the central processing unit 620 through the interrupt signal of the I2C bus; after receiving the interrupt signal, the central processing unit 620 sends a read instruction to the mainboard complex programmable logic device 610 through the I2C bus; after receiving the read instruction, the mainboard complex programmable logic device 610 reads the register in the complex programmable logic device 300 through the RSVD signal to obtain the specific slot information of the EDSFF solid state hard disk inserted, and processes the corresponding PCIe signal and sends the sideband signal to control the EDSFF solid state hard disk; the complex programmable logic device 300 receives the RSVD signal and analyzes the serial data carried by the RSVD signal, and processes the sideband signal to generate a first sub-sideband signal and a second sub-sideband signal; finally, the complex programmable logic device 300 sends the first sub-sideband signal and the second sub-sideband signal to the plurality of GenZ 1C connectors 500 respectively. Through the operation of the above entire process, the expansion of the server is realized.

[0034] In addition, when the hard disk has an error or needs to be positioned, etc., the central processing unit 620 transmits the corresponding LED signal to the mainboard complex programmable logic device 610 through the I2C bus, the mainboard complex programmable logic device 610 decodes the serial signal and then transmits the serial signal to the complex programmable logic device 300 on the adapter card through the RSVD signal, the CPLD on the adapter card receives the signal and decodes it, and controls the LED signal on the GenZ 1C connector 500 to realize the control of the EDSFF solid state hard disk LED.

[0035] In the embodiments of the present application, on the one hand, the PCIe x8 signal is enhanced and processed by the re-timer 400, which can effectively improve the strength and stability of the signal, reduce the attenuation and distortion of the signal in the transmission process, and ensure the integrity and accuracy of data transmission; on the other hand, the converted PCIe x4 signal is transmitted to the EDSFF solid state hard disk through the plurality of GenZ 1C connectors 500, which can fully utilize the advantage of multi-channel parallel to further improve the speed and bandwidth utilization of data transmission.

[0036] In addition, in order to more efficiently use the PCIe expansion slot resources in the server mainboard, in the embodiment of the application, by adopting the EDSFF hard disk, the server data center can more effectively use the PCIe expansion slot for expanding the storage capacity of the server, not only realizing the optimization and upgrading of the storage system, but also promoting the continuous growth and technological innovation of the business.

[0037] Specifically, when the EDSFF solid state disk is inserted or pulled out of the adapter card, the complex programmable logic device 300 can detect that the A12 pin signal PRSNT0# on the GenZ 1C connector 500 changes accordingly. Specifically, the EDSFF solid state disk insertion or pull-out adapter card process is as follows:

[0038] 01) Determine whether the EDSFF solid state disk is connected to or not connected to the adapter card;

[0039] 02) When the EDSFF solid state disk is connected to the adapter card, the A12 pin signal PRSNT0# of the GenZ 1C connector 500 is in a low level state;

[0040] 03) When the EDSFF solid state disk is not connected to the adapter card, the A12 pin signal PRSNT0# of the GenZ 1C connector 500 is in a high level state;

[0041] 04) The complex programmable logic device 300 sends the in-situ information of the EDSFF solid state disk through the RSVD signal on the B12 pin of the gold finger connector 200 to the server mainboard 600 end;

[0042] 05) The mainboard end reads the register in the complex programmable logic device 300 through the RSVD signal to obtain the in-situ information of the EDSFF solid state disk, and processes and sends the control EDSFF solid state disk sideband signal corresponding to the PCIe signal;

[0043] 06) The complex programmable logic device 300 receives the RSVD signal and parses the serial data carried by the RSVD signal, and processes and generates the first sub-sideband signal and the second sub-sideband signal;

[0044] 07) Send the first sub-sideband signal and the second sub-sideband signal to a plurality of GenZ 1C connectors 500 respectively.

[0045] Further, in an embodiment, the PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, the PERp / n3 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin and the PERp / n7 pin of the gold finger connector 200 are connected with the re-timer 400 to transmit the PCIe x8 signal to the re-timer 400.

[0046] In the embodiment, the gold finger connector 200 is provided with a plurality of pins for transmitting PCIe signal, wherein the PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, the PERp / n3 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin and the PERp / n7 pin are connected with the re-timer 400 to transmit the PCIe x8 signal received from the server to the re-timer 400.

[0047] Specifically, the PCIe bandwidth transmitted by the standard PCIE slot on the server motherboard is x8, since the gold finger connector 200 is plugged with the standard PCIE slot on the server motherboard and connected with the re-timer 400, after the gold finger connector 200 receives the PCIe x8 signal transmitted from the standard PCIE slot on the server, the PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, the PERp / n3 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin and the PERp / n7 pin are connected with the re-timer 400 to transmit the PCIe x8 signal received from the server to the re-timer 400, the re-timer 400 enhances and re-distributes the received PCIe x8 signal into two PCIe x4 signals, and transmits the two newly distributed PCIe x4 signals to a plurality of GenZ 1C connectors 500 respectively.

[0048] In an embodiment, as shown in FIG. 6, the gold finger connector 200 is connected with the re-timer 400 to transmit the PCIe x8 signal to the re-timer 400. Figure 2As shown, the SMCLK / SMDAT pins on the gold finger connector 200 are connected with the re-timer 400 and the complex programmable logic device 300 to transmit the I2C signals to the re-timer 400 and the complex programmable logic device 300, respectively, wherein the I2C signals are used for the BMC on the motherboard to configure the re-timer 400, and the I2C signals transmitted to the complex programmable logic device 300 are used for reading data.

[0049] In the embodiment, when the gold finger connector 200 is connected with the standard PCIe slot on the server, the BMC (Baseboard Management Controller) on the motherboard of the server can directly configure the re-timer 400 through the SMCLK / SMDAT pins of the gold finger connector 200 connected with the re-timer 400, which reduces the intermediate links of signal transmission and improves the configuration efficiency and accuracy.

[0050] The I2C signals are connected to the complex programmable logic device 300 through the SMCLK / SMDAT pins of the gold finger connector 200, which can ensure that the EDSFF solid state disk can normally read and write to realize the expansion of the server. In an embodiment, one or more registers are arranged in the complex programmable logic device 300 to store a set of special definition values. When the motherboard end BMC obtains the set of special definition values through the I2C signal when the system is powered on, the PCIe bandwidth of the standard PCIe slot is processed as two-way PCIe x4 signal.

[0051] Specifically, in the embodiment, the read and write steps of the EDSFF solid state disk inserted into the adapter card are as follows:

[0052] 10) System power-on;

[0053] 20) The complex programmable logic device 300 on the adapter card sends the PCIe signal resource allocation demand to the BMC at the motherboard end through the I2C signal;

[0054] 30) After the motherboard end BMC receives the resource allocation application of the PCIe signal, the information is sent to the PCH (Platform Controller Hub), and the BIOS (Basic Input / Output System) completes the final PCIe resource division and completes the docking with the EDSFF solid state disk.

[0055] In an embodiment, as Figure 2As shown, the complex programmable logic device 300 is connected with the golden finger connector 200, receives the sideband signal transmitted by the golden finger connector 200, and divides the sideband signal into a first sub-sideband signal and a second sub-sideband signal after processing the sideband signal; the sideband signal includes a PERST# signal and a golden finger B12-RSVD signal.

[0056] In this embodiment, the complex programmable logic device 300 is connected with the golden finger connector 200, and after the golden finger connector 200 sends the sideband signal received from the server to the complex programmable logic device 300, the complex programmable logic device 300 receives and processes the sideband signal to obtain a first sub-sideband signal and a second sub-sideband signal. The complex programmable logic device 300 can process and enhance the sideband signal received from the golden finger connector 200, ensure the integrity and stability of the sideband signal during transmission, reduce the attenuation and interference of the sideband signal, and thus improve the reliability of the sideband signal transmission.

[0057] The sideband signal includes a PERST# signal and a golden finger B12-RSVD signal; the first sub-sideband signal and the second sub-sideband signal each include a PERST0 signal, an LED signal, a DUPORTEN# signal, and a PWRDIS signal.

[0058] Further, as shown in the figure, Figure 2 The plurality of GenZ 1C connectors 500 includes a first GenZ 1C connector 510 and a second GenZ 1C connector 520; the first GenZ 1C connector 510 receives the first sub-sideband signal, and the second GenZ 1C connector 520 receives the second sub-sideband signal.

[0059] In this embodiment, the GenZ 1C connector 500 has a terminal pitch of 0.6 mm, can provide higher pin density, and can realize more data transmission channels in the same space to improve the data transmission rate. Therefore, after the complex programmable logic device 300 receives the sideband signal transmitted by the golden finger connector 200, the complex programmable logic device 300 processes the sideband signal internally to obtain a first sub-sideband signal and a second sub-sideband signal, transmits the processed first sub-sideband signal to the first GenZ 1C connector 510, and transmits the second sub-sideband signal to the second GenZ 1C connector 520. When the plurality of GenZ 1C connectors 500 are connected with the EDSFF hard disk, the data transmission rate of the sideband signal can be effectively improved.

[0060] In an embodiment, the PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, and the PERp / n3 pin on the first GenZ 1C connector 510 receive the first PCIe x4 signal sent from the retimer 400.

[0061] In the present embodiment, the PCIe bandwidth transmitted by the standard PCIE slot on the server motherboard is x8, and the PCIe x8 signal includes PETp / n0-7 signals and PERp / n0-7 signals, which together include 8 Lanes (a Lane includes a group of TX signals and RX signals, such as PETp / n0 and PERp / n0 to form Lane0), i.e., Lane0-7, wherein Lane0-3 (i.e., PETp / n0-3 signals and PERp / n0-3 signals) are processed by the retimer 400 as the first PCIe x4 signal, and the first PCIe x4 signal is sent to the first GenZ 1C connector 510. For the first GenZ 1C connector 510, the PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, and the PERp / n3 pin on the first GenZ 1C connector 510 can receive the first PCIe x4 signal sent from the retimer 400.

[0062] Further in an embodiment, the PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin, and the PERp / n7 pin on the second GenZ 1C connector 520 receive the second PCIe x4 signal sent from the retimer 400.

[0063] In this embodiment, the PCIe bandwidth transmitted by the standard PCIe slot on the server motherboard is x8. The PCIe x8 signal includes PETp / n0-7 signal and PERp / n0-7 signal, which contains a total of 8 lanes (one lane contains a set of TR signals and RX signals, such as PETp / n0 and PERp / n0 forming Lane 0), namely Lane 0-7. Among them, Lane 4-7 (i.e. PETp / n4-7 signal and PERp / n4-7 signal) is processed by the retimer 400 and used as the second PCIe x4 signal, and the second PCIe x4 signal is sent to the second GenZ 1C connector 520. For the second GenZ 1C connector 520, the second PCIe x4 signal sent from the retimer 400 can be received through the PETp / n4, PETp / n5, PETp / n6, PETp / n7, PERp / n4, PERp / n5, PERp / n6 and PERp / n7 pins on the second GenZ 1C connector 520.

[0064] In one embodiment, such as Figure 2 As shown, a buffer chip 700 is provided on the adapter card body; the buffer chip 700 is used to receive the 100MHz clock signal transmitted by the gold finger connector 200, and divide the 100MHz clock signal into a first clock signal, a second clock signal, and a third clock signal; the first end of the buffer chip 700 is connected to the REFCLK+ / - pin on the gold finger connector 200 to receive the 100MHz clock signal, the second end of the buffer chip 700 sends the third clock signal to the retimer 400, the third end of the buffer chip 700 sends the first clock signal to the REFCLKp / n0 pin on the first GenZ 1C connector 510, and sends the second clock signal to the REFCLKp / n0 pin on the second GenZ 1C connector 520.

[0065] In the embodiment, the buffer chip 700 is an integrated circuit for improving signal driving capability, optimizing timing and enhancing signal. The buffer chip 700 is connected with the REFCLK + / - pin on the latch connector 200, and the latch connector 200 sends a 100Mhz clock signal to the buffer chip 700 through the REFCLK + / - pin. After receiving the clock signal, the buffer chip 700 expands the received 100Mhz clock signal into three signals, i.e., a first clock signal, a second clock signal and a third clock signal. At the same time, the buffer chip 700 sends the first clock signal and the second clock signal to the REFCLKp / n0 pin of the GenZ 1C connector 500, respectively, and sends the third clock signal to the re-timer 400.

[0066] The buffer chip 700 can effectively distribute a single clock source (i.e., the 100Mhz clock signal on the latching connector 200) to multiple objects. This distribution mechanism reduces the redundancy of the clock source, simplifies the design of the adapter card, and reduces the cost.

[0067] In an embodiment, as shown in Figure 2 The adapter card body is also provided with an electrically erasable programmable read-only memory 800. The electrically erasable programmable read-only memory 800 is connected with the re-timer 400 through a 12C bus, and is used to store the configuration information of the re-timer 400.

[0068] In the embodiment, the electrically erasable programmable read-only memory 800 (EEPROM) is a non-volatile memory with the characteristics of electrically erasable, programmable and read-only. The 12C bus is mainly used to connect low-speed peripheral devices.

[0069] By storing the configuration information of the re-timer 400 in the electrically erasable programmable read-only memory 800, the re-timer 400 can be conveniently maintained and upgraded. When it is necessary to change the configuration or upgrade the re-timer 400, only the new configuration information needs to be written into the electrically erasable programmable read-only memory 800 through the 12C bus, without the need to make large-scale changes to the system hardware, greatly enhancing the maintainability and scalability of the system.

[0070] In addition, as shown in Figure 2As shown, the adapter card body in the embodiment of the present application is also provided with a plurality of groups of voltage conversion circuits 900, and the re-timer 400 is connected with the gold finger connector 200 through the plurality of groups of voltage conversion circuits 900. Since the voltage used by the re-timer 400 when working is usually small, the 12V power provided by the gold finger connector 200 cannot be directly received for use, so it is necessary to use the voltage conversion circuit to convert the 12V power provided by the gold finger connector 200 to match the different voltage requirements; at the same time, the voltage required by different re-timers 400 when working may be different, so a plurality of groups of voltage conversion circuits 900 are required. In actual application, the plurality of groups of voltage conversion circuits 900 can meet the working requirements of the re-timer 400 through the converted voltage.

[0071] In an embodiment, as shown in Figure 2 The gold finger connector 200 transmits 12V power to the first GenZ 1C connector 510 and the second GenZ 1C connector 520 through the gold finger pin# pin, and transmits 3V3 power to the complex programmable logic device 300 and the second GenZ 1C connector 520.

[0072] In the embodiment, a plurality of pins for transmitting power are arranged in the gold finger connector 200, and the gold finger pin# pin for transmitting different power can be arranged according to the actual application. Specifically, 12V power is transmitted to the first GenZ 1C connector 510 and the second GenZ 1C connector 520 through the gold finger pin# pin, and 3V3 power is transmitted to the complex programmable logic device 300 and the second GenZ 1C connector 520 through the gold finger pin# pin. Different voltages of power can be transmitted through the gold finger connector 200 to meet the power requirements of different components, so that the design of the adapter card is more flexible, which is conducive to improving the stability and reliability of the adapter card.

[0073] The utility model embodiment provides a switching card, including switching card body 100, gold finger connector 200, complex programmable logic device 300, re-timer 400 and a plurality of GenZ 1C connector 500, gold finger connector 200 complex programmable logic device 300 re-timer 400 and a plurality of GenZ 1C connector 500 all are arranged on switching card body 100, gold finger connector 200 is inserted with the standard PCIE slot on the server mainboard, to receive the server sent sideband signal and PCIe signal, and the sideband signal is sent to complex programmable logic device 300, and the PCIe signal is sent to re-timer 400, through complex programmable logic device 300 the sideband signal is divided into a plurality of sub sideband signals and the plurality of sub sideband signals are sent to a plurality of GenZ 1C connector 500 respectively, through re-timer 400 the PCIe signal is divided into a plurality of sub PCIe signals and the plurality of sub PCIe signals are sent to a plurality of GenZ 1C connector 500, a plurality of GenZ 1C connector 500 is connected with EDSFF solid state disk, to the plurality of sub sideband signals and the plurality of sub PCIe signals are sent to EDSFF solid state disk.The switching card in the utility model embodiment is inserted with the standard PCIE slot simultaneously supports and is connected with EDSFF hard disk, realizes the expansion of server storage capacity.

[0074] The above is merely a specific implementation of the present application, but the scope of protection of the present application is not limited thereto. Any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims.

Claims

1. A switch card, comprising: The adapter card body, the gold finger connector, the complex programmable logic device, the re-timer, and a plurality of GenZ 1C connectors are provided on the adapter card body. The gold finger connector is inserted into a standard PCIE slot on a server mainboard to receive a sideband signal and a PCIe signal sent by the server, and send the sideband signal to the complex programmable logic device and send the PCIe signal to the re-timer; the complex programmable logic device divides the sideband signal into a plurality of sub-sideband signals and sends the plurality of sub-sideband signals to the plurality of GenZ 1C connectors respectively; the re-timer divides the PCIe signal into a plurality of sub-PCIe signals and sends the plurality of sub-PCIe signals to the plurality of GenZ 1C connectors; the plurality of GenZ 1C connectors are connected with an EDSFF solid state disk to send the plurality of sub-sideband signals and the plurality of sub-PCIe signals to the EDSFF solid state disk.

2. The adapter card of claim 1, wherein, The PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin, the PERp / n3 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin, and the PERp / n7 pin of the gold finger connector are connected with the re-timer to transmit a PCIe x8 signal to the re-timer.

3. The riser card of claim 1, wherein, The SMCLK / SMDAT pin on the gold finger connector is connected with the re-timer and the complex programmable logic device to transmit a 12C signal to the re-timer and the complex programmable logic device respectively, wherein the 12C signal is used for the BMC on the mainboard to configure the re-timer, and the 12C signal is transmitted to the complex programmable logic device for data reading.

4. The adapter card of claim 1, wherein, The complex programmable logic device is connected with the gold finger connector to receive a sideband signal transmitted by the gold finger connector, and divide the sideband signal into a first sub-sideband signal and a second sub-sideband signal after processing the sideband signal; the sideband signal includes a PERST# signal and a gold finger B12-RSVD signal.

5. The adapter card of claim 4, wherein, The plurality of GenZ 1C connectors includes a first GenZ 1C connector and a second GenZ 1C connector; the first GenZ 1C connector receives the first sub-sideband signal, and the second GenZ 1C connector receives the second sub-sideband signal.

6. The riser card of claim 5, wherein, The PETp / n0 pin, the PETp / n1 pin, the PETp / n2 pin, the PETp / n3 pin, the PERp / n0 pin, the PERp / n1 pin, the PERp / n2 pin and the PERp / n3 pin on the first GenZ 1C connector receive the first PCIe x4 signal transmitted from the re-timer.

7. The adapter card of claim 5, wherein, The PETp / n4 pin, the PETp / n5 pin, the PETp / n6 pin, the PETp / n7 pin, the PERp / n4 pin, the PERp / n5 pin, the PERp / n6 pin and the PERp / n7 pin of the second GenZ 1C connector receive the second PCIe x4 signal transmitted from the re-timer.

8. The adapter card of claim 5, wherein, The adapter card body is provided with a buffer chip; the buffer chip is used for receiving the 100Mhz clock signal transmitted by the gold finger connector and dividing the 100Mhz clock signal into a first clock signal, a second clock signal and a third clock signal; a first end of the buffer chip is connected with a REFCLK + / - pin on the gold finger connector to receive the 100Mhz clock signal, a second end of the buffer chip transmits the third clock signal to the re-timer, and a third end of the buffer chip transmits the first clock signal to a REFCLKp / n0 pin on the first GenZ 1C connector and transmits the second clock signal to a REFCLKp / n0 pin on the second GenZ 1C connector.

9. The riser card of claim 1, wherein, The adapter card body is further provided with an electrically erasable programmable read-only memory; the electrically erasable programmable read-only memory is connected with the re-timer through a 12C bus, and the electrically erasable programmable read-only memory is used for storing configuration information of the re-timer.

10. The adapter card of claim 5, wherein, The gold finger connector transmits a 12V power supply to the first GenZ 1C connector and the second GenZ 1C connector and a 3V3 power supply to the complex programmable logic device and the second GenZ 1C connector through a gold finger pin#.

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