Package assembly

Abstract

The embodiment of the utility model provides a packaging assembly. The packaging assembly comprises a chip assembly; the packaging substrate is electrically connected with the chip assembly, the packaging substrate comprises a first main body layer and a first bonding pad group with a plurality of first bonding pads, the first bonding pad group is located on the side, away from the chip assembly, of the first main body layer, and a first initial bonding pad distance is formed between every two adjacent first bonding pads; the circuit board is arranged on the side, away from the chip assembly, of the packaging substrate in the first direction and comprises a second main body layer and a second bonding pad set with a plurality of second bonding pads, the second bonding pad set is configured to be electrically connected with the first bonding pad set, and a second initial bonding pad distance is formed between every two adjacent second bonding pads; wherein a first thermal expansion coefficient of the first body layer and a second thermal expansion coefficient of the second body layer have a first ratio, the first initial pad pitch and the second initial pad pitch have a second ratio, one of the first ratio and the second ratio is less than 1, and the other one of the first ratio and the second ratio is greater than 1.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor packaging, and in particular, to a packaging assembly. BACKGROUND

[0002] With the continuous development of semiconductor technology, for example, the artificial intelligence chip computing power increases exponentially, and the chip size and chip packaging size are becoming larger and larger. With the continuous increase of the chip packaging size, the solder joint stress after the chip packaging and the circuit board are welded also brings great challenges, and excessive solder joint stress may cause solder joint cracking problems. How to improve the solder joint cracking problem caused by solder joint stress to break through the chip design bottleneck is an important research topic in the field. SUMMARY

[0003] According to at least one embodiment of the present disclosure, a packaging assembly is provided, comprising: a chip assembly; a packaging substrate disposed on one side of the chip assembly in a first direction and electrically connected with the chip assembly, wherein the packaging substrate comprises a first main layer having a first coefficient of thermal expansion and a first pad group having a plurality of first pads, the first pad group is located on a side of the first main layer away from the chip assembly, and adjacent first pads have a first initial pad pitch; and a circuit board disposed on a side of the packaging substrate away from the chip assembly in the first direction and comprising a second main layer having a second coefficient of thermal expansion and a second pad group having a plurality of second pads, the second pad group is located on a side of the second main layer and is configured to be electrically connected with the first pad group, and adjacent second pads have a second initial pad pitch; wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion have a first ratio, and the first initial pad pitch and the second initial pad pitch have a second ratio, wherein one of the first ratio and the second ratio is less than 1, and the other of the first ratio and the second ratio is greater than 1.

[0004] In the packaging assembly provided by at least one embodiment of the present disclosure, the first coefficient of thermal expansion of the first main layer is less than the second coefficient of thermal expansion of the second main layer, and the first initial pad pitch is greater than the second initial pad pitch.

[0005] In the packaging assembly provided by at least one embodiment of the present disclosure, the first pad group has a first size, the first size is a center distance between two end first pads in the same row or the same column in the plurality of first pads; the second pad group has a second size, the second size is a center distance between two end second pads in the same row or the same column in the plurality of second pads; and the first size is greater than the second size.

[0006] In the packaging assembly according to at least one embodiment of the present disclosure, a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than 0 and less than or equal to 0.67, and a ratio of the second dimension to the first dimension ranges from 99.8% to 99.99%.

[0007] In the packaging assembly according to at least one embodiment of the present disclosure, a number of the first plurality of pads is the same as a number of the second plurality of pads.

[0008] In the packaging assembly according to at least one embodiment of the present disclosure, the first plurality of pads is arranged at equal intervals, and the second plurality of pads is arranged at equal intervals.

[0009] In the packaging assembly according to at least one embodiment of the present disclosure, the first plurality of pads and the second plurality of pads each have a same pad size.

[0010] In the packaging assembly according to at least one embodiment of the present disclosure, the first plurality of pads and the second plurality of pads each have a same pad size.

[0011] In the packaging assembly according to at least one embodiment of the present disclosure, the first plurality of pads and the second plurality of pads each have a same pad size.

[0012] In the packaging assembly according to at least one embodiment of the present disclosure, in each offset pad connection pair, a pad center of the second pad is closer to the pad center of the reference pad connection pair in the second direction than the pad center of the first pad.

[0013] In the packaging assembly according to at least one embodiment of the present disclosure, the first plurality of pads and the second plurality of pads each have a same pad size.

[0014] In the packaging assembly according to at least one embodiment of the present disclosure, an overlapping area of the first pad and the second pad in the first direction in the first offset pad connection pair is greater than an overlapping area of the first pad and the second pad in the first direction in the second offset pad connection pair.

[0015] In the packaging assembly according to at least one embodiment of the present disclosure, the packaging assembly further includes a plurality of conductive connectors respectively configured to connect the plurality of first pads of the packaging substrate and the plurality of second pads of the circuit board to solder the packaging substrate and the circuit board.

[0016] In the packaging assembly according to at least one embodiment of the present disclosure, the packaging substrate is configured to have a first pad pitch between the adjacent first pads after being soldered with the circuit board, the circuit board is configured to have a second pad pitch between the adjacent second pads after being soldered with the packaging substrate, and the first pad pitch is equal to the second pad pitch.

[0017] In the packaging assembly according to at least one embodiment of the present disclosure, the first pad pitch is greater than the first initial pad pitch, the second pad pitch is greater than the second initial pad pitch, and a difference between the second pad pitch and the second initial pad pitch is greater than a difference between the first pad pitch and the first initial pad pitch.

[0018] In the packaging assembly according to at least one embodiment of the present disclosure, the packaging substrate is configured to align first pad centers of the plurality of first pads with second pad centers of the plurality of second pads of the circuit board in the first direction after being soldered with the circuit board.

[0019] In the packaging assembly according to at least one embodiment of the present disclosure, the plurality of conductive connectors are respectively connected to the corresponding first pad and the second pad, and are symmetrical with respect to a pad center line of the first pad and the second pad, the pad center line extending through the first pad center of the first pad and the second pad center of the second pad in the first direction.

[0020] The package assembly provided by at least one embodiment of the present disclosure includes: a chip assembly; a package substrate disposed on one side of the chip assembly in a first direction and electrically connected to the chip assembly, wherein the package substrate includes a first main body layer and a first pad located on a side of the first main body layer away from the chip assembly; a circuit board disposed on a side of the package substrate away from the chip assembly in the first direction and including a second main body layer and a second pad located on a side of the second main body layer close to the package substrate; and a conductive connecting member located between the first pad of the package substrate and the second pad of the circuit board to solder the package substrate and the circuit board, wherein the package substrate and the circuit board have different coefficients of thermal expansion, and a first pad center of the first pad and a second pad center of the second pad are configured to be offset in a second direction parallel to a main surface of the circuit board before the conductive connecting member is completely soldered and aligned in the first direction perpendicular to the main surface of the circuit board after the conductive connecting member is completely soldered.

[0021] In the package assembly provided by at least one embodiment of the present disclosure, the coefficient of thermal expansion of the package substrate is less than the coefficient of thermal expansion of the circuit board; and the first pad has a first offset amount in the second direction during soldering, the second pad has a second offset amount in the second direction during soldering, and the first offset amount is less than the second offset amount.

[0022] In the package assembly provided by at least one embodiment of the present disclosure, the offset distance of the first pad center and the second pad center in the second direction before the conductive connecting member is completely soldered is equal to the difference between the second offset amount and the first offset amount.

[0023] The package assembly provided by at least one embodiment of the present disclosure can reduce or avoid the offset of the corresponding pads of the package substrate and the circuit board after soldering, and improve the device reliability of the package assembly. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described in the following description are only related to some embodiments of the present disclosure, but not limit the present disclosure.

[0025] Figure 1 A schematic cross-sectional view of a package structure is shown.

[0026] Figure 2 A schematic cross-sectional view of a package structure is shown. Figure 1 A partial enlarged schematic view of a package structure before the package substrate and the printed circuit board are soldered is shown.

[0027] Figure 3 shows Figure 1 a partial enlarged view of the encapsulation structure after the encapsulation substrate and the printed circuit board are soldered.

[0028] Figure 4 shows a schematic cross-sectional view of a package assembly according to some embodiments of the present disclosure.

[0029] Figure 5A shows a schematic plan view of an initial structure of a first set of pads of the encapsulation substrate and a second set of pads of the circuit board before soldering in a package assembly according to some embodiments of the present disclosure; Figure 5B shows a schematic plan view of a first set of pads of the encapsulation substrate and a second set of pads of the circuit board after soldering in a package assembly according to some embodiments of the present disclosure.

[0030] Figure 6A shows a schematic partial enlarged cross-sectional view of a package assembly before soldering according to some embodiments of the present disclosure; Figure 6B shows a schematic partial enlarged cross-sectional view of a package assembly after soldering according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort fall within the scope of the present disclosure.

[0032] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The words “first”, “second” and similar words of comparison are not used to denote any order, quantity or importance, but are used to distinguish different components. The words “comprise”, “contain” and similar words are intended to encompass the elements or objects listed thereafter, their equivalents, and other elements or objects not listed, without excluding other elements or objects. The words “connect” or “connected” or similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0033] Figure 1 shows a schematic cross-sectional view of a package structure. Figure 2 shows Figure 1 a partial enlarged view of the package structure before the encapsulation substrate and the printed circuit board are soldered. Figure 3 shows Figure 1A partial enlarged view of the package structure after the package substrate and the printed circuit board are soldered.

[0034] Referring to Figure 1 In some examples, the package structure includes a chip package and a printed circuit board 5; the chip package includes a chip component 1 and a substrate 3, and the chip package can be soldered to the printed circuit board 5 by solder balls 6, wherein the pads on the substrate 3 and the pads on the printed circuit board 5 correspond to each other and are electrically connected by the solder balls 6. Generally, the pads of the substrate 3 and the corresponding pads of the printed circuit board 5 usually adopt the same design. For example, referring to Figure 1 and Figure 2 After the pad design of the substrate 3 is known, the pad design parameters (such as pad size, pad pitch, etc.) of the substrate 3 are introduced into the corresponding pad design of the printed circuit board 5 in a 1:1 ratio, for example, so that the pad size, pad pitch, etc. of the substrate 3 completely correspond to the pad size, pad pitch, etc. of the printed circuit board 5, so that the corresponding pad positions of the substrate 3 and the printed circuit board 5 correspond to each other and are aligned with each other. For example, the pad center of the first conductive pad 2 in the substrate 3 and the pad center of the second conductive pad 4 in the printed circuit board 5 are aligned with each other in the direction perpendicular to the main surface of the printed circuit board 5, and the symmetry axis of the first conductive pad 2 and the symmetry axis of the second conductive pad 4 coincide with each other.

[0035] Referring to Figure 1 , Figure 2 and Figure 3 However, when soldering the substrate 3 and the printed circuit board 5 using the solder balls 6, due to the mismatch of the coefficients of thermal expansion of the substrate 3 and the printed circuit board 5, different degrees of thermal deformation (for example, thermal expansion) of the substrate 3 and the printed circuit board 5 can occur during high-temperature soldering, which in turn causes the substrate pads and the printed circuit board pads originally designed with the same design parameters to be offset after soldering. For example, as shown in Figure 3 , after soldering is completed, the first conductive pad 2 of the substrate 3 and the second conductive pad 4 of the printed circuit board 5 are offset from each other in the horizontal direction parallel to the main surface of the printed circuit board 5. For example, the pad center of the first conductive pad 2 and the pad center of the second conductive pad 4 are offset from each other in the horizontal direction and are no longer aligned in the vertical direction, that is, the symmetry axis of the first conductive pad 2 and the symmetry axis of the second conductive pad 4 are offset from each other and do not coincide. In this way, the solder ball 6 will also be tilted with the offset of the corresponding conductive pad, and such tilt can generate additional residual stress on the local part (for example, the bottom) of the solder ball. For example, as shown in Figure 3 , the bottom part 7 of the solder ball 6 can suffer greater stress, which in turn can cause the solder ball to crack at this part and can affect the device reliability of the package structure.

[0036] To this end, embodiments of the present disclosure provide a packaging assembly that can avoid the above-mentioned reliability problems caused by the mismatch of the coefficients of thermal expansion between the packaging substrate and the circuit board.

[0037] For example, embodiments of the present disclosure provide a packaging assembly, comprising: a chip assembly; a packaging substrate disposed on one side of the chip assembly in a first direction and electrically connected with the chip assembly, wherein the packaging substrate comprises a first main layer having a first coefficient of thermal expansion and a first pad group having a plurality of first pads, the first pad group is located on a side of the first main layer away from the chip assembly, and the first initial pad pitch is provided between adjacent first pads; and a circuit board disposed on a side of the packaging substrate away from the chip assembly in the first direction and comprising a second main layer having a second coefficient of thermal expansion and a second pad group having a plurality of second pads, the second pad group is located on a side of the second main layer and is configured to be electrically connected with the first pad group, and a second initial pad pitch is provided between adjacent second pads; wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion have a first ratio, and the first initial pad pitch and the second initial pad pitch have a second ratio, wherein one of the first ratio and the second ratio is less than 1, and the other of the first ratio and the second ratio is greater than 1.

[0038] In embodiments of the present disclosure, in the case that the packaging substrate and the circuit board have different coefficients of thermal expansion, the first initial pad pitch of the packaging substrate and the second initial pad pitch of the circuit board are designed differently, so that one of the first ratio and the second ratio is less than 1, and the other of the first ratio and the second ratio is greater than 1, so that the deviation of the first initial pad pitch and the second initial pad pitch can compensate for the difference in the amount of offset when the packaging substrate and the circuit board have different thermal deformations due to different coefficients of thermal expansion, thereby reducing or avoiding the offset of the corresponding pads of the packaging substrate and the circuit board after welding, further reducing or avoiding the problem of cracking of the solder joints of the packaging substrate and the circuit board after welding due to the offset of the pads, thereby improving the device reliability of the packaging assembly after welding.

[0039] Figure 4 A schematic cross-sectional view of a packaging assembly according to some embodiments of the present disclosure is shown. Figure 5A A schematic plan view of the initial structure of the first pad group of the packaging substrate and the second pad group of the circuit board in the packaging assembly before welding according to some embodiments of the present disclosure is shown. Figure 5B A schematic plan view of the first pad group of the packaging substrate and the second pad group of the circuit board in the packaging assembly after welding according to some embodiments of the present disclosure is shown. Figure 6A A schematic partial enlarged cross-sectional view of the packaging assembly before welding according to some embodiments of the present disclosure is shown. Figure 6BA schematic partial enlarged cross-sectional view of the package assembly after soldering is shown in accordance with some embodiments of the present disclosure. For example, Figure 6A and Figure 6B are enlarged views of region A in Figure 4 , and can be cross-sectional views taken along line I-I' of Figure 5A and Figure 5B , respectively.

[0040] Referring to Figure 4 , in some embodiments, the package assembly 500 includes the chip assembly 150, the package substrate 200, and the circuit board 300. The package substrate 200 is disposed on a side of the chip assembly 150 in the first direction D1 and is electrically connected with the chip assembly 150. The circuit board 300 is disposed on a side of the package substrate 200 away from the chip assembly 150 in the first direction D1, and the package substrate 200 and the circuit board 300 are configured to be soldered to each other to be electrically connected, for example, configured to be connected to each other through the conductive connectors 210.

[0041] In some embodiments, the package substrate 200 includes the first body layer 201 and a first pad group PG1 disposed on a side of the first body layer 201 away from the chip assembly 150 and including a plurality of first pads 202. For example, the plurality of first pads 202 can be disposed side by side at intervals in a direction parallel to a main surface of the package substrate 200, for example, can be arranged in an array.

[0042] In some embodiments, the circuit board 300 includes the second body layer 301 and a second pad group PG2 disposed on a side of the second body layer 301 and including a plurality of second pads 302. For example, the plurality of second pads 302 can be disposed side by side at intervals in a direction parallel to a main surface of the circuit board 300, for example, can be arranged in an array.

[0043] In some embodiments, the package substrate 200 and the circuit board 300 employ different body materials and have different coefficients of thermal expansion. For example, a first coefficient of thermal expansion of the first body layer 201 and a second coefficient of thermal expansion of the second body layer 301 are different from each other, and the first coefficient of thermal expansion and the second coefficient of thermal expansion have a first ratio.

[0044] In some embodiments, adjacent first pads 202 of the plurality of first pads 202 of the package substrate 200 can be arranged at a first initial pad pitch, adjacent second pads 302 of the plurality of second pads 302 of the circuit board 300 can be arranged at a second initial pad pitch, the first initial pad pitch and the second initial pad pitch are different from each other, and the first initial pad pitch and the second initial pad pitch have a second ratio. In some embodiments, one of the first ratio and the second ratio is less than 1, and the other of the first ratio and the second ratio is greater than 1.

[0045] That is, when the first coefficient of thermal expansion is less than the second coefficient of thermal expansion (i.e., the first ratio is less than 1), then the first initial pad pitch is greater than the second initial pad pitch (i.e., the second ratio is greater than 1); when the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion (i.e., the first ratio is greater than 1), then the first initial pad pitch is less than the second initial pad pitch (i.e., the second ratio is less than 1).

[0046] The first initial pad pitch and the second initial pad pitch are respective pad pitches of the package substrate and the circuit board before soldering, e.g., respective pitches of the first pad group and the second pad group at the beginning of pad design, respectively.

[0047] In some embodiments, the first coefficient of thermal expansion of the first body layer is less than the second coefficient of thermal expansion of the second body layer, and the first initial pad pitch is greater than the second initial pad pitch.

[0048] In some embodiments, the first pad group has a first size, the first size being a center-to-center spacing between two end first pads of the plurality of first pads in a same row or a same column; the second pad group has a second size, the second size being a center-to-center spacing between two end second pads of the plurality of second pads in the same row or the same column; and the first size is greater than the second size.

[0049] In some embodiments, a ratio of the first coefficient of thermal expansion of the first body layer in the package substrate to the second coefficient of thermal expansion of the second body layer in the circuit board is greater than 0 and less than or equal to 0.67, and a ratio of the second size to the first size ranges from 99.8% to 99.99%.

[0050] The following is exemplarily described with the first ratio being less than 1 and the second ratio being greater than 1.

[0051] Reference is made to Figure 5A and Figure 6A In some embodiments, the first coefficient of thermal expansion of the first body layer 201 of the package substrate 200 is less than the second coefficient of thermal expansion of the second body layer 301 of the circuit board 300. There is a mismatch of coefficients of thermal expansion between the package substrate 200 and the circuit board 300, and different degrees of thermal deformation (e.g., thermal expansion) will occur under high temperature conditions (e.g., during soldering).

[0052] In some embodiments, when designing the pads of the package substrate and the pads of the circuit board, the pad design parameters of the second pad group of the circuit board are scaled with respect to the corresponding pad design parameters of the first pad group of the package substrate, so that the initial design difference between the pads of the package substrate and the pads of the circuit board can compensate for the pad shift caused by the different degrees of thermal deformation during the soldering process, and thus the pad center of the pad in the package substrate and the pad center of the corresponding pad in the circuit board can be substantially aligned after soldering. Here, the pad design parameters can include the overall size of the pad group, the pad pitch between adjacent pads, etc.

[0053] For example, after the first pad design parameters of the first pad group of the package substrate are known, the parameters can be scaled down proportionally to obtain the second pad design parameters, and the second pad group of the circuit board is set according to the second pad design parameters.

[0054] For example, before the package substrate 200 and the circuit board 300 are soldered, in the package substrate 200, the first initial pad pitch d1 is between adjacent first pads 202, and in the circuit board 300, the second initial pad pitch d2 is between adjacent second pads 302. In the case where the first thermal expansion coefficient is less than the second thermal expansion coefficient, the first initial pad pitch d1 of the package substrate 200 is set to be greater than the second initial pad pitch d2 of the circuit board 300. Here, the pad pitch refers to the distance between two adjacent pads in the same row or column in the arrayed plurality of pads in the row direction or column direction, i.e., the distance between the opposite edges of the two adjacent pads facing each other in the row direction or column direction.

[0055] In some embodiments, the first pad group PG1 has a first size S1, which can be the center distance between two end first pads in the same row or column in the plurality of first pads 202; the second pad group PG2 has a second size S2, which can be the center distance between two end second pads in the same row or column in the plurality of second pads 302, and the first size S1 is greater than the second size S2. It should be understood that in each pad group, the center distance between the two end pads in the row direction can be the same as or different from the center distance between the two end pads in the column direction, and the above-mentioned first size S1 and second size S2 are compared for the corresponding end pads in the two pad groups; for example, the center distance between the end first pads in the same row direction and the center distance between the end second pads in the same row direction are compared, or the center distance between the end first pads in the same column direction and the center distance between the end second pads in the same column direction are compared.

[0056] Reference Figure 4 , Figure 5A and Figure 6AIn some embodiments, a ratio of the first coefficient of thermal expansion of the first bulk layer 201 in the package substrate 200 to the second coefficient of thermal expansion of the second bulk layer 301 in the circuit board 300 is greater than 0 and less than or equal to 0.67, for example, the ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion can range from about 0.1 to 0.67, 0.1 to 0.25, or 0.25 to 0.67; for example, the first coefficient of thermal expansion of the first bulk layer 201 can range from about 1.5 ppm / °C to 6 ppm / °C or 0.5 ppm / °C to 8 ppm / °C, and the second coefficient of thermal expansion of the second bulk layer 301 can range from about 9 ppm / °C to 13 ppm / °C. In some embodiments, a ratio of the second dimension S2 to the first dimension S1 can range from about 99.8% to 99.99%. In some embodiments, the smaller the ratio of the coefficients of thermal expansion of the package substrate 200 and the circuit board 300 (i.e., the greater the difference in thermal expansion between the two), the greater the scaling ratio of the second dimension S2 of the second pad group PG2 relative to the first dimension S1 of the first pad group PG1 (i.e., the greater the difference in size between the two relative to the first dimension S1).

[0057] In some embodiments, the plurality of first pads 202 of the first pad group PG1 and the plurality of second pads 302 of the second pad group PG2 are arranged one-to-one corresponding to each other. For example, the number of the plurality of first pads 202 and the number of the plurality of second pads 302 are the same. The plurality of first pads 202 are arranged at equal intervals, i.e., every two adjacent first pads 202 in the row direction or the column direction are arranged at the same first pad interval. The plurality of second pads 302 are arranged at equal intervals, i.e., every two adjacent second pads 302 in the row direction or the column direction are arranged at the same second pad interval.

[0058] In some embodiments, the first pads 202 and the second pads 302 comprise the same conductive material, for example, can each comprise a metal material such as titanium, copper, etc. For example, the plurality of first pads 202 and the plurality of second pads 302 can each have the same pad size. Here, the pad size refers to the width, diameter, area, etc. of the pad itself. For example, from a plan view, the first pads 202 and the second pads 302 can each be circular and have substantially the same diameter; from a cross-sectional view, the first pads 202 and the second pads 302 can each be square (square or rectangular) and have substantially the same width in a direction parallel to the main surface of the circuit board 300.

[0059] In some embodiments, when designing the first pad group and the second pad group, for example, scaling the relevant parameters of the second pad group based on the design parameters of the first pad group, the pad size of the pads themselves can not be changed, but the pad pitch and the overall size of the pad group can be changed; for example, based on the first size of the first pad group, the first size can be reduced by a proper ratio to obtain the second size of the second pad group, wherein the pad pitch is reduced by the same ratio, so that the plurality of second pads of the scaled second pad group are still arranged at equal intervals, and the overall size of the second pad group is reduced.

[0060] In some embodiments, the plurality of first pads and the plurality of second pads form a plurality of pad connection pairs, and each pad connection pair includes a first pad and a second pad configured to be electrically connected to each other, wherein the first pad and the second pad of at least some of the plurality of pad connection pairs are offset in a second direction parallel to the main surface of the circuit board.

[0061] In some embodiments, the plurality of pad connection pairs includes a reference pad connection pair and one or more offset pad connection pairs; the pad center of the first pad and the pad center of the second pad in the reference pad connection pair are aligned with each other in the first direction, and the pad center of the first pad and the pad center of the second pad of each offset pad connection pair are offset in the second direction.

[0062] In some embodiments, in each offset pad connection pair, the pad center of the second pad is closer to the pad center of the reference pad connection pair than the pad center of the first pad in the second direction.

[0063] In some embodiments, the plurality of pad connection pairs includes a first offset pad connection pair and a second offset pad connection pair, the second offset pad connection pair is farther away from the reference pad connection pair than the first offset pad connection pair, and a first center offset distance between the first pad and the second pad in the first offset pad connection pair in the second direction is less than a second center offset distance between the first pad and the second pad in the second offset pad connection pair in the second direction.

[0064] In some embodiments, the overlapping area of the first pad and the second pad in the first offset pad connection pair in the first direction is greater than the overlapping area of the first pad and the second pad in the second offset pad connection pair in the first direction.

[0065] Continuing to refer to Figure 5A and Figure 6AIn some embodiments, the plurality of first pads 202 and the plurality of second pads 302 form a plurality of pad connection pairs, and each pad connection pair includes a first pad 202 and a second pad 302 configured to be electrically connected to each other. As shown in FIG. 1, in some embodiments, the first pad 202 and the second pad 302 in each pad connection pair overlap with each other in a first direction D1 perpendicular to the package substrate 200 or the circuit board 300. In other embodiments, in one or more pad connection pairs, the first pad 202 and the second pad 302 can also not overlap in the first direction D1. Figure 5A and Figure 6A As shown in FIG. 1, in some embodiments, the first pad 202 and the second pad 302 in each pad connection pair overlap with each other in a first direction D1 perpendicular to the package substrate 200 or the circuit board 300. In other embodiments, in one or more pad connection pairs, the first pad 202 and the second pad 302 can also not overlap in the first direction D1.

[0066] In some embodiments, the pad center of the first pad 202 and the pad center of the second pad 302 in at least some of the plurality of pad connection pairs are not aligned in the first direction D1, but are offset in a second direction D2 parallel to the main surface of the circuit board 300. The first direction D1 and the second direction D2 intersect with each other, for example, are substantially perpendicular to each other. In this context, the second direction D2 refers to a direction parallel to the main surface of the package substrate 200 or parallel to the main surface of the circuit board 300, and can include a plurality of horizontal directions in the drawings, for example, include each direction parallel to the paper in FIG. 1. Figure 5A In some embodiments, the pad center of the first pad 202 and the pad center of the second pad 302 in at least some of the plurality of pad connection pairs are not aligned in the first direction D1, but are offset in a second direction D2 parallel to the main surface of the circuit board 300. The first direction D1 and the second direction D2 intersect with each other, for example, are substantially perpendicular to each other. In this context, the second direction D2 refers to a direction parallel to the main surface of the package substrate 200 or parallel to the main surface of the circuit board 300, and can include a plurality of horizontal directions in the drawings, for example, include each direction parallel to the paper in FIG. 1.

[0067] In some embodiments, the plurality of pad connection pairs can also include pad connection pairs with aligned pad centers. For example, when designing the pads, after the design parameters of a first pad group are known, one of the first pads in the first pad group (for example, a first pad in the center position in the plurality of first pads) can be taken as a reference pad, and then the size of the pad group is scaled by the reference pad as the center, thereby obtaining the relevant design parameters of a second pad group. When the package substrate and the circuit board are aligned for soldering preparation, the reference pads of the first pad group and the second pad group can be aligned with each other.

[0068] Referring to FIG. 1, Figure 5A and Figure 6A In some embodiments, the plurality of pad connection pairs includes a reference pad connection pair G1 and one or more offset pad connection pairs G2. The pad center of the first pad 202 and the pad center of the second pad 302 in the reference pad connection pair G1 are aligned with each other in the first direction D1, and the pad center of the first pad 202 and the pad center of the second pad 302 in each offset pad connection pair G2 are not aligned in the first direction D1, but are offset in the second direction D2, and have a center offset distance. In this context, the pad center refers to the geometric center of the pad, for example, in the case of a circular planar shape of the pad, the pad center is the center of the circle from the plan view; in the case of a square planar shape of the pad, the pad center is the intersection of the two diagonals of the square from the cross-sectional view.

[0069] In some embodiments, in each offset pad connection pair G2, the pad center of the second pad 302 is closer to the pad center of the reference pad connection pair G1 (i.e., the pad center of the first pad 202 or the second pad 302 in the reference pad connection pair G1) in a direction parallel to the main surface of the circuit board 300 than the pad center of the first pad 202. That is, in each offset pad connection pair G2, the distance between the pad center of the first pad 202 and the pad center of the reference pad connection pair G1 in the second direction D2 is greater than the distance between the pad center of the second pad 302 and the pad center of the reference pad connection pair G1 in the second direction D2.

[0070] In some embodiments, in the plurality of offset pad connection pairs, the greater the distance between the center of the first pad 202 and the second pad 302 of an offset pad connection pair G2 farther away from the reference pad connection pair G1. In some embodiments, in the plurality of offset pad connection pairs G2, the smaller the overlapping area between the first pad 202 and the second pad 302 in the first direction D1 in an offset pad connection pair G2 farther away from the reference pad connection pair G1.

[0071] For example, the plurality of pad connection pairs includes a first offset pad connection pair G21 and a second offset pad connection pair G22, the second offset pad connection pair G22 being farther away from the reference pad connection pair G1 than the first offset pad connection pair G21. In some embodiments, the reference pad connection pair G1, the first offset pad connection pair G21, and the second offset pad connection pair G22 can be arranged along a row direction of the pad arrangement or along a column direction, or can also be arranged along other horizontal directions intersecting the row direction and the column direction. The pad connection pairs are illustrated as being arranged along the column direction in the figures.

[0072] Continuing to refer to Figure 5A and Figure 6A In some embodiments, the first pad 202 and the second pad 302 in the reference pad connection pair G1 can be referred to as a first reference pad 202a and a second reference pad 302a, respectively; the first pad 202 and the second pad 302 in the first offset pad connection pair G21 can be referred to as a first offset pad 202b and a second offset pad 302b, respectively; and the first pad 202 and the second pad 302 in the second offset pad connection pair G22 can be referred to as a third offset pad 202c and a fourth offset pad 302c, respectively.

[0073] As Figure 6AAs shown, in the reference pad connection pair G1, the pad center of the first reference pad 202a and the pad center of the second reference pad 302a are aligned in the first direction D1. For example, in the case that the first reference pad 202a and the second reference pad 302a have the same pad size, the first reference pad 202a and the second reference pad 302a can be completely overlapped in the first direction, and have sidewalls that are substantially aligned in the first direction D1. That is, the normal projections of both on the major surface of the circuit board 300 can substantially coincide.

[0074] In the first offset pad connection pair G21, the pad center of the first offset pad 202b and the pad center of the second offset pad 302b are offset in the second direction D2, for example, by an offset distance dcl. The pad center of the second offset pad 302b is closer to the pad center of the reference pad connection pair G1 than the pad center of the first offset pad 202b. For example, the first offset pad connection pair G21 is the pad connection pair closest to the reference pad connection pair G1 among the plurality of offset pad connection pairs G2, and the first offset distance dcl can be substantially equal to the difference between the first initial pad pitch dl and the second initial pad pitch d2. In some embodiments, the first offset pad 202b and the second offset pad 302b can be partially overlapped in the first direction D1.

[0075] In the second offset pad connection pair G22, the pad center of the third offset pad 202c and the pad center of the fourth offset pad 302c are offset in the second direction D2, for example, by a second offset distance dc2. The pad center of the fourth offset pad 302c is closer to the pad center of the reference pad connection pair G1 than the pad center of the third offset pad 202c. For example, the second offset pad connection pair G22 is a pad connection pair that is spaced apart from the reference pad connection pair G1 by other pad connection pairs, and the second offset distance dc2 is greater than the difference between the first initial pad pitch dl and the second initial pad pitch d2. As shown, the second offset distance dc2 is greater than the first offset distance dcl. For example, the second offset pad connection pair G22 is spaced apart from the reference pad connection pair G1 by one offset pad connection pair in the column direction, and the second offset distance dc2 can be substantially equal to twice the difference between the first initial pad pitch dl and the second initial pad pitch d2. In some embodiments, the third offset pad 202c and the fourth offset pad 302c can also be partially overlapped in the first direction D1. Figure 6A

[0076] ​In some embodiments, the overlapping area of the third offset pad 202c and the fourth offset pad 302c in the first direction D1 is less than the overlapping area of the first offset pad 202b and the second offset pad 302b in the first direction D1. In this context, the overlapping of two members in a direction means that the projections of the two members on a reference plane perpendicular to the direction overlap, and the overlapping area of two members in a direction refers to the area of the overlapping part of the projections of the two members on a reference plane perpendicular to the direction.

[0077] In some embodiments, the packaging assembly includes a plurality of conductive connectors respectively configured to connect the plurality of first pads of the packaging substrate and the plurality of second pads of the circuit board to solder the packaging substrate and the circuit board.

[0078] In some embodiments, the packaging substrate is configured to have a first pad pitch between the adjacent first pads after being soldered with the circuit board, the circuit board is configured to have a second pad pitch between the adjacent second pads after being soldered with the packaging substrate, and the first pad pitch is equal to the second pad pitch.

[0079] In some embodiments, the first pad pitch is greater than the first initial pad pitch, the second pad pitch is greater than the second initial pad pitch, and the difference between the second pad pitch and the second initial pad pitch is greater than the difference between the first pad pitch and the first initial pad pitch.

[0080] In some embodiments, the packaging substrate is configured to have a plurality of first pad centers of the plurality of first pads respectively aligned with a plurality of second pad centers of the plurality of second pads of the circuit board in the first direction after being soldered with the circuit board.

[0081] In some embodiments, the plurality of conductive connectors each connect a respective first pad and a second pad, and are symmetric with respect to a pad center line of the first pad and the second pad, the pad center line extending through a first pad center of the first pad and a second pad center of the second pad in the first direction.

[0082] Reference Figure 4 In some embodiments, the packaging assembly 500 includes a plurality of conductive connectors 210 respectively configured to connect the plurality of first pads 202 of the packaging substrate 200 and the plurality of second pads 302 of the circuit board 300 to solder the packaging substrate 200 and the circuit board 300. For example, the conductive connectors 210 can be or include solder balls, such as a ball grid array (BGA).

[0083] In some embodiments, during the soldering of the package substrate 200 and the circuit board 300 by the conductive connectors 210, the package substrate 200 and the circuit board 300 can be subject to thermal deformation, such as thermal expansion, due to the high temperature during the soldering process. Such thermal deformation can cause the pad pitch and overall size of the pad groups on the package substrate 200 and the circuit board 300 to change.

[0084] Due to the difference in the thermal expansion coefficients of the package substrate 200 and the circuit board 300, the package substrate 200 and the circuit board 300 can expand to different extents. For example, the first thermal expansion coefficient of the package substrate 200 is less than the second thermal expansion coefficient of the circuit board 300, and thus the package substrate 200 can expand to a smaller extent than the circuit board 300 under the same temperature condition. In some embodiments, the difference in the thermal expansion coefficients of the package substrate 200 and the circuit board 300 is mainly due to the difference in the thermal expansion coefficients of the bulk materials of the bulk layers of the package substrate 200 and the circuit board 300.

[0085] In the design of the pads, the relevant pad parameters of the second pad group PG2 in the circuit board 300 are designed to be scaled with respect to the corresponding pad parameters of the first pad group PG1 in the package substrate 200, and thus the scaling design can compensate for the difference in the thermal expansion of the circuit board 300 and the package substrate 200 (i.e., the circuit board 300 expands to a greater extent than the package substrate 200) during the high-temperature soldering process, thereby facilitating the reduction or avoidance of the shift of the first pads 202 and the second pads 302 after the soldering is completed, such as the alignment of the corresponding pads of the first pad group PG1 and the second pad group PG2 with each other in the first direction D1 after the soldering.

[0086] Referring to Figure 5A , Figure 5B and Figure 6A and Figure 6B In some embodiments, after the soldering of the package substrate 200 and the circuit board 300 by the conductive connectors 210, the first pad group PG1 in the package substrate 200 can still have the first pads 202 arranged at the first pad pitch d3 between adjacent first pads 202. In some embodiments, the first pad pitch d3 is greater than the first initial pad pitch d1, i.e., the pad pitch between adjacent first pads 202 increases from the first initial pad pitch d1 to the first pad pitch d3 due to the thermal expansion of the package substrate 200 after the soldering.

[0087] In the second pad group PG2 of the circuit board 300, the second pad pitch d4 between adjacent second pads 302 can be equal. The second pad pitch d4 is greater than the second initial pad pitch d2, i.e., after soldering, the pad pitch between adjacent second pads 302 increases from the second initial pad pitch d2 to the second pad pitch d4 due to thermal expansion of the circuit board 300. In some embodiments, the first pad pitch d3 can be substantially equal to the second pad pitch d4 after soldering.

[0088] In some embodiments, since the thermal expansion of the circuit board 300 is greater than that of the package substrate 200, the increase in pad pitch on the circuit board 300 is greater than that on the package substrate 200, i.e., the difference between the second pad pitch d4 and the second initial pad pitch d2 (or the second increment) is greater than the difference between the first pad pitch d3 and the first initial pad pitch d1 (or the first increment). For example, the difference between the first initial pad pitch d1 and the second initial pad pitch d2 can be substantially equal to the difference between the second increment and the first increment, so that the difference in initial pad design can just compensate for the different increments in pad pitch due to different thermal expansions of the package substrate 200 and the circuit board 300 during high-temperature processes such as soldering, so that the first pad pitch d3 of the first pad group PG1 can be substantially equal to the second pad pitch d4 of the second pad group PG2 after soldering.

[0089] Reference Figure 5A and Figure 5B In some embodiments, the third dimension S3 of the first pad group PG1 and the fourth dimension S4 of the second pad group PG2 can be substantially the same after soldering. The third dimension S3 can be the center-to-center distance between two end first pads in the same row or column of the first pad group PG1; the fourth dimension S4 can be the center-to-center distance between two end second pads in the same row or column of the second pad group PG2. The third dimension S3 of the first pad group PG1 after soldering can be greater than the first dimension S1 before soldering, and the fourth dimension S4 of the second pad group PG2 after soldering can be greater than the second dimension S2 before soldering.

[0090] In some embodiments, the package substrate is configured such that, after soldering with the circuit board, the first pad centers of the first pads and the second pad centers of the second pads are aligned in the first direction.

[0091] In some embodiments, each of the plurality of conductive connections connects a respective first pad and a respective second pad, and is symmetric with respect to a pad centerline of the first pad and the second pad, the pad centerline extending through the first pad center of the first pad and the second pad center of the second pad in the first direction.

[0092] refer to Figure 5B and Figure 6B In some embodiments, after the package substrate 200 is soldered to the circuit board 300, the centers of the plurality of first pads 202 are substantially aligned with the centers of the plurality of second pads 302 in a first direction D1. In some embodiments, the first pads 202 and the second pads 302 also have substantially the same pad size (e.g., width, diameter, area, etc.) after soldering. The pad size after soldering may be the same or different from the pad size before soldering. Since the first pads 202 and the second pads 302 comprise substantially the same pad material, even if the first pads 202 and the second pads 302 undergo thermal expansion during soldering, the degree of thermal expansion of the two can be substantially the same. If the first pads 202 and the second pads 302 have the same pad size before soldering, they will also have substantially the same pad size after soldering.

[0093] For example, after soldering, the first pad 202 and the second pad 302 in each pad connection pair are electrically connected to each other via a conductive connector 210. The conductive connector 210 is located between the corresponding first pad 202 and the second pad 302 in a first direction D1 to provide an electrical connection between the two pads. In some embodiments, the centers of the first pad 202 and the second pad 302 in each pad connection pair are substantially aligned in the first direction D1. The conductive connector 210 may be substantially symmetrical with respect to the center line of the corresponding first pad 202 and the second pad 302, which extends in the first direction D1 through the center of the first pad 202 and the center of the second pad 302. In this way, the conductive connector can be prevented from tilting due to the offset of the center of the first pad 202 and the second pad 302, thereby avoiding the conductive connector 210 from being subjected to additional large stress due to tilting, and thus avoiding or reducing the possibility of problems such as cracking of the conductive connector 210, thereby improving the reliability of the package assembly 500.

[0094] like Figure 6B As shown, after soldering via conductive connector 210, in the reference pad connection pair G1, the center of the first reference pad 202a and the center of the second reference pad 302a are approximately aligned in the first direction D1. The two reference pads have approximately the same pad size and overlap in the first direction D1, for example, completely overlap, and have sidewalls that are approximately aligned in the first direction. The conductive connector 210 located between the first reference pad 202a and the second reference pad 302a is approximately symmetrical with respect to the first pad centerline CL1, which is a line extending in the first direction D1 through the center of the first reference pad 202a and the center of the second reference pad 302a.

[0095] In the first offset pad connection pair G21, the pad center of the first offset pad 202b is substantially aligned with the pad center of the second offset pad 302b in the first direction D1, the two offset pads have substantially the same pad size (e.g., width) and overlap in the first direction D1, for example, completely overlap, and have substantially aligned sidewalls in the first direction D1. The conductive connection 210 located between the first offset pad 202b and the second offset pad 302b is substantially symmetrical with respect to the second pad center line CL2, which is a line extending through the pad center of the first offset pad 202b and the pad center of the second offset pad 302b in the first direction D1.

[0096] In the second offset pad connection pair G22, the pad center of the third offset pad 202c is substantially aligned with the pad center of the fourth offset pad 302c in the first direction D1, the two offset pads have substantially the same pad size (e.g., width) and overlap in the first direction D1, for example, completely overlap, and have substantially aligned sidewalls in the first direction D1. The conductive connection 210 located between the third offset pad 202c and the fourth offset pad 302c is substantially symmetrical with respect to the third pad center line CL3, which is a line extending through the pad center of the third offset pad 202c and the pad center of the fourth offset pad 302c in the first direction D1.

[0097] Reference Figure 5A , 5B and Figure 6A , Figure 6B In some embodiments, the center positions of the package substrate and the circuit board can remain substantially unchanged when thermal expansion occurs, so when designing the pads, the pads substantially located at the center positions in each pad group of the package substrate and the circuit board can be used as reference pads, and the reference pads have aligned pad centers in the initial design. Under high-temperature conditions such as welding, the pad center positions of the two reference pads can remain substantially unchanged, or the relative positional relationship of the pad centers of the two reference pads remains unchanged, so that the pad center of the first reference pad is substantially aligned with the pad center of the second reference pad before and after welding in the first direction. Other pads can be arranged according to the corresponding pad parameters with the reference pads as reference points, so that the pad centers of the corresponding pads in the first pad group and the second pad group can be substantially aligned with each other after welding.

[0098] The embodiment of the present disclosure provides a packaging assembly, which comprises a chip assembly; a packaging substrate arranged on one side of the chip assembly in a first direction and electrically connected with the chip assembly, wherein the packaging substrate comprises a first main body layer and a first pad located on a side of the first main body layer away from the chip assembly; a circuit board arranged on a side of the packaging substrate away from the chip assembly in the first direction and comprising a second main body layer and a second pad located on a side of the second main body layer close to the packaging substrate; and a conductive connecting piece located between the first pad of the packaging substrate and the second pad of the circuit board to solder the packaging substrate and the circuit board, wherein the packaging substrate and the circuit board have different thermal expansion coefficients, and a first pad center of the first pad and a second pad center of the second pad are configured to be offset in a second direction parallel to a main surface of the circuit board before the conductive connecting piece is soldered and aligned in the first direction perpendicular to the main surface of the circuit board after the conductive connecting piece is soldered.

[0099] In the embodiment of the present disclosure, when the packaging substrate and the circuit board have different thermal expansion coefficients, the first pad center and the second pad center are arranged to be offset from each other before soldering, so that the offset can compensate for the expansion difference between the packaging substrate and the circuit board caused by different thermal expansion coefficients during soldering, and then the first pad center and the second pad center can be approximately aligned with each other after soldering. Since the first pad center and the second pad center are approximately aligned after the conductive connecting piece is soldered, the conductive connecting piece can be prevented from tilting due to the offset of the pad center, and the conductive connecting piece can be prevented from suffering greater additional stress, thereby improving the device reliability of the packaging assembly.

[0100] In some embodiments, the thermal expansion coefficient of the packaging substrate is less than the second thermal expansion coefficient of the circuit board; and the first pad has a first offset amount in the second direction during soldering, the second pad has a second offset amount in the second direction during soldering, and the first offset amount is less than the second offset amount.

[0101] In some embodiments, the offset distance of the first pad center and the second pad center in the second direction before the conductive connecting piece is soldered is equal to the difference between the second offset amount and the first offset amount.

[0102] Reference Figure 5A , Figure 5B and Figure 6A , Figure 6BFor example, for the first offset pad connection pair G21, the first offset amount of the pad center of the first offset pad 202b in the second direction during the soldering process (i.e., approximately equal to the difference between the first pad pitch d3 and the first initial pad pitch d1) is less than the second offset amount of the pad center of the second offset pad 302b in the second direction during the soldering process (i.e., approximately equal to the difference between the second pad pitch d4 and the second initial pad pitch d2). The offset distance of the pad center of the first offset pad 202b and the pad center of the second offset pad 302b in the second direction D2 before soldering (i.e., approximately equal to the difference between the first initial pad pitch d1 and the second initial pad pitch d2) is approximately equal to the difference between the second offset amount and the first offset amount, so that after soldering, the pad center of the first offset pad 202b and the pad center of the second offset pad 302b can be approximately aligned in the first direction D1.

[0103] Referring back to Figure 4 In some embodiments, the package substrate 200 and the circuit board 300 can each include a core layer, build-up layers disposed on opposite sides of the core layer, and a solder mask on the build-up layers away from the core layer. A plurality of conductive features, such as conductive vias and conductive lines, can be embedded in the core layer and the build-up layers. The core layer and the build-up layers can include organic dielectric materials. The conductive features can include metal materials such as copper, which can include copper foils.

[0104] In some embodiments, the core layer material of the package substrate 200 is different from the core layer material of the circuit board 300. For example, the core layer material of the package substrate 200 can be or include a suitable type of glass cloth, adhesive material, etc. The core layer material of the circuit board 300 can be or include a suitable type of glass cloth, adhesive material, etc. The build-up layers of the package substrate 200 and the build-up layers of the circuit board 300 can each include a suitable type of combination of glass cloth and adhesive material or a suitable type of combination of adhesive material and inorganic filler (e.g., spherical silica), etc. The above-mentioned materials of the package substrate 200 and the circuit board 300 are merely illustrative, and the present disclosure is not limited thereto. It should be understood that although the core materials of the package substrate 200 and the circuit board 300 are similar, such as both using adhesive material and glass cloth, etc., the specific materials used by the two can be different, or the specifications of the corresponding materials can be different, thus having different coefficients of thermal expansion. In some embodiments, the difference in the coefficients of thermal expansion of the package substrate 200 and the circuit board 300 is mainly due to the difference in the coefficients of thermal expansion between the core materials of the two.

[0105] In some embodiments, the first main body layer 201 of the package substrate 200 can be or include a core layer of the package substrate 200, or can also include an insulating structure (e.g., an organic insulating structure) integrally formed by the core layer and a build-up layer of the package substrate 200. The second main body layer 301 of the circuit board 300 can be or include a core layer of the circuit board 300, or can also include an insulating structure (e.g., an organic insulating structure) integrally formed by the core layer and a build-up layer of the circuit board 300.

[0106] With reference to Figure 4 , Figure 6A and Figure 6B , in some embodiments, the package substrate 200 includes a first solder resist layer 205 disposed on a side of the first main body layer 201 distal to the chip component 150 and exposing at least part of the first pads 202. In some embodiments, the first solder resist layer 205 covers edge portions of the first pads 202 and has a first solder resist opening to expose part of the surface of the first pads 202 for electrical connection with the conductive connectors 210; the width of the first solder resist opening can be smaller than the width of the first pads 202. In some embodiments, the package substrate 200 also has conductive pads and a solder resist layer (not shown) disposed on a side proximal to the chip component 150, the solder resist layer exposing at least part of the conductive pads, and the conductive pads configured to be electrically connected with the chip component 150, e.g., through the conductive bumps 106. For example, the conductive bumps 106 can be or include Controlled collapsed chip connection (C4) bumps. In some embodiments, the package assembly 500 can further include an underfill layer 107 filling the space between the chip component 150 and the package substrate 200 and surrounding the conductive bumps 106.

[0107] In some embodiments, the circuit board 300 can be a printed circuit board (PCB) and include a second solder resist layer 305 disposed on a side of the second main body layer 301 and exposing at least part of the surface of the second pads 302. In some embodiments, the second solder resist layer 305 has a second solder resist opening, which can be larger than the width of the second pads 302 to fully expose the surface of the second pads 302. In some embodiments, disposing the second solder resist opening to be larger than the width of the second pads 302 can facilitate the connection of the second pads 302 with the conductive connectors 210. In some embodiments, the circuit board 300 can also have a solder resist layer disposed on a side of the second main body layer 301 distal to the second pad group PG2.

[0108] In some embodiments, the chip assembly 150 can be or include one or more chips, or can be a chip package including one or more chips, and the present disclosure does not limit the type of chips or the type of chip package of the chip assembly 150.

[0109] For example, referring to Figure 4 In some embodiments, the chip assembly 150 can be a chip package including a plurality of chips 100. The plurality of chips in the chip assembly 150 can include chips of the same type or different types, and the number and type of chips can be selected according to product requirements; for example, the plurality of chips of the chip assembly 150 can include one or more of a system on chip (SoC), a digital signal processor (DSP) chip, a graphic processing unit (GPU), an application specific integrated circuit (ASIC) chip, a high bandwidth memory chip (HBM), a Central Processing Unit (CPU), a Tensor Processing Unit (TPU), a Neural network Processing Unit (NPU), a Deep learning Processing Unit (DPU), an Accelerated Processing Unit (APU), a General-Purpose computing on Graphics Processing Unit (GPGPU), a chiplet, etc. In some examples, the two chips shown in the figure are a logic chip such as an SoC and a memory chip such as an HBM respectively, but the present disclosure is not limited thereto.

[0110] In some embodiments, the chip assembly 150 further includes an interposer 105 and an encapsulation layer 110, the interposer 105 is located between the chips 100 and the package substrate 200 to provide interconnection between the plurality of chips 100 and electrical connection between the chips 100 and the package substrate 200. The interposer 105 can be a silicon-based interposer, for example, including a semiconductor substrate, substrate vias, and interconnection structures, etc. In other embodiments, the interposer 105 can also be replaced by a rewiring structure, or a rewiring structure embedded with a bridge chip, etc.

[0111] In some embodiments, the plurality of chips 100 can be electrically connected to the interposer 105 through a plurality of micro bumps. A bottom fill layer can be provided between the plurality of chips 100 and the interposer 105 to surround and protect the plurality of micro bumps.

[0112] An encapsulation layer 110 is provided on a side of the interposer 105 distal to the package substrate 200 to encapsulate the plurality of chips 100. The encapsulation layer 110 can comprise a molding compound, such as an epoxy molding compound (EMC).

[0113] In some embodiments, other electronic devices can also be provided on the package substrate 200, such as additional devices 220. For example, the additional devices 220 can comprise passive devices such as capacitors. The additional devices 220 can be provided on a side of the package substrate 200 proximal to the chip assembly 150 and / or on a side of the package substrate 200 distal to the chip assembly 150. In some embodiments, on the side of the package substrate 200 distal to the chip assembly 150, in addition to the first set of pads PG1 for electrical connection to the circuit board 300, other pads can also be provided for electrical connection to other electronic devices (e.g., the additional devices 220). In some embodiments, in addition to the chip assembly 150 and the package substrate 200, other electronic devices (not shown) can also be provided on the circuit board 300, and on a side of the circuit board 300 proximal to the package substrate 200, in addition to the second set of pads PG2, other pads can also be provided for electrical connection to the other electronic devices.

[0114] In some embodiments, a reinforcement structure 230 is provided on the package substrate 200, and the reinforcement structure 230 and the chip assembly 150 are provided on the same side of the package substrate 200. For example, the reinforcement structure 230 can be provided on an edge of the package substrate 200 and can be attached to the package substrate 200 through an adhesive layer. The chip assembly 150 can be located in an area surrounded by the reinforcement structure 230 in a direction parallel to a major surface of the package substrate 200. The reinforcement structure 230 can be beneficial in controlling and reducing warpage of the package substrate 200 and the overall package structure. In some embodiments, as shown in FIG. 2B, the reinforcement structure 230 can be a reinforcement ring; in alternative embodiments, the reinforcement structure 230 can also take the form of a reinforcement cover, i.e., can also comprise a cover portion located on a side of the chip assembly 150 distal to the interposer 105. Figure 4

[0115] ​In the packaging assembly of the embodiments of the present disclosure, in the case that the packaging substrate and the circuit board have different thermal expansion coefficients, the corresponding pad groups in the packaging substrate and the circuit board are designed to be offset, that is, the pad group of the one with larger thermal expansion coefficient is set to be scaled, so as to compensate for the larger offset of the one with larger thermal expansion coefficient due to the larger thermal expansion under high temperature conditions such as welding, and then the pad centers of the corresponding pads in the packaging substrate and the circuit board after welding can be substantially aligned in the direction perpendicular to the main surface of the circuit board, avoiding or improving the inclination of the conductive connecting piece between the two due to the offset of the pad center, thereby avoiding or reducing the additional stress suffered by the conductive connecting piece due to the inclination, thus avoiding or reducing the cracking of the conductive connecting piece due to the larger stress, thereby improving the reliability of the packaging assembly.

[0116] The following points need to be explained:

[0117] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can be referred to the usual design.

[0118] (2) The features in the same and different embodiments of the present disclosure can be combined with each other without conflict.

[0119] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A package assembly, comprising: The package assembly comprises: a chip component; a package substrate disposed on a side of the chip component in a first direction and electrically connected with the chip component, wherein the package substrate comprises a first body layer having a first coefficient of thermal expansion and a first pad group having a plurality of first pads, the first pad group is located on a side of the first body layer away from the chip component, and a first initial pad pitch is provided between adjacent first pads; and a circuit board disposed on a side of the package substrate away from the chip component in the first direction and comprising a second body layer having a second coefficient of thermal expansion and a second pad group having a plurality of second pads, the second pad group is located on a side of the second body layer and is configured to be electrically connected with the first pad group, and a second initial pad pitch is provided between adjacent second pads; wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion have a first ratio, and the first initial pad pitch and the second initial pad pitch have a second ratio, wherein one of the first ratio and the second ratio is less than 1, and the other of the first ratio and the second ratio is greater than 1.

2. The package assembly of claim 1, wherein: the first coefficient of thermal expansion of the first body layer is less than the second coefficient of thermal expansion of the second body layer, and the first initial pad pitch is greater than the second initial pad pitch.

3. The package assembly of claim 2, wherein, the first pad group has a first dimension, the first dimension being a center distance between two end first pads in the same row or the same column among the plurality of first pads; the second pad group has a second dimension, the second dimension being a center distance between two end second pads in the same row or the same column among the plurality of second pads; and the first dimension is greater than the second dimension.

4. The package assembly of claim 3, wherein, a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than 0 and less than or equal to 0.67, and a ratio of the second dimension to the first dimension ranges from 99.8% to 99.99%.

5. The package assembly of claim 1, wherein, a number of the plurality of first pads is the same as a number of the plurality of second pads.

6. The package assembly of claim 1, wherein, the plurality of first pads are arranged at equal intervals, and the plurality of second pads are arranged at equal intervals.

7. The package assembly of claim 1, wherein, the plurality of first pads and the plurality of second pads each have a same pad size.

8. The package assembly of any one of claims 1-7, wherein: the plurality of first pads and the plurality of second pads form a plurality of pad connection pairs respectively, and each pad connection pair comprises a first pad and a second pad configured to be electrically connected with each other, wherein a pad center of the first pad and a pad center of the second pad of at least part of the plurality of pad connection pairs are offset in a second direction parallel to a main surface of the circuit board.

9. The package assembly of claim 8, wherein: the plurality of pad connection pairs comprises a reference pad connection pair and one or more offset pad connection pairs. The pad center of the first pad and the pad center of the second pad in the reference pad connection pair are aligned with each other in the first direction, and the pad center of the first pad and the pad center of the second pad in each offset pad connection pair are offset in the second direction.

10. The package assembly of claim 9, wherein, In each offset pad connection pair, the pad center of the second pad is closer to the pad centers of the reference pad connection pair in the second direction than the pad center of the first pad.

11. The package assembly of claim 9, wherein, The plurality of pad connection pairs includes a first offset pad connection pair and a second offset pad connection pair, the second offset pad connection pair is farther away from the reference pad connection pair than the first offset pad connection pair, and a first center offset distance of the first pad and the second pad in the first offset pad connection pair in the second direction is less than a second center offset distance of the first pad and the second pad in the second offset pad connection pair in the second direction.

12. The package assembly of claim 11, wherein, An overlapping area of the first pad and the second pad in the first offset pad connection pair in the first direction is greater than an overlapping area of the first pad and the second pad in the second offset pad connection pair in the first direction.

13. The package assembly of any one of claims 1-7, wherein, Further comprising: A plurality of conductive connectors respectively configured to connect the plurality of first pads of the package substrate and the plurality of second pads of the circuit board to solder the package substrate and the circuit board.

14. The package assembly of claim 13, wherein, The package substrate is configured to have a first pad pitch between the adjacent first pads after being soldered with the circuit board, the circuit board is configured to have a second pad pitch between the adjacent second pads after being soldered with the package substrate, and the first pad pitch is equal to the second pad pitch.

15. The package assembly of claim 14, wherein, The first pad pitch is greater than the first initial pad pitch, the second pad pitch is greater than the second initial pad pitch, and a difference between the second pad pitch and the second initial pad pitch is greater than a difference between the first pad pitch and the first initial pad pitch.

16. The package assembly of claim 14, wherein, The package substrate is configured to have first pad centers of the plurality of first pads respectively aligned with second pad centers of the plurality of second pads of the circuit board in the first direction after being soldered with the circuit board.

17. The package assembly of claim 16, wherein, The plurality of conductive connectors are each connected to a corresponding first pad and a second pad, and are symmetrical with respect to a pad center line of the first pad and the second pad, the pad center line extends through a first pad center of the first pad and a second pad center of the second pad in the first direction.

18. A package assembly, comprising: Comprising: A chip assembly; A package substrate disposed on a side of the chip assembly in a first direction and electrically connected to the chip assembly, wherein the package substrate comprises a first body layer and a first pad, the first pad is located on a side of the first body layer away from the chip assembly; A circuit board disposed on a side of the package substrate away from the chip assembly in the first direction and comprising a second body layer and a second pad, the second pad is located on a side of the second body layer close to the package substrate; And A plurality of conductive connectors respectively configured to connect the plurality of first pads of the package substrate and the plurality of second pads of the circuit board to solder the package substrate and the circuit board. a conductive connector between the first pad of the package substrate and the second pad of the circuit board to solder the package substrate and the circuit board, wherein the package substrate and the circuit board have different coefficients of thermal expansion, and a first pad center of the first pad and a second pad center of the second pad are configured to be offset in a second direction parallel to a major surface of the circuit board before soldering of the conductive connector is complete and aligned in the first direction perpendicular to the major surface of the circuit board after soldering of the conductive connector is complete.

19. The package assembly of claim 18, wherein a coefficient of thermal expansion of the package substrate is less than a coefficient of thermal expansion of the circuit board; and the first pad is offset in the second direction by a first offset amount during soldering, the second pad is offset in the second direction by a second offset amount during soldering, and the first offset amount is less than the second offset amount.

20. The package assembly of claim 19, wherein the offset distance of the first pad center and the second pad center in the second direction before soldering of the conductive connector is complete is equal to a difference between the second offset amount and the first offset amount.

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