Chip input end logic level detection circuit
By using a self-powered design and a logic latch circuit, the problems of unstable voltage source and current consumption in the logic level detection circuit at the chip input end are solved, achieving logic level detection with low complexity and low power consumption.
Patent Information
- Application Number
- CN202423096525.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-16
AI Technical Summary
In the prior art, the logic level detection circuit at the chip input end is difficult to achieve a high-precision and stable voltage source when the input range is wide, which leads to increased design complexity and power consumption, and serious current consumption problems.
The self-powered design utilizes diodes and energy storage devices to maintain a high level at the power supply terminal of the input inverter when the input terminal is low. Combined with a logic latch circuit, the low-level signal is latched to ensure that the toggle point is independent of the chip power supply voltage and does not consume current when the chip enable terminal is powered on or off.
This achieves logic level judgment independent of chip power supply voltage, reducing design complexity and circuit cost, while avoiding current consumption when the chip enable state changes, thus improving energy efficiency.
Smart Images
Figure CN223729725U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic circuit field, concretely relates to a chip input end logic level detection circuit. BACKGROUND
[0002] The input pin of the chip needs to judge whether the input signal is a logic high level or a logic low level according to the height of the input voltage. The inverter can be used in the chip to make the logic judgment. But the flip point of the inverter is proportional to the supply voltage, in order to ensure that the flip point meets the design specification, a stable power supply must be provided. It is not easy to realize a high-precision stable voltage source for the chip with wide range input, which greatly increases the design difficulty of the chip. For example, the output of the internal LDO of the chip is generally stable 5V, but when the input voltage is lower than 5V, the output of the LDO will decrease with the input voltage. At this time, if the VCC generated by the internal LDO is still used to power the logic circuit, it cannot meet the voltage requirement of the logic circuit flip at low voltage. Therefore, an additional circuit is needed to generate a stable power supply.
[0003] The effect of the flip level independent of the power supply voltage can also be realized by building an analog circuit. Figure 1 It is a circuit diagram of an embodiment of the logic level detection circuit in the prior art. As shown in Figure 1 The flip point of this circuit is mainly determined by the threshold voltage of the MOS device and the size of the internal resistance, and is independent of the chip voltage VCC. But this circuit has the problem of current consumption, for example, when the enable signal IN is high, the chip voltage VCC will have a current consumption through the internal resistance, which obviously increases the power consumption of the chip for low power consumption applications. Utility model content
[0004] In view of the defects of the prior art, the utility model discloses a chip input end logic level detection circuit.
[0005] The technical scheme adopted by the utility model is as follows:
[0006] A chip input end logic level detection circuit comprises:
[0007] An input inverter is used to receive the voltage signal of the input end and output the inverted voltage signal.
[0008] A diode device is connected between the input end and the power supply end of the input inverter, and supplies power to the input inverter when the input end is high, and turns off the circuit when the input end is low.
[0009] An energy storage device is used to maintain the high level at the power supply end of the input inverter when the input end is low.
[0010] Further, the diode device is a diode, the anode of the diode is connected to the input end, and the cathode of the diode is connected to the power supply end of the input inverter.
[0011] Further, the diode device is a MOS tube, the source, the gate and the substrate of the NMOS tube are connected together as the anode connected to the input end, and the drain of the NMOS tube is connected to the power supply end of the input inverter as the cathode.
[0012] Alternatively, the diode device is a PMOS tube, the source, the gate and the substrate of the PMOS tube are connected together as the cathode connected to the power supply end of the input inverter, and the drain of the PMOS tube is connected to the input end as the anode.
[0013] Further, the energy storage device is a capacitor, and the capacitor is connected between the ground end and the power supply end of the input inverter.
[0014] Further, the detection circuit further comprises a logic latch circuit, and the logic latch circuit is used to latch the low-level signal when the input end is at a low level, and maintain the high level at the power supply end of the input inverter.
[0015] Further, the logic latch circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube and an output inverter.
[0016] The first NMOS tube and the first PMOS tube are connected in series, and the second NMOS tube and the second PMOS tube are connected in series.
[0017] The gate of the first NMOS tube is used to receive a voltage signal of the input end, and the gate of the second NMOS tube is used to receive a voltage signal opposite to the logic level of the voltage signal of the input end.
[0018] The gate of the first PMOS tube is connected to the common end of the second NMOS tube and the second PMOS tube, and the gate of the second PMOS tube is connected to the common end of the first NMOS tube and the first PMOS tube.
[0019] The common end of the second NMOS tube and the second PMOS tube is connected to the input end of the output inverter, the output end of the inverter is connected to the gate of the third NMOS tube, and the third NMOS tube is connected in series to the input end of the output inverter.
[0020] Further, a feedback resistor is further connected in series between the third NMOS tube and the input end of the output inverter.
[0021] Further technical solutions are as follows: the logic latching circuit comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, an output inverter and a feedback inverter;
[0022] The first NMOS transistor and the first PMOS transistor are connected in series; and the second NMOS transistor and the second PMOS transistor are connected in series.
[0023] The gate of the first NMOS transistor is configured to receive a voltage signal of the input end; and the gate of the second NMOS transistor is configured to receive a voltage signal opposite to the logic level of the voltage signal of the input end.
[0024] The gate of the first PMOS transistor is connected to the common end of the second NMOS transistor and the second PMOS transistor; and the gate of the second PMOS transistor is connected to the common end of the first NMOS transistor and the first PMOS transistor.
[0025] The common end of the second NMOS transistor and the second PMOS transistor is connected to the input end of the output inverter; the output end of the output inverter is connected to the input end of the feedback inverter; and the output end of the feedback inverter is connected to the input end of the output inverter.
[0026] The beneficial effects of the present application are as follows:
[0027] In the input logic level detection circuit, the self-powered design is used, so that the judgment of the logic level is independent of the chip power voltage, the design scheme of increasing a stable power supply to ensure the flip point is avoided, the complexity of the design is reduced, and the circuit cost is reduced.
[0028] Meanwhile, since the detection circuit in the embodiment is a logic gate circuit, no current is consumed after the chip is powered on or powered off, and the chip energy consumption is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0029] Figure 1 The circuit diagram of an embodiment of the logic level detection circuit in the prior art.
[0030] Figure 2 The circuit diagram of the chip input logic level detection circuit in the embodiment of the present application.
[0031] Figure 3 The connection position diagram of the logic latching circuit in the embodiment of the present application.
[0032] Figure 4 The circuit diagram of the logic latching circuit in the embodiment of the present application.
[0033] Figure 5 FIG. 2 is a circuit diagram of another embodiment of the logic latch circuit in the utility model. DETAILED DESCRIPTION
[0034] The utility model discloses a specific embodiment in combination with the drawings.
[0035] Embodiment one
[0036] Figure 2 FIG. 1 is a circuit diagram of the chip input end logic level detection circuit in the utility model. As shown in the figure, the chip input end logic level detection circuit disclosed by the utility model comprises an input inverter, a diode device and an energy storage device. Figure 2 The input inverter INV1 is used for receiving the voltage signal IO of the input end and outputting the voltage signal ION after reversing the voltage signal IO. The input inverter INV1 is designed in the logic level detection circuit, which is used for improving the level compatibility, enhancing the noise suppression and protecting the internal circuit.
[0037] The diode device is connected between the input end and the power supply end of the input inverter INV1, and supplies power for the input inverter INV1 when the input end is at a high level and turns off the circuit when the input end is at a low level. Specifically, the diode device can be a single diode element or a device with diode characteristics connected by a MOS tube. Using the device with diode characteristics connected by a MOS tube can reduce the increase of lithography cost caused by chip technology.
[0038] The energy storage device is used for maintaining the high level at the power supply end of the input inverter INV1 when the input end is at a low level. The energy storage device can be a capacitor or other electrical components or circuit structures with energy storage characteristics.
[0039] As shown in the figure, in the embodiment, the diode device is a diode D1, the anode of the diode D1 is connected to the input end, and the cathode of the diode D1 is connected to the power supply end of the input inverter INV1. The energy storage device is a capacitor C1. The capacitor C1 is connected between the ground end and the power supply end of the input inverter INV1.
[0040] As an alternative, when the diode device is an NMOS tube, the source, gate and substrate of the NMOS tube are connected together as the anode to connect the input end, and the drain of the NMOS tube is connected as the cathode to connect the power supply end of the input inverter INV1. Alternatively, the diode device is a PMOS tube, the source, gate and substrate of the PMOS tube are connected together as the cathode to connect the power supply end of the input inverter INV1, and the drain of the PMOS tube is connected as the anode to connect the input end. Figure 2
[0041]
[0042] When the voltage signal IO at the input end changes from low level to high level, the voltage VPRE at the cathode of the diode D1 rises with the voltage at the input end and provides power supply for the input inverter INV1, at this time, because the received voltage signal of the input inverter INV1 and the power supply voltage of the input inverter INV1 are almost close to the same value, the flipping point of the input inverter INV1 is close to the threshold voltage of the NMOS device in the input inverter INV1.
[0043] When the voltage signal IO at the input end changes from high level to low level, the diode D1 is reverse blocked, because of the existence of the capacitor C1, the voltage VPRE at the cathode of the diode D1 is kept high through the capacitor C1, at this time, when the input voltage at the input end IO is less than the low threshold voltage of the input inverter INV1, the input inverter INV1 can still output high level, that is, the low level at the input end is judged.
[0044] In the embodiment as shown in the figure, Figure 2 The flipping level of the input inverter INV1 is related to the voltage VPRE, that is, the voltage signal IO at the input end, therefore, the flipping level of the circuit is not related to the power supply voltage of the chip, and because the voltage VPRE only provides power supply for the input inverter INV1, no current is consumed after the input inverter INV1 is flipped stably.
[0045] In the prior art, the port input voltage detection threshold of the logic level detection circuit changes with the change of the power supply voltage, and the detection circuit current consumption problem occurs when the port input is high level or low level. The embodiment solves the two problems in the prior art. In the embodiment, a self-powered design is used in the input end logic level detection circuit, so that the judgment of the logic level is not related to the power supply voltage of the chip, and because the detection circuit in the embodiment is a logic gate circuit, no current is consumed after the chip is powered on or powered off.
[0046] Embodiment two
[0047] Based on embodiment one, embodiment two proposes an optimized implementation.
[0048] In the Figure 2 circuit diagram, when the voltage signal IO at the input end changes from high level to low level, the charge on the capacitor C1 will slowly leak after a long time, which will cause the logic level judgment of the input inverter INV1 to fail. In view of this problem, embodiment two also proposes a more optimal implementation.
[0049] Figure 3 It is a schematic view of the connection position of the logic latching circuit in the embodiment of the utility model. Figure 4 It is a circuit diagram of the logic latching circuit in the embodiment of the utility model. As Figure 3and Figure 4 As shown, this embodiment further includes a logic latch circuit LS_RS.
[0050] The logic latch circuit LS_RS includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PMOS transistor P1, a second PMOS transistor P2, and an output inverter INV2.
[0051] The first NMOS transistor N1 and the first PMOS transistor N2 are connected in series. The second NMOS transistor N2 and the second PMOS transistor P2 are connected in series. In the description of two MOS transistors connected in series here and elsewhere in this document, it means that the source of the first MOS transistor is connected to the drain of the second MOS transistor, and the drain of the first MOS transistor and the source of the second MOS transistor serve as the two ends of this series circuit for connection in the circuit. The MOS transistors can be either NMOS transistors or PMOS transistors.
[0052] The gate of the first NMOS transistor N1 is used to receive the input voltage signal IO. The gate of the second NMOS transistor N2 is used to receive the voltage signal ION, which has the opposite logic level to the input voltage signal IO. That is, the gate of the second NMOS transistor N2 is connected to the output terminal ION of the input inverter INV1.
[0053] The gate of the first PMOS transistor P1 is connected to the common terminal of the second NMOS transistor N2 and the second PMOS transistor P2. The gate of the second PMOS transistor P2 is connected to the common terminal of the first NMOS transistor N1 and the first PMOS transistor P1. The common terminal of the second NMOS transistor N2 and the second PMOS transistor P2 is connected to the input terminal of the output inverter INV2. The output terminal of the output inverter INV2 is fed back to the input terminal of the output inverter INV2 through the gate of the third NMOS transistor N3. The third NMOS transistor N3 is connected in series between the input terminal of the output inverter INV2 and the ground terminal. A feedback resistor R is also included, connected in series between the third NMOS transistor N3 and the input terminal of the output inverter INV2.
[0054] In this embodiment, the gate of the first NMOS transistor N1 receives the input voltage signal IO, and the gate of the second NMOS transistor N2 receives a voltage signal ION that is logic level opposite to the input voltage signal IO. Then, the result is latched through interlocking of the first PMOS transistor P1 and the second PMOS transistor P2, along with feedback from the third NMOS transistor N3 and the feedback resistor R. When the input voltage signal IO is low, the output voltage signal ION of the input inverter INV1 is high. At this time, the second NMOS transistor N2 is turned on, and the common terminal of the second NMOS transistor N2 and the second PMOS transistor P2, i.e. Figure 4b point in the low level, the output end OUT of the output inverter INV2 is high level, the third NMOS tube N3 and the feedback resistance R feedback, b point is latched as low level, at this time the first PMOS tube P1 opens, the common end of the first NMOS tube N1 and the first PMOS tube P1, that is Figure 4 The a point is high level, the second PMOS tube P2 is closed, the signal state is latched, and the problem that the charge on the capacitor C1 slowly leaks when the voltage signal IO at the input end changes from high level to low level is solved.
[0055] Embodiment three
[0056] Based on embodiment one and embodiment two, embodiment three proposes another alternative implementation of the logic latching circuit LS_RS. Figure 5 The circuit diagram of another implementation of the logic latching circuit in the embodiment of the utility model.
[0057] As shown in Figure 5 The logic latching circuit LS_RS includes the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1, the second PMOS tube P2, the feedback inverter INV3 and the output inverter INV2. Among them, the connection mode of the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1, the second PMOS tube P2 is same with embodiment two. The output end of the output inverter INV2 is connected with the input end of the feedback inverter INV3. The output end of the feedback inverter INV3 is connected with the input end of the output inverter INV2.
[0058] When the voltage signal IO at the input end changes from high level to low level, b point is low level, at this time the output end OUT is high point level, and b point level is latched as low level through the feedback of the feedback inverter INV3. The feedback inverter INV3 is a weak pull-up and pull-down ability, that is, the inverter with weak ability to output low level signal or high level signal, and the driving pull-up and pull-down ability is weaker than that of the second PMOS tube P2 and the second NMOS tube N2. For example, one possible situation is that the driving current output by the feedback inverter INV3 is weaker than that of the second PMOS tube P2 and the second NMOS tube N2, or the output impedance of the feedback inverter INV3 is higher than that of the second PMOS tube P2 and the second NMOS tube N2. When the detection circuit works normally, the voltage signal IO at the input end can control the high and low level of b point through the second PMOS tube P2 and the second NMOS tube N2, and the feedback inverter INV3 does not affect the flip of working state. At the same time, in the latching state, since a point is high level, the second PMOS tube P2 is closed, and the feedback inverter INV3 can guarantee the low level latching state of b point only with weak pull-down ability.
[0059] Of course, those skilled in the art can know that, under the premise of being able to realize low-level signal latching, other circuit structures can also be used to realize the functions of the second and third embodiments, and the second and third embodiments are preferred solutions of the latch structure and not a limitation on the specific implementation of the latch structure.
[0060] The above description is an explanation of the utility model, not a limitation of the utility model, the range defined by the utility model is seen from the claims, and the utility model can be modified in any form without violating the basic structure of the utility model.
Claims
1. A chip input logic level detection circuit, characterized by, The application relates to a detection circuit for detecting a low-level signal of an input terminal, comprising: an input inverter for receiving a voltage signal of the input terminal and outputting the voltage signal after reversing the voltage signal; a diode device connected between the input terminal and a power supply terminal of the input inverter, for supplying power to the input inverter when the input terminal is at a high level and shutting down the circuit when the input terminal is at a low level; an energy storage device for maintaining a high level at the power supply terminal of the input inverter when the input terminal is at a low level.
2. The chip input logic level detection circuit according to claim 1, characterized in that: The diode device is a diode, the anode of the diode is connected to the input terminal, and the cathode of the diode is connected to the power supply terminal of the input inverter.
3. The chip input logic level detection circuit of claim 1, wherein: The diode device is formed by connecting MOS tubes; the diode device is an NMOS tube, the source, the gate and the substrate of the NMOS tube are connected together to serve as the anode and are connected to the input terminal, and the drain of the NMOS tube serves as the cathode and is connected to the power supply terminal of the input inverter; alternatively, the diode device is a PMOS tube, the source, the gate and the substrate of the PMOS tube are connected together to serve as the cathode and are connected to the power supply terminal of the input inverter, and the drain of the PMOS tube serves as the anode and is connected to the input terminal.
4. The chip input logic level detection circuit of claim 1, wherein: The energy storage device is a capacitor, and the capacitor is connected between a ground terminal and the power supply terminal of the input inverter.
5. The chip input logic level detection circuit of claim 1, wherein: The detection circuit further comprises a logic latch circuit, which is used for latching the low-level signal when the input terminal is at a low level and maintaining a high level at the power supply terminal of the input inverter.
6. The chip input logic level detection circuit of claim 5, wherein: The logic latch circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube and an output inverter; the first NMOS tube and the first PMOS tube are connected in series, and the second NMOS tube and the second PMOS tube are connected in series; the gate of the first NMOS tube is used for receiving a voltage signal of the input terminal, and the gate of the second NMOS tube is used for receiving a voltage signal whose logic level is opposite to that of the input terminal; the gate of the first PMOS tube is connected to a common terminal of the second NMOS tube and the second PMOS tube, and the gate of the second PMOS tube is connected to a common terminal of the first NMOS tube and the first PMOS tube; the common terminal of the second NMOS tube and the second PMOS tube is connected to the input terminal of the output inverter, the output terminal of the inverter is connected to the gate of the third NMOS tube, and the third NMOS tube is connected in series to the input terminal of the output inverter.
7. The chip input logic level detection circuit of claim 6, wherein: A feedback resistor is further connected in series between the third NMOS tube and the input terminal of the output inverter.
8. The chip input logic level detection circuit of claim 5, wherein: The logic latch circuit comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, an output inverter and a feedback inverter; the first NMOS tube and the first PMOS tube are connected in series, and the second NMOS tube and the second PMOS tube are connected in series; the gate of the first NMOS tube is used for receiving a voltage signal of the input terminal, and the gate of the second NMOS tube is used for receiving a voltage signal whose logic level is opposite to that of the input terminal; The gate of the first PMOS tube is connected to the common end of the second NMOS tube and the second PMOS tube; the gate of the second PMOS tube is connected to the common end of the first NMOS tube and the first PMOS tube; The common end of the second NMOS tube and the second PMOS tube is connected to the input end of an output inverter; the output end of the output inverter is connected to the input end of the feedback inverter; the output end of the feedback inverter is connected to the input end of an output inverter.