Circuit for inhibiting generation of high peak
By introducing a buffer circuit consisting of inductor L1, diodes D1 and D10, and a soft-switching design for MOSFETs Q2 and Q3 into the circuit, the problem of voltage spikes caused by transformer leakage inductance was solved, protecting the components and improving current efficiency, thus achieving safe power output.
Patent Information
- Application Number
- CN202423291074.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-12-30
- Estimated Expiration
- 2034-12-30
AI Technical Summary
In industrial power applications, transformers can cause excessively high voltage spikes in electrically connected components due to leakage inductance, which can lead to component burnout.
A buffer circuit is formed by inductor L1, diode D1 and diode D10. Excess voltage energy is discharged through diodes D1 and D10. Combined with the soft switching design of MOSFETs Q2 and Q3, capacitors Cq3 and Cq2 are used for filtering, capacitors EC1 and EC2 temporarily store voltage energy, and overload protection is provided through fuses F1, F2 and F3.
It effectively suppressed the voltage spikes generated by the transformer leakage inductance, protected the key components in the circuit, improved the output current efficiency, reduced the withstand voltage requirements of the MOSFET, and ensured the safe operation of the components.
Smart Images
Figure CN223744374U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit design technology, and in particular to a circuit for suppressing the generation of high spikes. Background Technology
[0002] Currently, in industrial power supply applications, the 380V AC input power needs to be stepped down by a transformer before being connected to electronic products. However, transformers can experience leakage inductance, leading to excessively high peak voltages on components electrically connected to the transformer, which can burn out these components. Utility Model Content
[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a circuit that suppresses the generation of high spikes, which can solve the problem of excessively high spike voltages in components electrically connected to the transformer due to transformer leakage inductance.
[0004] The objective of this utility model is achieved through the following technical solution:
[0005] The first aspect of this application provides a circuit for suppressing high peak generation, comprising: a power input module; a protection module including an inductor L1, a diode D1, and a diode D10, wherein a first end of the inductor L1 is electrically connected to the power input module, a second end of the inductor L1 is electrically connected to the first end of the diode D1 and the first end of the diode D10, and the second ends of the diode D1 and the second ends of the diode D1 and the diode D10 are respectively electrically connected to the power input module; and a power output module including a transformer T1, wherein the first ends of the diode D1 and the first ends of the diode D10 are respectively electrically connected to the transformer T1.
[0006] The power output module also includes MOSFET Q3, MOSFET Q2, inductor L2 and capacitor EC3. MOSFET Q3 and MOSFET Q2 are electrically connected to transformer T1 respectively. One end of inductor L2 is electrically connected to MOSFET Q2 and the other end of inductor L2 is electrically connected to capacitor EC3.
[0007] The power output module also includes capacitor Cq3 and capacitor Cq2. Capacitor Cq3 is connected in parallel with MOSFET Q3, and capacitor Cq2 is connected in parallel with MOSFET Q2.
[0008] The power input module includes diode D2, MOSFET Q1, diode D9, and MOSFET Q4. The first end of diode D2 is electrically connected to MOSFET Q1, and the second end of diode D2 is electrically connected to transformer T1. The first end of diode D9 is electrically connected to MOSFET Q4, and the second end of diode D9 is electrically connected to the first end of inductor L1.
[0009] The power input module also includes capacitors Cq1 and Cq4. Capacitor Cq1 is connected in parallel with MOSFET Q1, and capacitor Cq4 is connected in parallel with MOSFET Q4.
[0010] The power input module also includes capacitor EC1 and capacitor EC2. The first terminal of capacitor EC1 is electrically connected to the second terminal of diode D1, the second terminal of capacitor EC1 is electrically connected to the first terminal of capacitor EC2, and the second terminal of capacitor EC2 is electrically connected to the second terminal of diode D10.
[0011] The power input module also includes resistors R1 and R2, wherein resistor R1 is connected in parallel with capacitor EC1, and resistor R2 is connected in parallel with capacitor EC2.
[0012] The power input module further includes a rectifier unit, which includes diodes D3, D4, D5, D6, D7, and D8. The first terminal of diode D3 is electrically connected to the first terminal of capacitor EC1, the second terminal of diode D3 is electrically connected to the first terminal of diode D6, the second terminal of diode D6 is electrically connected to the second terminal of capacitor EC2, the first terminal of diode D4 is electrically connected to the first terminal of capacitor EC1, the second terminal of diode D4 is electrically connected to the first terminal of diode D7, the second terminal of diode D7 is electrically connected to the second terminal of capacitor EC2, the first terminal of diode D5 is electrically connected to the first terminal of capacitor EC1, the second terminal of diode D5 is electrically connected to the first terminal of diode D8, and the second terminal of diode D8 is electrically connected to the second terminal of capacitor EC2.
[0013] The power input module further includes capacitors CX1, CX2, and CX3, common-mode inductors LF1A, LF1B, and LF1C. The first terminal of capacitor CX1 is electrically connected to the first terminals of common-mode inductors LF1A and LF1B, respectively. The first terminal of capacitor CX1 is also electrically connected to the second terminal of diode D3. The second terminal of capacitor CX1 is electrically connected to the first terminal of capacitor CX2. The first terminal of common-mode inductor LF1B is electrically connected to the first terminal of capacitor CX2. The second terminal of capacitor CX2 is electrically connected to the second terminal of diode D5. The first terminal of capacitor CX3 is electrically connected to the first terminal of common-mode inductor LF1C. The second terminal of capacitor CX3 is electrically connected to the first terminal of capacitor CX1.
[0014] The power input module also includes fuses F1, F2 and F3. Fuse F1 is electrically connected to the second terminal of the common mode inductor LF1A, fuse F2 is electrically connected to the second terminal of the common mode inductor LF1B, and fuse F3 is electrically connected to the second terminal of the common mode inductor LF1C.
[0015] Compared with the prior art, the present invention has at least the following advantages:
[0016] Inductor L1, diode D1, and diode D10 form a buffer circuit. Inductor L1 limits the current. When the transformer leakage inductance generates a voltage spike, the voltage spike will cause diodes D1 and D10 to conduct. The excess voltage energy is discharged through diodes D1 and D10, thereby accumulating high voltage and achieving the purpose of clamping voltage and protecting circuit components. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the embodiments will be briefly described below.
[0018] Figure 1 This is a functional block diagram of a circuit for suppressing high peak generation in one embodiment of the present invention;
[0019] Figure 2 This is a circuit diagram of a circuit for suppressing the generation of high spikes in one embodiment of the present invention. Detailed Implementation
[0020] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make this application more thorough and complete, and to fully convey the scope of this application to those skilled in the art.
[0021] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0022] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0023] Currently, in industrial power supply applications, the 380V AC input power needs to be stepped down by a transformer before being connected to electronic products. However, transformers can experience leakage inductance, leading to excessively high peak voltages on components electrically connected to the transformer, which can burn out these components.
[0024] To address the aforementioned issues, this application provides a circuit for suppressing high voltage spikes, which can solve the problem of excessively high voltage spikes in components electrically connected to the transformer due to transformer leakage inductance.
[0025] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.
[0026] See Figure 1 and Figure 2 A circuit for suppressing high peak generation includes: a power input module 100, a protection module 200, and a power output module 300. The protection module 200 includes an inductor L1, a diode D1, and a diode D10. The first end of the inductor L1 is electrically connected to the power input module, and the second end of the inductor L1 is electrically connected to the first ends of the diodes D1 and D10, respectively. The second ends of the diodes D1 and D10 are also electrically connected to the power input module. The power output module 300 includes a transformer T1, and the first ends of the diodes D1 and D10 are electrically connected to the transformer T1, respectively.
[0027] It should be noted that inductor L1 serves as a current limiter. Furthermore, inductor L1, diode D1, and diode D10 form a buffer circuit. When the transformer leakage inductance generates a voltage spike, the voltage spike will cause diodes D1 and D10 to conduct, and the excess voltage energy will be discharged through diodes D1 and D10, thereby accumulating high voltage and achieving the purpose of clamping voltage and protecting circuit components.
[0028] See Figure 2In one embodiment, the power output module 300 further includes MOSFET Q3, MOSFET Q2, inductor L2 and capacitor EC3. MOSFET Q3 and MOSFET Q2 are electrically connected to transformer T1, one end of inductor L2 is electrically connected to MOSFET Q2, and the other end of inductor L2 is electrically connected to capacitor EC3.
[0029] It should be noted that inductor L2 serves as a freewheeling current source, and capacitor EC3 serves as a filter. Furthermore, MOSFETs Q2 and Q1 are soft switches, meaning they can be turned on at zero voltage and turned off at zero current. Moreover, due to the inclusion of inductor L1, diodes D1 and D10, the breakdown voltage of MOSFETs Q2 and Q3 is significantly reduced. Therefore, MOSFETs Q2 and Q3 can be selected with low-voltage, high-current specifications, thereby improving the efficiency of the output current.
[0030] See Figure 2 In one embodiment, the power output module 300 further includes capacitor Cq3 and capacitor Cq2, with capacitor Cq3 connected in parallel with MOSFET Q3 and capacitor Cq2 connected in parallel with MOSFET Q2.
[0031] It should be noted that capacitor Cq3 is the junction capacitance of MOSFET Q3, and capacitor Cq2 is the junction capacitance of MOSFET Q2.
[0032] See Figure 2 In one embodiment, the power input module 100 includes diode D2, MOSFET Q1, diode D9 and MOSFET Q4. The first end of diode D2 is electrically connected to MOSFET Q1, the second end of diode D2 is electrically connected to transformer T1, the first end of diode D9 is electrically connected to MOSFET Q4, and the second end of diode D9 is electrically connected to the first end of inductor L1.
[0033] It should be noted that diodes D2 and D9 serve to protect the components in the circuit.
[0034] See Figure 2 In one embodiment, the power input module 100 further includes capacitors Cq1 and Cq4, with capacitor Cq1 connected in parallel with MOSFET Q1 and capacitor Cq4 connected in parallel with MOSFET Q4.
[0035] It should be noted that capacitor Cq1 is the junction capacitance of MOSFET Q1, and capacitor Cq4 is the junction capacitance of MOSFET Q4.
[0036] See Figure 2In one embodiment, the power input module 100 further includes capacitors EC1 and EC2. The first terminal of capacitor EC1 is electrically connected to the second terminal of diode D1, the second terminal of capacitor EC1 is electrically connected to the first terminal of capacitor EC2, and the second terminal of capacitor EC2 is electrically connected to the second terminal of diode D10. Specifically, the power input module also includes resistors R1 and R2. Resistor R1 is connected in parallel with capacitor EC1, and resistor R2 is connected in parallel with capacitor EC2.
[0037] It should be noted that capacitors EC1 and EC2 not only serve a filtering function, but the energy discharged by diodes D1 and D10 will also be temporarily stored in capacitors EC1 and EC2 before being released through the HVDC port. Because capacitors EC1 and EC2 are too large, two resistors R1 and R2 are used to balance their voltages and prevent them from becoming unbalanced.
[0038] See Figure 2 In one embodiment, the power input module 100 further includes a rectifier unit, which includes diodes D3, D4, D5, D6, D7, and D8. The first terminal of diode D3 is electrically connected to the first terminal of capacitor EC1, the second terminal of diode D3 is electrically connected to the first terminal of diode D6, the second terminal of diode D6 is electrically connected to the second terminal of capacitor EC2, the first terminal of diode D4 is electrically connected to the first terminal of capacitor EC1, the second terminal of diode D4 is electrically connected to the first terminal of diode D7, the second terminal of diode D7 is electrically connected to the second terminal of capacitor EC2, the first terminal of diode D5 is electrically connected to the first terminal of capacitor EC1, the second terminal of diode D5 is electrically connected to the first terminal of diode D8, and the second terminal of diode D8 is electrically connected to the second terminal of capacitor EC2.
[0039] It should be noted that diodes D3, D4, D5, D6, D7, and D8 have unidirectional conductivity. These diodes can be used to convert alternating current into direct current, thus achieving rectification.
[0040] See Figure 2In one embodiment, the power input module 100 further includes capacitors CX1, CX2, and CX3, common-mode inductors LF1A, LF1B, and LF1C. The first terminal of capacitor CX1 is electrically connected to the first terminals of common-mode inductors LF1A and LF1B, respectively. The first terminal of capacitor CX1 is also electrically connected to the second terminal of diode D3. The second terminal of capacitor CX1 is electrically connected to the first terminal of capacitor CX2. The first terminal of common-mode inductor LF1B is electrically connected to the first terminal of capacitor CX2. The second terminal of capacitor CX2 is electrically connected to the second terminal of diode D5. The first terminal of capacitor CX3 is electrically connected to the first terminal of common-mode inductor LF1C, and the second terminal of capacitor CX3 is electrically connected to the first terminal of capacitor CX1.
[0041] It should be noted that capacitors CX1, CX2, and CX3, as well as common-mode inductors LF1A, LF1B, and LF1C, serve as filters, while common-mode inductors LF1A, LF1B, and LF1C also suppress common-mode interference.
[0042] See Figure 2 In one embodiment, the power input module 100 further includes fuses F1, F2 and F3. Fuse F1 is electrically connected to the second terminal of common mode inductor LF1A, fuse F2 is electrically connected to the second terminal of common mode inductor LF1B, and fuse F3 is electrically connected to the second terminal of common mode inductor LF1C.
[0043] It should be noted that fuses F1, F2, and F3 serve as overload protection.
[0044] The principles of this application are explained below:
[0045] A 380V three-phase AC power supply is input through pins L1, L2, and L3. After passing through fuses F1, F2, and F3, and then filtered by capacitors CX1, CX2, CX3, common-mode inductors LF1A, LF1B, and LF1C, it enters the rectifier unit for rectification. During this time, MOSFETs Q1 and Q4 are turned on. When the transformer leakage inductance generates a voltage spike, this spike causes diodes D1 and D10 to turn on. Excess voltage energy is discharged through diodes D1 and D10 to capacitors EC1 and EC2 for temporary storage, and then released through the HVDC port, thus protecting MOSFETs Q2 and Q3. Finally, the current is output through the OUT interface.
[0046] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different focuses; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.
[0047] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A circuit for suppressing the generation of high spikes, characterized by comprising: The power input module comprises: a protection module comprising an inductor L1, a diode D1 and a diode D10, a first end of the inductor L1 is electrically connected with the power input module, a second end of the inductor L1 is respectively electrically connected with a first end of the diode D1 and a first end of the diode D10, a second end of the diode D1 and a second end of the diode D10 are respectively electrically connected with the power input module; a power output module comprising a transformer T1, a first end of the diode D1 and a first end of the diode D10 are respectively electrically connected with the transformer T1. The power output module further comprises a MOS tube Q3, a MOS tube Q2, an inductor L2 and a capacitor EC3, the MOS tube Q3 and the MOS tube Q2 are respectively electrically connected with the transformer T1, one end of the inductor L2 is electrically connected with the MOS tube Q2, the other end of the inductor L2 is electrically connected with the capacitor EC3.
2. The circuit for suppressing high spike generation according to claim 1, characterized by, The power output module further comprises a capacitor Cq3 and a capacitor Cq2, the capacitor Cq3 is connected in parallel with the MOS tube Q3, and the capacitor Cq2 is connected in parallel with the MOS tube Q2.
3. The circuit for suppressing high spike generation according to claim 2, characterized by, The power input module comprises a diode D2, a MOS tube Q1, a diode D9 and a MOS tube Q4, a first end of the diode D2 is electrically connected with the MOS tube Q1, a second end of the diode D2 is electrically connected with the transformer T1, a first end of the diode D9 is electrically connected with the MOS tube Q4, and a second end of the diode D9 is electrically connected with a first end of the inductor L1.
4. The circuit for suppressing high spike generation according to claim 1, wherein The power input module further comprises a capacitor Cq1 and a capacitor Cq4, the capacitor Cq1 is connected in parallel with the MOS tube Q1, and the capacitor Cq4 is connected in parallel with the MOS tube Q4.
5. The circuit for suppressing high spike generation according to claim 4, wherein The power input module further comprises a capacitor EC1 and a capacitor EC2, a first end of the capacitor EC1 is electrically connected with a second end of the diode D1, a second end of the capacitor EC1 is electrically connected with a first end of the capacitor EC2, and a second end of the capacitor EC2 is electrically connected with a second end of the diode D10.
6. The circuit for suppressing high spike generation according to claim 1, wherein The power input module further comprises a resistor R1 and a resistor R2, the resistor R1 is connected in parallel with the capacitor EC1, and the resistor R2 is connected in parallel with the capacitor EC2.
7. The circuit for suppressing high spike generation according to claim 6, wherein 8. The circuit for suppressing high spike generation according to claim 6, wherein The power input module further comprises a rectifier unit, the rectifier unit comprises a diode D3, a diode D4, a diode D5, a diode D6, a diode D7 and a diode D8, the first end of the diode D3 is electrically connected with the first end of the capacitor EC1, the second end of the diode D3 is electrically connected with the first end of the diode D6, the second end of the diode D6 is electrically connected with the second end of the capacitor EC2, the first end of the diode D4 is electrically connected with the first end of the capacitor EC1, the second end of the diode D4 is electrically connected with the first end of the diode D7, the second end of the diode D7 is electrically connected with the second end of the capacitor EC2, the first end of the diode D5 is electrically connected with the first end of the capacitor EC1, the second end of the diode D5 is electrically connected with the first end of the diode D8, the second end of the diode D8 is electrically connected with the second end of the capacitor EC2.
9. The circuit for suppressing high spike generation according to claim 8, wherein The power input module further comprises a capacitor CX1, a capacitor CX2, a capacitor CX3, a common mode inductor LF1A, a common mode inductor LF1B and a common mode inductor LF1C, the first end of the capacitor CX1 is electrically connected with the first end of the common mode inductor LF1A and the first end of the common mode inductor LF1B respectively, the first end of the capacitor CX1 is also electrically connected with the second end of the diode D3, the second end of the capacitor CX1 is electrically connected with the first end of the capacitor CX2, the first end of the common mode inductor LF1B is electrically connected with the first end of the capacitor CX2, the second end of the capacitor CX2 is electrically connected with the second end of the diode D5, the first end of the capacitor CX3 is electrically connected with the first end of the common mode inductor LF1C, the second end of the capacitor CX3 is electrically connected with the first end of the capacitor CX1.
10. The circuit for suppressing high spike generation according to claim 9, wherein The power input module further comprises a fuse F1, a fuse F2 and a fuse F3, the fuse F1 is electrically connected with the second end of the common mode inductor LF1A, the fuse F2 is electrically connected with the second end of the common mode inductor LF1B, the fuse F3 is electrically connected with the second end of the common mode inductor LF1C.