Low-voltage device electrostatic discharge protection circuit and chip

Abstract

The utility model relates to a low-voltage device electrostatic discharge protection circuit and a chip, and the circuit comprises a bias circuit unit, the electric input end of which is coupled to a power supply voltage line, and the electric output end of which is coupled to a bias point; the electric input end of the low-voltage device voltage division circuit unit is coupled to the power supply voltage line, and the control end of the low-voltage device voltage division circuit unit is coupled to the bias point; the electric input end of the RC trigger circuit unit is coupled to the bias point position, and the grounding end of the RC trigger circuit unit is coupled to a reference ground wire; and the electric input end of the low-voltage device clamping circuit unit is coupled to the electric output end of the low-voltage device voltage division circuit unit, the electric output end of the low-voltage device clamping circuit unit is coupled to a reference ground wire, and the control end of the low-voltage device clamping circuit unit is coupled to the control output end of the RC trigger circuit unit. According to the electrostatic discharge protection circuit, miniaturization of the area of the electrostatic discharge protection circuit is facilitated, the non-uniform triggering condition during electrostatic discharge is weakened, and the electrostatic discharge capability is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of chip electrostatic protection, and in particular, to a low-voltage device electrostatic discharge protection circuit and a chip. BACKGROUND

[0002] As an electrostatic discharge (ESD) protection circuit of an integrated circuit, a power clamp circuit is crucial for the normal operation of the integrated circuit and for protecting the integrated circuit from external static electricity.

[0003] The power clamp circuit can prevent abnormal fluctuations in the power supply voltage from damaging the internal components of the integrated circuit. When subjected to electrostatic discharge, such as a sudden high voltage between the power supply voltage line and the reference ground line, the power clamp circuit quickly discharges current to prevent large current from flowing through the integrated circuit, thereby protecting the integrated circuit. The power clamp circuit is commonly used in the protection design of chip power pins (such as power voltage line pins and reference ground line pins) and can support test standards such as the human body model (HBM).

[0004] The electrostatic discharge protection circuit using the power clamp circuit is usually arranged near the power pins of the chip. As the critical dimension (CD) of the integrated circuit in the chip continues to decrease, the integration level of the integrated circuit is increasingly high, and the function is increasingly complex. Consequently, the number of related power pins is also increasing, and the size of the power pins is also becoming smaller, which leads to the need to reduce the electrostatic discharge protection circuit. However, the related devices in the electrostatic discharge protection circuit, such as the discharge device in the power clamp circuit, will inevitably change its performance after being reduced, which may cause unpredictable problems. If the original electrostatic discharge protection circuit is continued to be used, it will inevitably occupy a larger relative area in the chip, thereby hindering the miniaturization process of the integrated circuit and making it increasingly difficult to meet the current discharge requirements of the integrated circuit after miniaturization.

[0005] Figure 1 is a structure diagram of an electrostatic discharge protection circuit in the related art, as shown in Figure 1As shown, the ESD protection circuit includes a resistor R, a capacitor C, an inverter INV, and a clamping circuit unit PC. The resistor R and the capacitor C are connected in series between a power supply voltage and a reference ground and form an RC circuit. An input terminal of the inverter INV is coupled between the resistor R and the capacitor C. An output terminal of the inverter INV is coupled to a control terminal of the clamping circuit unit PC. A high-voltage access terminal of the clamping circuit unit PC is coupled to the power supply voltage. A low-voltage access terminal of the clamping circuit unit PC is coupled to the reference ground. Because the ESD protection circuit is placed near a chip power pin and needs to ensure that it is not broken down by high voltage of static electricity when discharging current, the clamping circuit unit PC includes a plurality of high-voltage MOS (Metal Oxide Semiconductor) devices. Because these MOS devices are MOS devices applied to an analog circuit part, the working voltage domain is higher than that of MOS devices used in digital circuits, which can ensure that the MOS devices are not broken down by high voltage of static electricity. Therefore, in the embodiment of the present disclosure, the MOS devices are referred to as high-voltage MOS devices. Because the MOS devices applied to the analog circuit part need to ensure that the amplitude attenuation of signals in the external data transmission channel of the chip or chiplet is as small as possible, a higher working voltage domain is required. Therefore, the high-voltage MOS devices can also be referred to as IO devices (input / output devices).

[0006] Taking the plurality of high-voltage NMOS (N-channel Metal-Oxide-Semiconductor) devices included in the clamping circuit unit PC as an example, the gates of the plurality of high-voltage NMOS devices are coupled to the output terminal of the inverter INV (the control terminal of the clamping circuit unit PC is the gate of the plurality of high-voltage NMOS devices). The sources of the plurality of high-voltage NMOS devices are coupled to the reference ground. The drains of the plurality of high-voltage NMOS devices are coupled to the power supply voltage.

[0007] The time constant of the RC circuit is usually 0.1 μs to 1 μs. When static electricity is generated, the rising edge of the voltage on the power supply voltage side is detected by the RC circuit (the rising time of the voltage rising edge of typical static electricity is about 10 ns). At this time, because the charging process of the capacitor C cannot keep up with the voltage rising speed of the static electricity, the connection point between the resistor R and the capacitor C, i.e., the input terminal of the inverter INV, is in a low-level state, which makes the inverter INV output a high level and turn on the plurality of high-voltage MOS devices of the clamping circuit unit PC. High-voltage static electricity of the power supply voltage is discharged to the reference ground through the turned-on high-voltage MOS devices, thereby achieving the purpose of static electricity discharge.

[0008] In normal circumstances, at the time of starting, the power supply voltage gradually rises from 0V to the working voltage, and the rise of the power supply voltage is a slow rise of the order of milliseconds (ms). Because the time constant of the RC circuit is usually 0.1 to 1 microseconds, the voltage at the connection point between the resistor R and the capacitor C, that is, the input end of the inverter INV, can follow the rising speed of the power supply voltage, so the inverter INV will not turn on the high-voltage MOS device of the clamping circuit unit PC to discharge current, and thus the power supply voltage can normally power the integrated circuit.

[0009] With the continuous reduction of the critical size of the integrated circuit, the integration level of the integrated circuit is getting higher and higher, and the number of pins of the power supply part is also increasing, and the arrangement of the power supply pins is also getting denser. In the electrostatic discharge protection circuit in the related art as shown in Figure 1 The clamping circuit unit PC includes a plurality of high-voltage MOS devices, and in order to ensure that the high-voltage MOS devices are not broken down, the size of the high-voltage MOS devices cannot be reduced, so the size is relatively large. At the same time, in order to ensure the effective release of static electricity, a large number of high-voltage MOS devices need to be arranged, and there is some redundancy in the number of high-voltage MOS devices, thereby occupying too much area. At the same time, during the release of static electricity, the discharge current is not discharged through all the high-voltage MOS devices, but may be discharged from some local high-voltage MOS devices, so it will also cause non-uniform triggering between multiple high-voltage MOS devices. Therefore, overall, the area of the electrostatic discharge protection circuit in the related art cannot be further reduced, and the utilization rate is not ideal. Invention content

[0010] Therefore, the present disclosure provides a low-voltage device electrostatic discharge protection circuit and a chip to realize smaller area and higher discharge current capability, and help improve the uniform triggering capability of the clamping circuit.

[0011] According to an aspect of an embodiment of the present disclosure, a low-voltage device electrostatic discharge protection circuit is provided, comprising:

[0012] A bias circuit unit, an electrical input end of the bias circuit unit being coupled to a power supply voltage line, and an electrical output end of the bias circuit unit being coupled to a bias point;

[0013] A low-voltage device voltage dividing circuit unit, an electrical input end of the low-voltage device voltage dividing circuit unit being coupled to the power supply voltage line, and a control end of the low-voltage device voltage dividing circuit unit being coupled to the bias point;

[0014] An RC trigger circuit unit, an electrical input end of the RC trigger circuit unit being coupled to the bias point, and a ground end of the RC trigger circuit unit being coupled to a reference ground line;

[0015] a low-voltage device clamping circuit unit, an electrical input end of the low-voltage device clamping circuit unit is coupled to an electrical output end of the low-voltage device voltage dividing circuit unit, an electrical output end of the low-voltage device clamping circuit unit is coupled to the reference ground, and a control end of the low-voltage device clamping circuit unit is coupled to the control output end of the RC trigger circuit unit.

[0016] In a possible implementation, the bias circuit unit comprises:

[0017] at least one first MOS transistor, a gate of each of the first MOS transistors is coupled to a respective electrical output end of the first MOS transistor;

[0018] in a case where the number of the first MOS transistors is one, an electrical input end of the first MOS transistor is coupled to the power supply voltage line, and an electrical output end of the first MOS transistor is coupled to the bias point;

[0019] in a case where the number of the first MOS transistors is two, the two first MOS transistors are connected in parallel or in series between the power supply voltage line and the bias point;

[0020] in a case where the number of the first MOS transistors is more than two, the first MOS transistors are connected in parallel, in series, or in series-parallel between the power supply voltage line and the electrical input end of the bias point.

[0021] In a possible implementation, the first MOS transistor is a high-voltage MOS transistor used in an analog circuit or a low-voltage MOS transistor used in a digital circuit.

[0022] In a possible implementation, the low-voltage device voltage dividing circuit unit comprises:

[0023] at least one second MOS transistor coupled between the power supply voltage line and the electrical input end of the low-voltage device clamping circuit unit, a gate of each of the second MOS transistors is coupled to the bias point;

[0024] in a case where the number of the second MOS transistors is one, an electrical input end of the second MOS transistor is coupled to the power supply voltage line, and an electrical output end of the second MOS transistor is coupled to the low-voltage device clamping circuit unit;

[0025] in a case where the number of the second MOS transistors is two, the two second MOS transistors are connected in parallel or in series between the power supply voltage line and the electrical input end of the low-voltage device clamping circuit unit;

[0026] In the case where the number of the second MOS tubes is multiple, the multiple second MOS tubes are connected in parallel, in series, or in series-parallel connection between the power voltage line and the electric input end of the low-voltage device clamping circuit unit.

[0027] In a possible implementation, the second MOS tube is a low-voltage MOS tube for a digital circuit.

[0028] In a possible implementation, the RC trigger circuit unit comprises:

[0029] a resistor, one end of the resistor being coupled to the bias point;

[0030] a MOS tube resistor circuit, an electric input end of the MOS tube resistor circuit being coupled to the other end of the resistor;

[0031] a capacitor, one end of the capacitor being coupled to an electric output end of the MOS tube resistor circuit, and the other end of the capacitor being coupled to the reference ground line;

[0032] an inverter, an input end of the inverter being coupled to the electric output end of the MOS tube resistor circuit, and an output end of the inverter being coupled to the control end of the low-voltage device clamping circuit unit.

[0033] In a possible implementation, the MOS tube resistor circuit comprises:

[0034] at least one third MOS tube, a gate of each of the third MOS tubes being coupled to the respective electric output end of the third MOS tube;

[0035] In the case where the number of the third MOS tubes is one, an electric input end of the third MOS tube is coupled to the resistor, and an electric output end of the third MOS tube is coupled to the capacitor;

[0036] In the case where the number of the third MOS tubes is two, the two third MOS tubes are connected in parallel or in series between the resistor and the capacitor;

[0037] In the case where the number of the third MOS tubes is multiple, the multiple third MOS tubes are connected in parallel, in series, or in series-parallel connection between the resistor and the capacitor.

[0038] In a possible implementation, the third MOS tube is a high-voltage MOS tube for an analog circuit or a low-voltage MOS tube for a digital circuit.

[0039] In a possible implementation, the low-voltage device clamping circuit unit comprises:

[0040] at least one fourth MOS transistor coupled between the electrical output terminal of the low-voltage device voltage dividing circuit unit and the reference ground, a gate of each of the fourth MOS transistors being coupled to the control output terminal of the RC trigger circuit unit;

[0041] in a case where the number of the fourth MOS transistors is one, an electrical input terminal of the fourth MOS transistor being coupled to the electrical output terminal of the low-voltage device voltage dividing circuit unit, and an electrical output terminal of the fourth MOS transistor being coupled to the reference ground;

[0042] in a case where the number of the fourth MOS transistors is two, the two fourth MOS transistors being connected in parallel or in series between the electrical output terminal of the low-voltage device voltage dividing circuit unit and the reference ground;

[0043] in a case where the number of the fourth MOS transistors is more than two, the fourth MOS transistors being connected in parallel, in series, or in a series-parallel manner between the electrical output terminal of the low-voltage device voltage dividing circuit unit and the reference ground.

[0044] In a possible implementation, the fourth MOS transistor is a low-voltage MOS transistor used in a digital circuit.

[0045] According to another aspect of the embodiments of the present disclosure, there is provided a chip comprising the low-voltage device electrostatic discharge protection circuit as described in any of the above.

[0046] The low-voltage device electrostatic discharge protection circuit and the chip of the present disclosure use a low-voltage device clamping circuit unit composed of low-voltage devices, the current density of the low-voltage devices per unit area is higher than that of high-voltage devices, and the current discharge capacity of the low-voltage devices is stronger than that of the high-voltage devices in the same area. In the case of achieving the same current discharge capacity, the area of the low-voltage device clamping circuit unit is much smaller than that of the clamping circuit unit using high-voltage devices in the related art. Therefore, compared with the related art, the present disclosure helps to miniaturize the circuit area. Moreover, compared with high-voltage devices, the threshold voltage of low-voltage devices is lower, and it is easier to enter the sub-threshold state and to turn on, which also helps to weaken the non-uniform triggering phenomenon of the low-voltage device clamping circuit unit.

[0047] The low-voltage device voltage dividing circuit unit is added to the low-voltage device clamping circuit unit to divide the voltage between the power supply voltage line and the reference ground line, so that the voltage between the power supply voltage line and the reference ground line does not apply to the low-voltage device clamping circuit unit to break the low-voltage device clamping circuit unit. On one side of the biasing circuit unit and the RC trigger circuit unit, the low-voltage device voltage dividing circuit unit is given a suitable biasing voltage by the biasing point, so that the low-voltage device voltage dividing circuit unit functions as a resistor to divide the voltage, and when electrostatic discharge occurs, the low-voltage device voltage dividing circuit unit functioning as a resistor can ensure that the current is discharged without breaking the low-voltage device voltage dividing circuit unit and the devices in the low-voltage device voltage dividing circuit unit.

[0048] The biasing circuit unit and the MOS resistor circuit are introduced on one side of the biasing circuit unit and the RC trigger circuit unit, so that the resistance value of the resistor in the RC trigger circuit is shared, and therefore the resistance can be made smaller. On this basis, when the layout design is performed, the smaller resistance can be arranged in the device layer or the metal layer. When the smaller resistance is arranged in the device layer, a large amount of space can be saved for the arrangement of the biasing circuit unit, the low-voltage device voltage dividing circuit unit, the MOS resistor circuit, and the MOS transistor in the low-voltage device clamping circuit unit. When the smaller resistance is arranged in the metal layer, the occupied space of the resistance in the device layer can be completely saved. Therefore, the low-voltage device electrostatic discharge protection circuit according to the present disclosure is helpful to the miniaturization of the area and the weakening of the non-uniform triggering condition during electrostatic discharge, and is helpful to the improvement of the electrostatic discharge capacity.

[0049] In summary, the low-voltage device electrostatic discharge protection circuit and the chip according to the present disclosure are helpful to the miniaturization of the area and the weakening of the non-uniform triggering condition during electrostatic discharge, and are helpful to the improvement of the electrostatic discharge capacity. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 is a structure diagram of an electrostatic discharge protection circuit in the related art;

[0051] Figure 2 is a structure diagram of a low-voltage device electrostatic discharge protection circuit according to an illustrative embodiment;

[0052] Figure 3 is a structure diagram of a low-voltage device electrostatic discharge protection circuit according to an illustrative embodiment.

[0053] In the drawings, the components represented by the reference numerals are as follows:

[0054] R, resistor,

[0055] C, capacitor,

[0056] INV, inverter,

[0057] PC, clamping circuit unit,

[0058] VDD, power voltage line,

[0059] VSS, reference ground line,

[0060] 1, bias circuit unit,

[0061] 2, low-voltage device voltage dividing circuit unit,

[0062] 3, RC trigger circuit unit,

[0063] 31, MOS tube resistance circuit,

[0064] 4, low-voltage device clamping circuit unit,

[0065] BP, bias point,

[0066] M1, first MOS tube,

[0067] M2, second MOS tube,

[0068] M3, third MOS tube,

[0069] M4, fourth MOS tube. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0071] It should be noted that the terms "first", "second" and the like in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0072] The "coupling (or connection)" used in the specification and claims of the present disclosure can refer to any direct or indirect connection means, for example, the first device is coupled (or connected) to the second device, which should be interpreted as the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means.

[0073] Therefore, the embodiments of the present disclosure provide a low-voltage device electrostatic discharge protection circuit and a chip to ensure the realization of electrostatic current discharge capability, help the electrostatic discharge protection circuit to be further miniaturized, help to reduce the layout area, and weaken the influence of non-uniform triggering.

[0074] Figure 2 is a low-voltage device electrostatic discharge protection circuit schematic diagram according to an illustrative embodiment, as shown in Figure 2As shown, the low-voltage device electrostatic discharge protection circuit includes a bias circuit unit 1, a low-voltage device voltage dividing circuit unit 2, an RC trigger circuit unit 3, and a low-voltage device clamping circuit unit 4. The electrical input end of the bias circuit unit 1 is coupled to the power supply voltage line VDD, and the electrical output end of the bias circuit unit 1 is coupled to a bias point BP. The electrical input end of the low-voltage device voltage dividing circuit unit 2 is coupled to the power supply voltage line VDD, and the control end of the low-voltage device voltage dividing circuit unit 2 is coupled to the bias point BP. The electrical input end of the RC trigger circuit unit 3 is coupled to the bias point BP, and the ground end of the RC trigger circuit unit 3 is coupled to the reference ground line VSS. The electrical input end of the low-voltage device clamping circuit unit 4 is coupled to the electrical output end of the low-voltage device voltage dividing circuit unit 2, the electrical output end of the low-voltage device clamping circuit unit 4 is coupled to the reference ground line VSS, and the control end of the low-voltage device clamping circuit unit 4 is coupled to the control output end of the RC trigger circuit unit 3.

[0075] The low-voltage device electrostatic discharge protection circuit of the embodiments of the present disclosure adopts the low-voltage device clamping circuit unit 4. Compared with the clamping circuit unit PC of the related art which adopts a high-voltage MOS device, because the low-voltage device is adopted, due to the characteristics of the device itself, the current density of the low-voltage device per unit area is higher than that of the high-voltage device, so under the same area, the current discharge capacity of the low-voltage device is stronger than that of the high-voltage device. Further, in the case of realizing the same current discharge capacity, the area of the low-voltage device clamping circuit unit 4 is much smaller than that of the clamping circuit unit PC of the related art which adopts a high-voltage device, so compared with the related art, the electrostatic discharge protection circuit of the embodiments of the present disclosure helps to miniaturize the circuit area. Moreover, compared with the high-voltage device, the threshold voltage (Vth) of the low-voltage device is lower, it is easier to enter the sub-threshold state and it is easier to open, which also helps to weaken the non-uniform triggering phenomenon of the low-voltage device clamping circuit unit 4. Therefore, the low-voltage device electrostatic discharge protection circuit of the embodiments of the present disclosure helps to miniaturize the area and weaken the non-uniform triggering situation during electrostatic discharge, and helps to improve the electrostatic discharge capacity.

[0076] The low-voltage device electrostatic discharge protection circuit of the embodiment of the present disclosure, because the withstand voltage value of the low-voltage device is low, the low-voltage device cannot work in the voltage domain of the high-voltage device, therefore, in the embodiment of the present disclosure, a low-voltage device voltage dividing circuit unit 2 is added, the low-voltage device voltage dividing circuit unit 2 and the low-voltage device clamping circuit unit 4 are coupled in cascade between the power supply voltage line VDD and the reference ground line VSS, the low-voltage device voltage dividing circuit unit 2 is used to divide the voltage of the low-voltage device clamping circuit unit 4, so that the voltage between the power supply voltage line VDD and the reference ground line VSS will not be applied to the low-voltage device clamping circuit unit 4 to break down the low-voltage device clamping circuit unit 4. On the side of the biasing circuit unit 1 and the RC trigger circuit unit 3, the low-voltage device voltage dividing circuit unit 2 is given a suitable bias voltage through the biasing point BP, so that the low-voltage device voltage dividing circuit unit 2 plays a role of resistance to divide the voltage, and when the electrostatic discharge occurs, the low-voltage device voltage dividing circuit unit 2 playing a role of resistance can ensure that the current discharge will not break down the low-voltage device voltage dividing circuit unit 2 and the devices in the low-voltage device voltage dividing circuit unit 2.

[0077] Figure 3 is a circuit structure schematic diagram of a specific application scenario of the low-voltage device electrostatic discharge protection circuit according to an illustrative embodiment, and the low-voltage device electrostatic discharge protection circuit of the present disclosure will be further described below in combination with the specific circuit structure of Figure 3 .

[0078] As shown in Figure 3 , in the illustrative embodiment, the biasing circuit unit 1 includes at least one first MOS tube M1, and the gate of each first MOS tube M1 is coupled to the respective electrical output end of the first MOS tube M1. In the case of one first MOS tube M1, the electrical input end of the first MOS tube M1 is coupled to the power supply voltage line VDD, and the electrical output end of the first MOS tube M1 is coupled to the biasing point BP. In the case of two first MOS tubes M1, the two first MOS tubes M1 are connected in parallel or in series between the power supply voltage line VDD and the biasing point BP. In the case of multiple first MOS tubes M1, the multiple first MOS tubes M1 are connected in any one of parallel connection, series connection, series-parallel mixed connection, between the electrical input end of the power supply voltage line VDD and the biasing point BP.

[0079] It should be noted that, Figure 3 only one first MOS tube M1 is shown in the above embodiment, which can represent one first MOS tube M1, or two first MOS tubes M1 connected in parallel or in series, or multiple first MOS tubes M1 connected in parallel, series, or series-parallel mixed connection.

[0080] As shown in Figure 3As shown, in the illustrative embodiment, the first MOS transistor M1 is an NMOS, and the electrical input end of the first MOS transistor M1 is the drain of the NMOS, and the electrical output end of the first MOS transistor M1 is the source of the NMOS. In addition, the first MOS transistor M1 can also be a PMOS (P-channel Metal-Oxide-Semiconductor), and in the case where the first MOS transistor M1 is a PMOS, the electrical input end of the first MOS transistor M1 is the source of the PMOS, and the electrical output end of the first MOS transistor M1 is the drain of the PMOS.

[0081] In the embodiments of the present disclosure, the biasing circuit unit 1 functions to generate the required bias voltage at the bias point BP, and the connection mode of the first MOS transistor M1 enables the first MOS transistor M1 to function as a resistor. Compared with conventional resistors (such as metal resistors and poly resistors), the first MOS transistor M1 has a smaller area, and thus using the first MOS transistor M1 as a resistor helps to ensure the miniaturization of the low-voltage device ESD protection circuit as a whole.

[0082] In the illustrative embodiment, the first MOS transistor M1 can be a high-voltage MOS transistor for analog circuits or a low-voltage MOS transistor for digital circuits as required. Meanwhile, the resistance values of high-voltage MOS transistors and low-voltage MOS transistors are different when used as resistors, and thus, in order to obtain more accurate bias voltage, when multiple first MOS transistors M1 are included in the biasing circuit unit 1, the multiple first MOS transistors M1 can also be implemented in a mixed mode of high-voltage MOS transistors and low-voltage MOS transistors, i.e., a part of the first MOS transistors M1 are high-voltage MOS transistors and another part of the first MOS transistors M1 are low-voltage MOS transistors.

[0083] For the series connection mode of the first MOS transistors M1, the electrical output end of the front first MOS transistor M1 is connected to the electrical input end of the rear first MOS transistor M1 between the front and rear first MOS transistors M1. For the parallel connection mode of the first MOS transistors M1, the electrical input ends of the parallel first MOS transistors M1 are connected to each other, and the electrical output ends of the parallel first MOS transistors M1 are connected to each other.

[0084] As shown, in the illustrative embodiment, the first MOS transistor M1 is an NMOS, and the electrical input end of the first MOS transistor M1 is the drain of the NMOS, and the electrical output end of the first MOS transistor M1 is the source of the NMOS. In addition, the first MOS transistor M1 can also be a PMOS (P-channel Metal-Oxide-Semiconductor), and in the case where the first MOS transistor M1 is a PMOS, the electrical input end of the first MOS transistor M1 is the source of the PMOS, and the electrical output end of the first MOS transistor M1 is the drain of the PMOS. Figure 3As shown in the illustrative embodiment, the low-voltage device voltage dividing circuit unit 2 includes at least one second MOS transistor M2 coupled between the power supply voltage line VDD and the electrical input of the low-voltage device clamping circuit unit 4, and the gate of each second MOS transistor M2 is coupled to the bias point BP, wherein the control terminal of the low-voltage device voltage dividing circuit unit 2 is the gate of each second MOS transistor M2. In the case where the number of second MOS transistors M2 is one, the electrical input of the second MOS transistor M2 is coupled to the power supply voltage line VDD, and the electrical output of the second MOS transistor M2 is coupled to the low-voltage device clamping circuit unit 4. In the case where the number of second MOS transistors M2 is two, the two second MOS transistors M2 are connected in parallel or in series between the power supply voltage line VDD and the electrical input of the low-voltage device clamping circuit unit 4. In the case where the number of second MOS transistors M2 is more than two, the plurality of second MOS transistors M2 are connected in parallel, in series, or in series-parallel between the power supply voltage line VDD and the electrical input of the low-voltage device clamping circuit unit 4.

[0085] It should be noted that, Figure 3 In the illustrative embodiment, only one second MOS transistor M2 is shown, which can represent one second MOS transistor M2, or two second MOS transistors M2 connected in parallel or in series, or a plurality of second MOS transistors M2 connected in parallel, in series, or in series-parallel.

[0086] As Figure 3 shown in the illustrative embodiment, the second MOS transistor M2 is an NMOS, the electrical input of the second MOS transistor M2 is the drain of the NMOS, and the electrical output of the second MOS transistor M2 is the source of the NMOS. In addition, the second MOS transistor M2 can also be a PMOS, in which case the electrical input of the second MOS transistor M2 is the source of the PMOS, and the electrical output of the second MOS transistor M2 is the drain of the PMOS.

[0087] In the embodiments of the present disclosure, the low-voltage device voltage dividing circuit unit 2 functions as a resistor to divide the voltage of the low-voltage device clamping circuit unit 4, so that the voltage between the power supply voltage line VDD and the reference ground line VSS does not break through the low-voltage device clamping circuit unit 4. Therefore, the second MOS transistor M2 in the low-voltage device voltage dividing circuit unit 2 is in a metastable state under the action of the bias voltage and works in the linear region, realizing its resistance function.

[0088] In the illustrative embodiment, the second MOS transistor M2 is a low-voltage MOS transistor for digital circuit. By using a low-voltage MOS transistor, compared with a high-voltage MOS transistor for analog circuit, the over-current capability is stronger, which helps to discharge the electrostatic current on the side of the low-voltage device voltage dividing circuit unit 2 and the low-voltage device clamping circuit unit 4. Therefore, in general, by using a low-voltage MOS transistor for digital circuit as the second MOS transistor M2, the low-voltage device voltage dividing circuit unit 2 can not only achieve the voltage dividing effect on the low-voltage device clamping circuit unit 4, but also can ensure the over-current capability of the low-voltage device voltage dividing circuit unit 2, realize the effect of discharging the electrostatic current by using a low-voltage MOS transistor without being broken down, and because the over-current capability of the low-voltage device voltage dividing circuit unit 2 is stronger, the current density is higher, which helps to miniaturize the area of the low-voltage device electrostatic discharge protection circuit as a whole and weaken the non-uniform triggering of each low-voltage MOS transistor in the low-voltage device clamping circuit unit 4 during electrostatic discharge.

[0089] For the series form of the second MOS transistor M2, the electrical output end of the front second MOS transistor M2 is connected to the electrical input end of the rear second MOS transistor M2 between the front and rear second MOS transistors M2. For the parallel form of the second MOS transistor M2, the electrical input ends of the parallel second MOS transistors M2 are connected to each other, and the electrical output ends of the parallel second MOS transistors M2 are connected to each other.

[0090] The number and connection form of the second MOS transistor M2 can be determined according to the design requirement, i.e. the size of the voltage division required by the low-voltage device voltage dividing circuit unit 2.

[0091] As shown in Figure 3 In the illustrative embodiment, the RC trigger circuit unit 3 includes a resistor R, a MOS transistor resistance circuit 31, a capacitor C, and an inverter INV. The one end of the resistor R is coupled to the bias point BP. The electrical input end of the MOS transistor resistance circuit 31 is coupled to the other end of the resistor R. The one end of the capacitor C is coupled to the electrical output end of the MOS transistor resistance circuit 31, and the other end of the capacitor C is coupled to the reference ground VSS. The input end of the inverter INV is coupled to the electrical output end of the MOS transistor resistance circuit 31, and the output end of the inverter INV is coupled to the control end of the low-voltage device clamping circuit unit 4.

[0092] Among them, the resistor R, the capacitor C and the inverter INV are the basic form of the RC trigger circuit unit 3, and the functions and principles are the same as those of the electrostatic discharge protection circuit of the related art. The main function of the MOS transistor resistance circuit 31 is to set the bias voltage of the bias point BP in cooperation with the bias circuit unit 1.

[0093] As shown in Figure 3As shown in the illustrative embodiment, the MOS resistor circuit 31 includes at least one third MOS transistor M3, and the gate of each third MOS transistor M3 is coupled to the respective electrical output terminal of the third MOS transistor M3. In the case of one third MOS transistor M3, the electrical input terminal of the third MOS transistor M3 is coupled to the resistor R, and the electrical output terminal of the third MOS transistor M3 is coupled to the capacitor C. In the case of two third MOS transistors M3, the two third MOS transistors M3 are connected in parallel or in series between the resistor R and the capacitor C. In the case of a plurality of third MOS transistors M3, the plurality of third MOS transistors M3 are connected in parallel, in series, or in a series-parallel combination between the resistor R and the capacitor C.

[0094] It should be noted that, Figure 3 The third MOS transistor M3 is only briefly shown in the embodiment, and can represent one third MOS transistor M3, two third MOS transistors M3 connected in parallel or in series, or a plurality of third MOS transistors M3 connected in parallel, in series, or in a series-parallel combination.

[0095] As Figure 3 shown in the illustrative embodiment, the third MOS transistor M3 is an NMOS, and the electrical input terminal of the third MOS transistor M3 is the drain of the NMOS, and the electrical output terminal of the third MOS transistor M3 is the source of the NMOS. In addition, the third MOS transistor M3 can also be a PMOS, and in the case of a PMOS, the electrical input terminal of the third MOS transistor M3 is the source of the PMOS, and the electrical output terminal of the third MOS transistor M3 is the drain of the PMOS.

[0096] In the embodiment, the MOS resistor circuit 31 functions to generate the required bias voltage at the bias point BP in cooperation with the bias circuit unit 1, and the precision fine adjustment of the bias voltage is achieved by changing the number and combination of the first MOS transistors M1 and the number and combination of the third MOS transistors M3. The connection mode of the third MOS transistors M3 enables the third MOS transistors M3 to function as resistors, and compared with conventional resistors, the third MOS transistors M3 have a smaller area, so that the use of the third MOS transistors M3 as resistors helps to ensure the miniaturization of the low-voltage device ESD protection circuit as a whole.

[0097] In the illustrative embodiment, the third MOS transistor M3 can be a high-voltage MOS transistor for analog circuits or a low-voltage MOS transistor for digital circuits as needed. Meanwhile, the resistance values of the high-voltage MOS transistor and the low-voltage MOS transistor are different when used as resistors, so, in order to obtain more accurate bias voltage, when multiple third MOS transistors M3 are included in the MOS transistor resistance circuit 31, the multiple third MOS transistors M3 can also be implemented in a mixed manner of high-voltage MOS transistors and low-voltage MOS transistors, that is, a part of the third MOS transistors M3 are high-voltage MOS transistors and another part of the third MOS transistors M3 are low-voltage MOS transistors.

[0098] For the series form of the third MOS transistor M3, the electrical output end of the former third MOS transistor M3 is connected to the electrical input end of the latter third MOS transistor M3 between the former and the latter third MOS transistors M3. For the parallel form of the third MOS transistor M3, the electrical input ends of the parallel third MOS transistors M3 are connected to each other, and the electrical output ends of the parallel third MOS transistors M3 are connected to each other.

[0099] As shown in FIG. 1, Figure 3 In the illustrative embodiment, the low-voltage device clamping circuit unit 4 includes at least one fourth MOS transistor M4 coupled between the electrical output end of the low-voltage device voltage dividing circuit unit 2 and the reference ground VSS, and the gate of each fourth MOS transistor M4 is coupled to the control output end of the RC trigger circuit unit 3. In the case where the number of the fourth MOS transistors M4 is one, the electrical input end of the fourth MOS transistor M4 is coupled to the electrical output end of the low-voltage device voltage dividing circuit unit 2, and the electrical output end of the fourth MOS transistor M4 is coupled to the reference ground VSS. In the case where the number of the fourth MOS transistors M4 is two, the two fourth MOS transistors M4 are connected in parallel or in series between the electrical output end of the low-voltage device voltage dividing circuit unit 2 and the reference ground VSS. In the case where the number of the fourth MOS transistors M4 is multiple, the multiple fourth MOS transistors M4 are connected in any one of the parallel, series, series-parallel mixed connection manner between the electrical output end of the low-voltage device voltage dividing circuit unit 2 and the reference ground VSS.

[0100] It should be noted that, ​ In the illustrative embodiment, only one fourth MOS transistor M4 is shown, which can represent one fourth MOS transistor M4, or two fourth MOS transistors M4 connected in parallel or in series, or multiple fourth MOS transistors M4 connected in parallel, series, or series-parallel mixed connection manner.

[0101] As shown in FIG. 1, ​As shown, in the illustrative embodiment, the fourth MOS transistor M4 is an NMOS, the electrical input end of the fourth MOS transistor M4 is the drain of the NMOS, and the electrical output end of the fourth MOS transistor M4 is the source of the NMOS. In addition, the fourth MOS transistor M4 can also be a PMOS, in which case the electrical input end of the fourth MOS transistor M4 is the source of the PMOS, and the electrical output end of the fourth MOS transistor M4 is the drain of the PMOS.

[0102] In the embodiments of the present disclosure, the low-voltage device clamping circuit unit 4 is used to discharge the static electricity current when static electricity is generated, and is in a closed state under the action of the inverter INV when working normally, so that the low-voltage device clamping circuit unit 4 plays a switching role in discharging the static electricity current.

[0103] In the illustrative embodiment, the fourth MOS transistor M4 is a low-voltage MOS transistor used in a digital circuit. By using a low-voltage MOS transistor, the overcurrent capacity is stronger than that of a high-voltage MOS transistor used in an analog circuit in the related art, which helps to discharge the static electricity current on the side of the low-voltage device voltage dividing circuit unit 2 and the low-voltage device clamping circuit unit 4. Therefore, in the case of having the same current discharge capacity as the static electricity discharge protection circuit in the related art, the low-voltage device static electricity discharge protection circuit in the embodiments of the present disclosure can have a smaller area and a stronger uniform triggering capability, which can meet the needs of further miniaturization of integrated circuits.

[0104] For the series form of the fourth MOS transistor M4, the electrical output end of the front fourth MOS transistor M4 is connected to the electrical input end of the rear fourth MOS transistor M4 between the front and rear fourth MOS transistors M4. For the parallel form of the fourth MOS transistor M4, the electrical input ends of the parallel fourth MOS transistors M4 are connected to each other, and the electrical output ends of the parallel fourth MOS transistors M4 are connected to each other.

[0105] The number and connection form of the fourth MOS transistor M4 can be determined according to design needs.

[0106] In the embodiments of the present disclosure, the low-voltage device can also be referred to as a low-voltage MOS device, which is mainly used in the digital circuit part inside an integrated circuit compared to a high-voltage device, and thus the low-voltage MOS device can also be referred to as a core device. Compared to an input and output device, the core device has a lower working voltage domain, a larger current density, and a stronger overcurrent capacity, but a relatively weak voltage resistance. Therefore, the embodiments of the present disclosure ensure that the used low-voltage device is not broken down by increasing the low-voltage device voltage dividing circuit unit 2, and further reduce the circuit area.

[0107] In the illustrative embodiment, on the side of the biasing circuit unit 1 and the RC trigger circuit unit 3, because the biasing circuit unit 1 and the MOS transistor resistance circuit 31 share the resistance value of the resistance R in the RC trigger circuit, the resistance R can be made smaller, and on this basis, when performing layout design, the smaller resistance R can be set in the device layer or in the metal layer. When set in the device layer, because the smaller resistance R can save a large amount of space for the layout of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4, and when set in the metal layer, the occupied space of the device layer can be completely saved, thus as a whole, it is helpful to significantly reduce the area of the low-voltage device electrostatic discharge protection circuit.

[0108] Regarding the biasing voltage of the biasing point BP, from the process point of view, the biasing point BP is generated by biasing the MOS device, and in the preparation process, because the plasma environment for preparing the device will simultaneously act on the entire substrate surface, the drift of the threshold voltage of the MOS device involved in the low-voltage device electrostatic discharge protection circuit of the embodiment of the present disclosure as a whole caused by the process will also cause a corresponding drift of the biasing voltage. Therefore, the low-voltage device electrostatic discharge protection circuit of the embodiment of the present disclosure will not be affected by the process to cause the biasing voltage to be unstable, and can always ensure the voltage dividing protection effect of the low-voltage device voltage dividing circuit unit 2 on the low-voltage device clamping circuit unit 4.

[0109] In the illustrative embodiment, according to different designs, the implementation mode of at least one of the biasing circuit unit 1, the low-voltage device voltage dividing circuit unit 2, the RC trigger circuit unit 3, and the low-voltage device clamping circuit unit 4 can be a combination of multiple of hardware, firmware, and software (i.e., programs).

[0110] In hardware form, at least one of the biasing circuit unit 1, the low-voltage device voltage dividing circuit unit 2, the RC trigger circuit unit 3, and the low-voltage device clamping circuit unit 4 can be implemented as logic circuits on an integrated circuit. For example, the functions of at least one of the biasing circuit unit 1, the low-voltage device voltage dividing circuit unit 2, the RC trigger circuit unit 3, and the low-voltage device clamping circuit unit 4 can be implemented as various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The functions of at least one of the biasing circuit unit 1, the low-voltage device voltage dividing circuit unit 2, the RC trigger circuit unit 3, and the low-voltage device clamping circuit unit 4 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

[0111] In software or firmware form, the functions of at least one of the biasing circuit unit 1, the low-voltage device voltage dividing circuit unit 2, the RC trigger circuit unit 3, and the low-voltage device clamping circuit unit 4 can be implemented as programming codes. For example, at least one of the biasing circuit unit 1, the low-voltage device voltage dividing circuit unit 2, the RC trigger circuit unit 3, and the low-voltage device clamping circuit unit 4 is implemented by using a general programming language (such as C, C++, or assembly language) or other suitable programming language. The programming codes can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and / or a storage device. An electronic device (such as a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functions of at least one of the biasing circuit unit 1, the low-voltage device voltage dividing circuit unit 2, the RC trigger circuit unit 3, and the low-voltage device clamping circuit unit 4.

[0112] In illustrative embodiments, the low-voltage device electrostatic discharge protection circuit of the present disclosure is applicable to a SoC chip, etc., where the SoC chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0113] In illustrative embodiments, a chip is also provided, which includes the low-voltage device electrostatic discharge protection circuit as described in any one of the above embodiments.

[0114] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A low voltage device electrostatic discharge protection circuit, comprising: The application relates to a bias circuit unit, a low-voltage device voltage divider circuit unit, an RC trigger circuit unit and a low-voltage device clamping circuit unit. The bias circuit unit is coupled to a power supply voltage line at an electrical input end and coupled to a bias point at an electrical output end. The low-voltage device voltage divider circuit unit is coupled to the power supply voltage line at an electrical input end and coupled to the bias point at a control end. The RC trigger circuit unit is coupled to the bias point at an electrical input end and coupled to a reference ground line at a ground end. The low-voltage device clamping circuit unit is coupled to the electrical output end of the low-voltage device voltage divider circuit unit at an electrical input end, coupled to the reference ground line at an electrical output end and coupled to the control output end of the RC trigger circuit unit at a control end.

2. The low voltage device electrostatic discharge protection circuit of claim 1, wherein, The bias circuit unit comprises at least one first MOS transistor, and the gate of each first MOS transistor is coupled to the electrical output end of the first MOS transistor. When the number of first MOS transistors is one, the electrical input end of the first MOS transistor is coupled to the power supply voltage line, and the electrical output end of the first MOS transistor is coupled to the bias point. When the number of first MOS transistors is two, the two first MOS transistors are connected in parallel or in series between the power supply voltage line and the bias point. When the number of first MOS transistors is more than two, the first MOS transistors are connected in parallel, in series or in series-parallel between the power supply voltage line and the bias point. The first MOS transistor is a high-voltage MOS transistor for an analog circuit or a low-voltage MOS transistor for a digital circuit.

3. The low voltage device electrostatic discharge protection circuit of claim 2, wherein, The low-voltage device voltage divider circuit unit comprises at least one second MOS transistor coupled between the power supply voltage line and the electrical input end of the low-voltage device clamping circuit unit, and the gate of each second MOS transistor is coupled to the bias point.

4. The low voltage device electrostatic discharge protection circuit of claim 1, wherein, When the number of second MOS transistors is one, the electrical input end of the second MOS transistor is coupled to the power supply voltage line, and the electrical output end of the second MOS transistor is coupled to the low-voltage device clamping circuit unit. When the number of second MOS transistors is two, the two second MOS transistors are connected in parallel or in series between the power supply voltage line and the electrical input end of the low-voltage device clamping circuit unit. When the number of second MOS transistors is more than two, the second MOS transistors are connected in parallel, in series or in series-parallel between the power supply voltage line and the electrical input end of the low-voltage device clamping circuit unit. The second MOS transistor is a low-voltage MOS transistor for a digital circuit. The RC trigger circuit unit comprises a resistor coupled to the bias point at one end and a MOS transistor resistor circuit coupled to the other end of the resistor at an electrical input end.

5. The low voltage device electrostatic discharge protection circuit of claim 4, wherein, ​ 6. The low voltage device electrostatic discharge protection circuit of claim 1, wherein, ​ ​ ​ a capacitor, one end of the capacitor is coupled to the electrical output end of the MOS resistor circuit, and the other end of the capacitor is coupled to the reference ground line; an inverter, an input end of the inverter is coupled to the electrical output end of the MOS resistor circuit, and an output end of the inverter is coupled to the control end of the low-voltage device clamping circuit unit.

7. The low voltage device electrostatic discharge protection circuit of claim 6, wherein, The MOS resistor circuit comprises: at least one third MOS transistor, a gate of each of the third MOS transistors is coupled to a respective electrical output end of the third MOS transistor; in the case that the third MOS transistor is one, an electrical input end of the third MOS transistor is coupled to the resistor, and an electrical output end of the third MOS transistor is coupled to the capacitor; in the case that the number of the third MOS transistors is two, the two third MOS transistors are connected in parallel or in series between the resistor and the capacitor; in the case that the number of the third MOS transistors is multiple, the multiple third MOS transistors are connected in parallel, in series, or in series-parallel between the resistor and the capacitor.

8. The low voltage device electrostatic discharge protection circuit of claim 7, wherein, The third MOS transistor is a high-voltage MOS transistor for an analog circuit or a low-voltage MOS transistor for a digital circuit.

9. The low voltage device electrostatic discharge protection circuit of claim 1, wherein, The low-voltage device clamping circuit unit comprises: at least one fourth MOS transistor coupled between the electrical output end of the low-voltage device voltage dividing circuit unit and the reference ground line, a gate of each of the fourth MOS transistors is coupled to the control output end of the RC trigger circuit unit; in the case that the number of the fourth MOS transistors is one, an electrical input end of the fourth MOS transistor is coupled to the electrical output end of the low-voltage device voltage dividing circuit unit, and an electrical output end of the fourth MOS transistor is coupled to the reference ground line; in the case that the number of the fourth MOS transistors is two, the two fourth MOS transistors are connected in parallel or in series between the electrical output end of the low-voltage device voltage dividing circuit unit and the reference ground line; in the case that the number of the fourth MOS transistors is multiple, the multiple fourth MOS transistors are connected in parallel, in series, or in series-parallel between the electrical output end of the low-voltage device voltage dividing circuit unit and the reference ground line.

10. The low voltage device electrostatic discharge protection circuit of claim 9, wherein, The fourth MOS transistor is a low-voltage MOS transistor for a digital circuit.

11. A chip, characterized by The low-voltage device electrostatic discharge protection circuit comprises the low-voltage device electrostatic discharge protection circuit according to any one of claims 1 to 10.

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