Phase-locked loop behavior level model

Abstract

The utility model discloses a phase-locked loop behavioral model, which is used for solving the problems that a behavioral modeling method for a phase-locked loop in the prior art needs more complex digital logic and the model cannot fully reflect digital-analog interface behaviors. The phase-locked loop behavior level model comprises a phase frequency detector (PFD) used for generating an error signal according to phase deviation between a reference clock signal and a feedback clock signal and outputting the error signal to an integral path and a proportional path respectively; the integral path is composed of a first charge pump module, an integrator and a first gain amplifier which are connected in sequence, and is used for adjusting the output frequency of the behavior-level model and outputting a first voltage value to the summator; the proportional path consists of a second charge pump module, a loop filter and a second gain amplifier which are connected in sequence, and is used for adjusting the phase change of the behavior-level model and outputting a second voltage value to the summator; the voltage-controlled oscillator VCO is used for generating a clock signal of a corresponding frequency according to the input voltage value and transmitting the clock signal to the frequency divider; the frequency divider is used for generating the feedback clock signal according to the clock signal and transmitting the feedback clock signal to the PFD.

Description

Technical Field

[0001] This utility model relates to the field of computer technology, and in particular to a phase-locked loop behavioral level model. Background Technology

[0002] With the continuous advancement of semiconductor technology, the integration scale of System-On-Chip (SoC) has grown rapidly in accordance with Moore's Law, and the application of Bipolar CMOS DMOS (BCD) chips has become increasingly widespread.

[0003] To ensure that the designed circuit meets the requirements and reduce the probability of major bugs after chip fabrication, simulation verification has become an important part of circuit design. Here, simulation verification generally refers to compiling the logic system design and then running it with simulation tools to simulate and test the various functions of the design.

[0004] In chip design, it is often necessary to perform mixed-signal simulation of analog and digital circuits. Analog circuits are used to transmit, transform, amplify, process, measure, and display analog quantities, while digital circuits are used to perform arithmetic and logical operations on digital quantities using digital signals. Since the simulation principles of analog and digital circuits are fundamentally different, it is necessary to digitally model the analog circuit to obtain a digital model of the analog circuit. This digital model is then used together with the digital circuit in a mixed-signal simulation verification using a digital simulator.

[0005] Generally, conventional analog circuits can have their netlists extracted directly from the circuit schematic as digital models. However, some analog circuits, such as phase-locked loops (PLLs), have high nonlinearity and logic loops, making it impossible to extract digital models directly from the circuit schematic for use in digital simulators. In such cases, behavioral-level modeling of the analog circuit is often required.

[0006] However, in the existing technology, there is no unified standard for behavioral modeling methods. Therefore, how to use limited digital logic to build a behavioral model that can fully reflect the behavior of the digital-analog interface has become a technical problem that urgently needs to be solved in the field of mixed-signal chip simulation and verification. Utility Model Content

[0007] This invention provides a phase-locked loop (PLL) behavioral-level model to address the problem that existing PLL behavioral-level modeling methods require complex digital logic and the models cannot fully reflect the behavior of the digital-analog interface.

[0008] The present invention adopts the following technical solution:

[0009] A phase-locked loop (PLL) behavioral-level model includes: a frequency and phase detector (PFD), which is connected to a frequency divider, an integrator, and a proportional path, respectively, for generating an error signal based on the phase offset between a reference clock signal and a feedback clock signal, and outputting the error signal to the integrator and the proportional path, respectively; the integrator consists of a first charge pump module, an integrator, and a first gain amplifier connected in sequence, and is connected to the PFD and an adder, for adjusting the output frequency of the PLL simulation model and outputting a first voltage value to the adder; the proportional path consists of a second charge pump module, a loop filter, and a second gain amplifier connected in sequence, and the integrator is connected to the PFD. The PFD and the adder are connected to adjust the phase change of the phase-locked loop simulation model and output the second voltage value to the adder. The adder is connected to the integral path, the proportional path, and the voltage-controlled oscillator (VCO) to generate an input voltage value based on the first and second voltage values ​​and transmit the input voltage value to the VCO. The VCO is connected to the adder and the frequency divider to generate a clock signal of the corresponding frequency based on the input voltage value and transmit the clock signal to the frequency divider. The frequency divider is connected to the phase-frequency detector (PFD) to generate the feedback clock signal based on the clock signal and transmit the feedback clock signal to the PFD.

[0010] Optionally, a frequency and phase detector (PFD) is used to generate the error signal by setting the Up signal when the phase of the reference clock signal leads the feedback clock signal, and by setting the Dn signal when the phase of the feedback clock signal leads the reference clock signal.

[0011] Optionally, the integration path uses an integrator to integrate the first voltage value using a digital high-frequency counter.

[0012] Optionally, the integrator is used to obtain the first voltage value by forward integration when the Up signal is 1 and the Dn signal is 0; and to obtain the first voltage value by reverse integration when the Dn signal is 1 and the Up signal is 0.

[0013] Optionally, the proportional path is configured to linearly generate the second voltage value with a fixed gain.

[0014] Optionally, the proportional path is used to generate a second voltage value with positive voltage gain when the Up signal is 1 and the Dn signal is 0; and to generate a second voltage value with negative voltage gain when the Dn signal is 1 and the Up signal is 0.

[0015] Optionally, the voltage-controlled oscillator (VCO) is used to generate a clock signal with a frequency corresponding to the input voltage value based on the integral path voltage gain, the proportional path voltage gain, the highest frequency of the VCO output clock, the lowest frequency of the VCO output clock, the first voltage value, and the second voltage value obtained from simulation.

[0016] The above-mentioned technical solution adopted by this utility model can achieve the following beneficial effects:

[0017] The phase-locked loop (PLL) behavioral-level model provided by this utility model includes: a frequency and phase detector (PFD), which is connected to a frequency divider, an integrator, and a proportional amplifier, and is used to generate an error signal based on the phase offset between the reference clock signal and the feedback clock signal, and output the error signal to the integrator and proportional amplifier respectively; an integrator consisting of a first charge pump module, an integrator, and a first gain amplifier connected in sequence, which is connected to the PFD and an adder, and is used to adjust the output frequency of the PLL simulation model and output a first voltage value to the adder; and a proportional amplifier consisting of a second charge pump module, a loop filter, and a second gain amplifier connected in sequence, which is used to adjust the output frequency of the PLL simulation model and output a first voltage value to the adder; and a proportional amplifier consisting of a second charge pump module, a loop filter, and a second gain amplifier connected in sequence. The example path is connected to the phase-frequency detector (PFD) and the adder, respectively, to adjust the phase change of the phase-locked loop simulation model and output the second voltage value to the adder; the adder is connected to the integral path, the proportional path, and the voltage-controlled oscillator (VCO), respectively, to generate an input voltage value based on the first voltage value and the second voltage value, and transmit the input voltage value to the VCO; the VCO is connected to the adder and the frequency divider, respectively, to generate a clock signal of the corresponding frequency based on the input voltage value, and transmit the clock signal to the frequency divider; the frequency divider is connected to the phase-frequency detector (PFD), to generate a feedback clock signal based on the clock signal, and transmit the feedback clock signal to the phase-frequency detector (PFD). The phase-locked loop (PLL) behavioral-level model provided by this invention distinguishes between the integral and proportional paths in the PLL loop, making it more consistent with the actual circuit behavior and improving the accuracy of the model simulation. Furthermore, during modeling, the PLL behavioral-level model can be fitted with simulation results from simulation tools, effectively utilizing the advantages of simulation tools for parasitic parameters and device nonlinearity simulation. This results in a high degree of matching between the model behavior and the analog circuit, improving verification coverage. Finally, the PLL behavioral-level model provided by this invention is implemented in a digital logic-friendly manner, optimizing the complexity of most circuits, significantly saving simulation time, and greatly improving the efficiency of chip simulation verification. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 A schematic diagram of the overall structure of a phase-locked loop behavioral level model provided by this utility model;

[0020] Figure 2 A schematic diagram of the specific circuit structure of a frequency and phase detector (PFD) provided by this utility model;

[0021] Figure 3 A simulation waveform diagram generated by the frequency and phase detector PFD provided by this utility model;

[0022] Figure 4 A simulation waveform diagram of an integration path provided by this utility model;

[0023] Figure 5 The present invention provides an integral path voltage value V. INT Simulation waveform diagram;

[0024] Figure 6 A STEP provided by this utility model INT and the frequency of the voltage-controlled oscillator (VCO) output clock (F) VCO A proportional diagram;

[0025] Figure 7 The proportional path voltage value V provided by this utility model PROP Simulation waveform diagram;

[0026] Figure 8 The present invention provides a V signal generated within a continuous period of Up / Dn signal. PROP Simulation waveform diagram;

[0027] Figure 9 A schematic diagram of the specific structure of an FFT circuit data system provided by this utility model. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The technical solution provided by this utility model will be described in detail below with reference to the accompanying drawings.

[0030] The overall structure of the phase-locked loop behavioral level model provided by this utility model is as follows: Figure 1 As shown, the phase-locked loop behavioral-level model mainly consists of a phase frequency detector (PFD), an integral path, a proportional path, an adder, a voltage-controlled oscillator (VCO), and dividers (DIV).

[0031] The frequency and phase detector (PFD) is connected to the frequency divider (DIV), the integration path, and the proportional path, respectively. It is used to generate an error signal based on the phase offset between the reference clock signal and the feedback clock signal, and output the error signal to the integration path and the proportional path, respectively.

[0032] In this embodiment, the phase-frequency detector (PFD) can be implemented using digital logic, and its specific circuit structure is as follows: Figure 2 As shown, the Up signal is set when the phase of the reference clock signal (RefClk) leads the feedback clock signal (FbClk) obtained by dividing the current voltage-controlled oscillator (VCO) clock signal by the DIV divider. The Dn signal is set when the phase of FbClk leads RefClk. It should be noted that in a phase-locked loop (PLL), the Dn signal typically works in conjunction with the Up signal as the output of the phase-frequency discriminator (PFD), indicating the PLL's lock-in state and phase difference.

[0033] In this embodiment, the phase difference between the specific reference clock signal RefClk and the feedback clock signal FbClk can be represented by the pulse widths of the Up and Dn signals, such as... Figure 3 As shown.

[0034] In this embodiment, the Integral Path can be composed of a first charge pump module, an integrator, and a first gain amplifier connected in sequence. The Integral Path is connected to a frequency and phase detector (PFD) and an adder, respectively, to adjust the output frequency of the behavioral-level model and output the first voltage value to the adder.

[0035] In one implementation, the integration path voltage V can be achieved using an integrator and a digital high-frequency counter. INT Specifically, such as Figure 4As shown, when the Up signal is 1 and the Dn signal is 0, positive integration can be performed through the integrator; while when the Dn signal is 1 and the Up signal is 0, negative integration can be performed through the integrator.

[0036] In one implementation, when the digital high-frequency counter uses a frequency (F... SMPL ) is a 10GHz high-frequency clock (CLK) SMPL When integrating through an integrator, the pair is... Figure 4 The integrated path voltage value V obtained by processing the selected area is shown below. INT like Figure 5 As shown, STEP INT Represents each high-frequency clock (CLK) SMPL () Integral step of the cycle.

[0037] In this embodiment, the highest frequency (F) of the voltage-controlled oscillator (VCO) output clock can be simulated using Analog simulation tools. MAX ) and the lowest frequency (F MIN Through model processing, the frequency (F) of the voltage-controlled oscillator (VCO) output clock can be obtained. VCO ) and integral step STEP INT Proportional relationships, such as Figure 6 As shown, STEP MAX and STEP MIN These represent the integral step size corresponding to the highest / lowest frequency of the VCO output clock, respectively. Figure 6 It can be seen that STEP INT and the frequency of the voltage-controlled oscillator (VCO) output clock (F) VCO The relationship is directly proportional. After fitting the curve, the following formula can be obtained [1]. Then, each high-frequency clock (CLK) can be calculated using the following formula [1]. SMPL Integral steps within a period:

[0038] [1]

[0039] In this embodiment, the proportional path can consist of a second charge pump module, a loop filter, and a second gain amplifier connected in sequence. The proportional path is connected to the phase detector (PFD) and the adder, respectively, to adjust the phase change of the behavioral model and output the second voltage value to the adder.

[0040] In one implementation, the proportional path is configured to linearly generate a second voltage value V with a fixed gain. PROPSpecifically, such as Figure 7 As shown, when the Up signal is 1 and the Dn signal is 0, a second voltage value for the positive voltage gain is generated, namely V. PROP For "+GAIN" PROP When the Dn signal is 1 and the Up signal is 0, a second voltage value with negative voltage gain is generated, namely V. PROP For "-GAIN" PROP ".

[0041] In one implementation, it can be Figure 7 The selected duration T SMPL (CLK) SMPL The V generated within the Up signal / Dn signal (period) PROP Represented as Figure 8 ,like Figure 8 As shown, V can be seen PROP The pulse width will not be entirely concentrated within the pulses of the Up and Dn signals, but will instead persist for a period of time with a relatively small amplitude. Therefore, we use a pulse width of FILT. PROP *T SMPL The amplitude is GAIN PROP / FILT PROP pulse to V PROP V-shape obtained through plastic surgery PROP_SHAPING .

[0042] In this embodiment, the adder is connected to the integral path, the proportional path, and the voltage-controlled oscillator (VCO) respectively, and is used to generate an input voltage value based on a first voltage value and a second voltage value, and transmit the input voltage value to the VCO.

[0043] In this embodiment, the voltage-controlled oscillator (VCO) is connected to an adder and a frequency divider, respectively, to generate a clock signal of the corresponding frequency according to the input voltage value, and transmit the clock signal to the frequency divider. It should be noted that, ideally, the frequency of the output clock of the VCO can be in one-to-one correspondence with the input voltage, so the VCO can be simulated directly in the form of a lookup table during the modeling process. In this embodiment, the control voltage (V) can be determined by the following formula [2]. CTL ):

[0044] [2]

[0045] V can be obtained through simulation using simulation tools. CTL The relationship between the voltage-controlled oscillator (VCO) output clock frequency and the frequency of the voltage-controlled oscillator (VCO), such as Figure 9 As shown, by Figure 9 It can be known that V CTLThe frequency of the output clock of the voltage-controlled oscillator (VCO) is directly proportional to the frequency of the VCO output clock. Therefore, the frequency of the VCO output clock (F) can be determined by the following formula [3] [4]. VCO ):

[0046] [3]

[0047] In this embodiment of the application, K can be determined by the following formulas [4] and [5], respectively. CTL and F C :

[0048] [4]

[0049] [5]

[0050] Among them, K INT and K PROP V represents the voltage gain of the integral path and the voltage gain of the proportional path, respectively, obtained through simulation using a simulation tool (e.g., Analog). CTL_MAX and V CTL_MIN The voltage-controlled oscillator (VCO) output clock frequency reaches its maximum frequency (F). MAX ) and the lowest frequency (F MIN V corresponding to ) CTL value.

[0051] In summary, based on the phase-locked loop simulation modeling method provided in the embodiments of this application, the parameters that need to be defined during modeling are shown in Table 1 below. Among them, some modeling parameters need to be obtained through simulation tools.

[0052] Table 1. Simulation Modeling Parameters for Phase-Locked Loops

[0053]

[0054] After modeling the aforementioned sub-modules, a complete behavioral-level model can be obtained by cascading the modules. This behavioral-level model can then be used for digital simulation to model the process of a phase-locked loop (PLL) starting up, stabilizing, and even subsequently enabling spread-spectrum clocking (SSC). In this embodiment, the parameter F can be adjusted... SMPL Parameters and FILT PROP Modifying parameters allows for fine-tuning of the model's simulation accuracy and time.

[0055] In one implementation, by adjusting F SMPLThe impact of parameters on the simulation accuracy and simulation time of the model is shown in Table 2 below. The ideal clock model refers to providing a standard 1.2 GHz clock.

[0056] Table 2F SMPL The influence of parameters on the model

[0057]

[0058] In one implementation, by adjusting FILT PROP The effects of parameters on the simulation accuracy and simulation time of the model are shown in Table 3 below:

[0059] Table 3 FILT PROP The influence of parameters on the model

[0060]

[0061] As shown in Tables 2 and 3, compared to the ideal clock model, the modeling method provided in this application embodiment can achieve a high degree of matching with the analog circuit at the cost of minimal simulation time, and the accuracy can be improved by adjusting F. SMPL and FILT PORP This allows for the adjustment and control of simulation time and simulation accuracy.

[0062] The phase-locked loop (PLL) behavioral-level model provided by this utility model includes: a frequency and phase detector (PFD), which is connected to a frequency divider, an integrator, and a proportional amplifier, and is used to generate an error signal based on the phase offset between the reference clock signal and the feedback clock signal, and output the error signal to the integrator and proportional amplifier respectively; an integrator consisting of a first charge pump module, an integrator, and a first gain amplifier connected in sequence, which is connected to the PFD and an adder, and is used to adjust the output frequency of the PLL simulation model and output a first voltage value to the adder; and a proportional amplifier consisting of a second charge pump module, a loop filter, and a second gain amplifier connected in sequence, which is used to adjust the output frequency of the PLL simulation model and output a first voltage value to the adder; and a proportional amplifier consisting of a second charge pump module, a loop filter, and a second gain amplifier connected in sequence. The example path is connected to the phase-frequency detector (PFD) and the adder, respectively, to adjust the phase change of the phase-locked loop simulation model and output the second voltage value to the adder; the adder is connected to the integral path, the proportional path, and the voltage-controlled oscillator (VCO), respectively, to generate an input voltage value based on the first voltage value and the second voltage value, and transmit the input voltage value to the VCO; the VCO is connected to the adder and the frequency divider, respectively, to generate a clock signal of the corresponding frequency based on the input voltage value, and transmit the clock signal to the frequency divider; the frequency divider is connected to the phase-frequency detector (PFD), to generate a feedback clock signal based on the clock signal, and transmit the feedback clock signal to the phase-frequency detector (PFD). The phase-locked loop (PLL) behavioral-level model provided by this invention distinguishes between the integral and proportional paths in the PLL loop, making it more consistent with the actual circuit behavior and improving the accuracy of the model simulation. Furthermore, the PLL behavioral-level model provided by this invention can be fitted with simulation results from simulation tools during modeling, effectively utilizing the advantages of simulation tools for parasitic parameters and device nonlinearity simulation. This results in a high degree of matching between the model behavior and the analog circuit, improving verification coverage. Finally, the PLL behavioral-level model provided by this invention is mainly implemented using a digital logic-friendly approach, optimizing the complexity of most circuits, significantly saving simulation time, and greatly improving the efficiency of chip simulation verification.

[0063] All the devices (parts whose specific structures are not specified) selected in this application are general standard parts or parts known to those skilled in the art. Their structures and principles can be learned by those skilled in the art through technical manuals or conventional experimental methods.

[0064] In the description of the embodiments of this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0065] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0067] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] In addition, in the various embodiments of this utility model, each functional unit can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0069] Based on the above-described preferred embodiments of this utility model, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification; any modifications, equivalent substitutions, or improvements made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A phase-locked loop behavioral level model, characterized by, The frequency discriminator PFD is connected with a frequency divider, an integral channel and a proportional channel respectively, and is used for generating an error signal according to a phase offset between a reference clock signal and a feedback clock signal, and outputting the error signal to the integral channel and the proportional channel respectively. The integral channel is composed of a first charge pump module, an integrator and a first gain amplifier connected in sequence, and is connected with the frequency discriminator PFD and an adder respectively, and is used for adjusting an output frequency of the behavioral level model and outputting a first voltage value to the adder. The proportional channel is composed of a second charge pump module, a loop filter and a second gain amplifier connected in sequence, and is connected with the frequency discriminator PFD and the adder respectively, and is used for adjusting a phase change of the behavioral level model and outputting a second voltage value to the adder. The adder is connected with the integral channel, the proportional channel and a voltage-controlled oscillator VCO respectively, and is used for generating an input voltage value according to the first voltage value and the second voltage value, and transmitting the input voltage value to the voltage-controlled oscillator VCO. The voltage-controlled oscillator VCO is connected with the adder and the frequency divider respectively, and is used for generating a clock signal of a corresponding frequency according to the input voltage value, and transmitting the clock signal to the frequency divider. The frequency divider is connected with the frequency discriminator PFD, and is used for generating the feedback clock signal according to the clock signal, and transmitting the feedback clock signal to the frequency discriminator PFD. The frequency discriminator PFD is used for generating the error signal by setting an Up signal when a phase of the reference clock signal leads a phase of the feedback clock signal.

2. The phase-locked loop behavior level model of claim 1, wherein, The frequency discriminator PFD is used for generating the error signal by setting a Dn signal when the phase of the feedback clock signal leads the phase of the reference clock signal. The integral channel obtains the first voltage value by integral of a digital high-frequency counter through the integrator.

3. The phase-locked loop behavior level model of claim 1, wherein, The integrator is used for obtaining the first voltage value by forward integral when the Up signal is 1 and the Dn signal is 0.

4. The phase-locked loop behavior level model of claim 3, wherein, The integrator is used for obtaining the first voltage value by reverse integral when the Dn signal is 1 and the Up signal is 0. The proportional channel is configured to generate the second voltage value according to a fixed gain linearly.

5. The phase-locked loop behavior level model of claim 1, wherein, The proportional channel is used for generating the second voltage value of a positive voltage gain when the Up signal is 1 and the Dn signal is 0.

6. The phase-locked loop behavior level model of claim 5, wherein, The proportional channel is used for generating the second voltage value of a negative voltage gain when the Dn signal is 1 and the Up signal is 0. The voltage-controlled oscillator VCO is used for generating the clock signal of the corresponding frequency of the input voltage value according to an integral channel voltage gain, a proportional channel voltage gain, a highest frequency of a voltage-controlled oscillator VCO output clock, a lowest frequency of the voltage-controlled oscillator VCO output clock, the first voltage value and the second voltage value obtained by analog simulation.

7. The phase-locked loop behavior level model of claim 1, wherein, ​

Images