Signal converter and signal conversion system

Abstract

The embodiment of the utility model discloses a signal converter and a signal conversion system. The signal converter includes a receiver, a field programmable gate array, and a transmitter. The field programmable gate array comprises an input interface, a first output interface and a second output interface. The receiver is used for receiving a first DP signal from a DP signal source and converting the first DP signal into a first signal in a first preset format; the field programmable gate array is used for acquiring a first signal based on the input interface; generating a second signal in a second predetermined format based on the first signal; transmitting the second signal to the transmitter based on the first output interface; converting the first signal into a third signal matched with the signal format of the output end; sending the third signal to the output end based on the second output interface; and the transmitter is used for converting the second signal into a second DP signal and transmitting the second DP signal to the loopback end. The processing speed of the DP signal is improved, and the processing time is shortened.

Description

TECHNICAL FIELD

[0001] The utility model relates to signal processing technical field, especially signal converter and signal conversion system. BACKGROUND

[0002] DP (DisplayPort) is a kind of high-definition digital display interface standard, can transmit high-quality audio signal and / or video signal.The main features of DP signal include high bandwidth, support multi-stream transmission, low delay and good compatibility.Compared with traditional high-definition multimedia interface (High Definition Multimedia Interface, HDMI), DP interface has significant advantages in bandwidth and transmission quality, can support higher resolution and refresh rate, is suitable for high-end display equipment.

[0003] In the video conversion scene, DP signal often has loopback (also known as loop output) requirement.That is, while converting the received DP signal into a one-way output signal matching the supported format of display device, it is also necessary to output the received DP signal in another way.At present, loopback is generally realized by splitter.However, this processing method has the disadvantage of slow processing speed. SUMMARY

[0004] The utility model embodiment proposes signal converter and signal conversion system, to improve processing speed.

[0005] A kind of signal converter, including receiver, Field Programmable GateArray (FPGA) and transmitter;The receiver is coupled with DP signal source, the FPGA includes input interface, first output interface and second output interface, the input interface is coupled with the receiver, the first output interface is coupled with the transmitter, the second output interface and output end are coupled, the transmitter is coupled with loopback end;Wherein: the receiver is used to receive first DP signal from the DP signal source, the first DP signal is converted into the first signal of first predetermined format;The FPGA is used to obtain the first signal based on the input interface;Second signal of second predetermined format is generated based on the first signal;The second signal is sent to the transmitter based on the first output interface;The first signal is converted into the third signal compatible with the signal format of the output end;The third signal is sent to the output end based on the second output interface;The transmitter is used to convert the second signal into second DP signal, and the second DP signal is sent to the loopback end.

[0006] Therefore, the signal loopback is realized by the signal converter with the novel structure comprising the receiver, the transmitter and the FPGA, the number of link training is reduced, the processing speed is improved, and the delay time is reduced.

[0007] In one embodiment, the second predetermined format is the same format as the first predetermined format.

[0008] The FPGA comprises a first circuit between the input interface and the first output interface, and the first circuit is configured to copy the first signal to generate the second signal.

[0009] Therefore, in the embodiment of the utility model, when the second predetermined format is the same format as the first predetermined format, the FPGA directly performs the copy processing on the first signal based on the built-in first circuit to generate the second signal, further speeds up the processing speed, and reduces the complexity.

[0010] In one embodiment, the second predetermined format is not the same format as the first predetermined format.

[0011] The FPGA comprises a first circuit between the input interface and the first output interface, and the first circuit is configured to convert the format of the first signal to the second signal.

[0012] Therefore, in the embodiment of the utility model, when the second predetermined format is not the same format as the first predetermined format, the FPGA performs the format conversion on the first signal based on the built-in first circuit to convert the first signal to the second signal with the second predetermined format, and the transmitter is facilitated to perform the format conversion on the second signal to output the loopback DP signal.

[0013] In one embodiment, the FPGA comprises a second circuit between the input interface and the second output interface, and the second circuit is configured to convert the first signal to the third signal.

[0014] Therefore, in the embodiment of the utility model, the FPGA can conveniently convert the first signal to the third signal based on the built-in second circuit.

[0015] A signal conversion system comprises:

[0016] A DP signal source;

[0017] A signal converter;

[0018] An output end;

[0019] A loopback end;

[0020] The signal converter comprises a receiver, an FPGA and a transmitter; the receiver is coupled with the DP signal source; the FPGA comprises an input interface, a first output interface and a second output interface; the input interface is coupled with the receiver; the first output interface is coupled with the transmitter; the second output interface is coupled with the output end; the transmitter is coupled with the loopback end; wherein: the receiver is configured to receive a first DP signal from the DP signal source and convert the first DP signal into a first signal in a first predetermined format; the FPGA is configured to acquire the first signal based on the input interface, generate a second signal in a second predetermined format based on the first signal, send the second signal to the transmitter based on the first output interface, convert the first signal into a third signal compatible with the signal format of the output end, and send the third signal to the output end based on the second output interface; and the transmitter is configured to convert the second signal into a second DP signal and send the second DP signal to the loopback end.

[0021] Therefore, the signal loopback is realized by the signal converter with a novel structure comprising a receiver, a transmitter and an FPGA without using a separator, the number of link training can be reduced, the processing speed is improved, and the delay time is reduced.

[0022] In one embodiment, the second predetermined format is the same as the first predetermined format.

[0023] The FPGA comprises a first circuit between the input interface and the first output interface; the first circuit is configured to copy the first signal to generate the second signal.

[0024] Therefore, in the embodiment of the utility model, when the second predetermined format is the same as the first predetermined format, the FPGA directly performs the copy processing on the first signal based on the built-in first circuit to generate the second signal, the processing speed is further improved, and the complexity is reduced.

[0025] In one embodiment, the second predetermined format is different from the first predetermined format.

[0026] The FPGA comprises a first circuit between the input interface and the first output interface; the first circuit is configured to convert the first signal format into the second signal.

[0027] Therefore, in the embodiment of the present application, when the second predetermined format is different from the first predetermined format, the FPGA performs format conversion on the first signal based on the built-in first circuit to convert the first signal into a second signal with the second predetermined format, so that the transmitter can further perform format conversion on the second signal to output the loopback DP signal.

[0028] In one embodiment, the FPGA comprises a second circuit between the input interface and the second output interface; the second circuit is configured to convert the first signal into the third signal.

[0029] Therefore, in the embodiment of the present application, the FPGA can conveniently convert the first signal into the third signal based on the built-in second circuit.

[0030] In one embodiment, the signal conversion system is connected with a medical imaging system, wherein the DP signal source is from the medical imaging system.

[0031] Therefore, the signal converter of the embodiment of the present application can be applied to the medical imaging scene requiring high-quality video display.

[0032] In one embodiment, the medical imaging system comprises a Computed Tomography (CT) system, an X-ray photography system, a magnetic resonance imaging system, an ultrasound system or an endoscope imaging system.

[0033] Therefore, the medical imaging system can be implemented in various types and has wide applicability. BRIEF DESCRIPTION OF DRAWINGS

[0034] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that the above and other features and advantages of the present application can be more clearly understood by those skilled in the art. In the drawings:

[0035] Figure 1 is an exemplary structural diagram of a signal converter in the prior art.

[0036] Figure 2 is an exemplary structural diagram of a signal converter according to the embodiment of the present application.

[0037] Figure 3 is a first exemplary structural diagram of a signal converter according to the embodiment of the present application.

[0038] Figure 4 is a second exemplary structural diagram of a signal converter according to the embodiment of the present application.

[0039] Figure 5is a demonstrative structural diagram of a signal conversion system of a medical image system according to the embodiment of the present utility model.

[0040] In the drawings, the reference signs are as follows:

[0041]

[0042] DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the present utility model more clear, the following examples further explain the present utility model in detail. The nouns and pronouns about people in the present patent application are not limited to specific gender.

[0044] In order to describe concisely and intuitively, the following describes the scheme of the present utility model by describing several representative embodiments. A large number of details in the embodiments are only used to help understand the scheme of the present utility model. However, it is obvious that the technical scheme of the present utility model can not be limited to these details. In order to avoid unnecessary obscuring of the scheme of the present utility model, some embodiments are not described in detail, but only a framework is given. In the following, “comprising” means “comprising but not limited to”, and “according to” means “at least according to, but not limited to only according to”. Due to the language habit of Chinese, when the quantity of a component is not specifically indicated in the following, it means that the component can be one or multiple, or can be understood as at least one.

[0045] Video loopback is a signal transmission technology mainly used to ensure that video signals are transmitted without loss during transmission. It transmits the input video signal directly to the output port through the loopback output port (which can be called loopback port), ensuring the integrity and stability of the video signal. Video loopback can be used in troubleshooting applications to facilitate the detection and debugging of video signals, thereby ensuring that there is no attenuation or distortion of the video signal during transmission. Video loopback has applications in a variety of scenarios, especially in situations that require high-precision signal transmission. For example, in the fields of broadcast television, monitoring systems and video conferencing. Moreover, in situations that require high-quality video display such as educational demonstrations and medical imaging, video loopback also plays an important role. For example, in the video conversion scenario of DP signals, there is often a need for video loopback. That is, while converting the received DP signal into a format supported by the display device, the DP signal also needs to be output in another branch.

[0046] Currently, the loopback of DP signals is generally realized by a splitter. However, this processing method has the disadvantage of slow processing speed. Figure 1 is a demonstrative structural diagram of a signal converter in the prior art. In the prior art, the signal converter is used to convert the received DP signal into a format supported by the display device. Figure 1In this circuit, the signal converter includes a splitter 12, a receiver 13, an FPGA 14, an output terminal 15, and a loopback terminal 16.

[0047] Splitter 12 receives DP signals from DP signal source 11 coupled to a signal converter, whereby the DP signals may carry audio and / or video, etc. Splitter 12 performs a copying process on the received DP signals, resulting in two DP signals (referred to as the first DP signal and the second DP signal). Splitter 12 transmits the first DP signal to receiver 13 and the second DP signal to loopback terminal 16. At loopback terminal 16, various applications such as troubleshooting can be performed on the second DP signal to ensure stable transmission of the DP signals provided by DP signal source 11.

[0048] Receiver 13 converts the first DP signal into a predetermined video format (e.g., RGBHV) and then sends the converted signal to FPGA 14. FPGA 14 converts the format of the converted signal provided by receiver 13 to be compatible with the signal format of output terminal 15. Therefore, at output terminal 15, the signal converted from the first DP signal and compatible with the signal format of output terminal 15 can be visually displayed (e.g., output terminal 15 is implemented as a display device). For example, when output terminal 15 is implemented as a DVI display device, FPGA 14 converts the signal converted by receiver 13 to DVI format; when output terminal 15 is implemented as an HDMI display device, FPGA 14 converts the signal converted by receiver 13 to HDMI format, and so on.

[0049] exist Figure 1 In the signal converter shown, splitter 12 needs to perform multiple link training processes. Link training is used to determine the rates and related configurations of both parties through a handshake and interaction process before normal communication between the devices, ensuring that signals can be transmitted reliably and correctly in the complex physical link. The main purpose of link training is to ensure that the receiver can reliably and correctly receive the sender's signal in the physical link, thereby improving signal integrity and compatibility.

[0050] For example, the basic process of link training generally includes: (1) hot plug detection: when hot plugging, the sender accesses the DisplayPort Configuration Data (DPCD) register block of the receiver through an auxiliary (AUX) channel. (2) Link configuration: the sender reads the DPCD function field in the DPCD register block, determines the requirements of the receiver, and writes the link configuration field to configure the link bandwidth and the number of channels. (3) Training mode selection: the sender selects a training mode and sends a training mode signal through the main link; for example, the training mode signal can be used to lock the clock recovery circuit, or to set equalization, determine the symbol boundary, and achieve inter-channel alignment, etc. (4) State monitoring and adjustment: during the training process, the sender regularly reads the link state and makes adjustments as needed, wherein if the clock recovery fails, the sender checks the link driver settings and responds accordingly.

[0051] The above exemplary describes the basic process of link training, and those skilled in the art can realize that this description is only exemplary.

[0052] Specifically: in the process that the splitter 12 receives the DP signal from the DP signal source 11, the splitter 12 needs to perform a first link training process with the DP signal source 11. In the process that the splitter 12 transmits the first DP signal to the receiver 13, the splitter 12 needs to perform a second link training process with the receiver 13. In the process that the splitter 12 transmits the second DP signal to the loopback end 16, the splitter 12 needs to perform a third link training process with the loopback end 16.

[0053] It can be seen that the splitter 12 needs to perform three link training processes, so the signal processing speed is slow, and usually requires a delay of more than 3 seconds.

[0054] In view of the slow processing speed and long delay time caused by the need to perform multiple link training processes in the prior art signal conversion process with loopback through a splitter, the embodiments of the present application do not use a splitter, but a novel signal converter that only needs a small number of link training processes, to improve the signal processing speed and reduce the delay time.

[0055] The above disclosure details the technical defects in the related art, the causes of the technical defects, and the thinking and analysis process of overcoming the technical defects. In fact, the understanding of the above technical defects is not common knowledge in the art, but a novel discovery of the applicant in research. In addition, the cause of the technical defects and the thinking and analysis process of overcoming the technical defects are also the results of the applicant's gradual analysis in the actual research process, and are not common knowledge in the art.

[0056] Figure 2 is an exemplary block diagram of a signal converter according to embodiments of the present application. As shown in Figure 2 the signal converter 20 includes a receiver 21, an FPGA 23 and a transmitter 22. The receiver 21 is coupled with a DP signal source 24, the FPGA 23 is coupled with the receiver 21, the transmitter 22 and an output terminal 26 respectively, and the transmitter 22 is coupled with a loopback terminal 25. The FPGA 23 includes an input interface 231, a first output interface 232 and a second output interface 233, wherein the input interface 231 is coupled with the receiver 21, the first output interface 232 is coupled with the transmitter 22, and the second output interface 233 is coupled with the output terminal 26.

[0057] The receiver 21 can receive a first DP signal from the DP signal source 24. The first DP signal can carry audio and / or video, etc. The receiver 21 converts the first DP signal into a first signal in a first predetermined format. The receiver 21 sends the first signal to the input interface 231 of the FPGA 23. For example, the receiver 21 can be implemented as a DP Rx chip.

[0058] The FPGA 23 obtains the first signal from the receiver 21 based on the input interface 231. The FPGA 23 converts the first signal into a third signal which is adapted to the signal format of the output terminal 26. The FPGA 23 sends the third signal to the output terminal 26 based on the second output interface 233. For example, when the output terminal 26 is implemented as a DVI display device, the FPGA 23 converts the first signal into a DVI format; when the output terminal 26 is implemented as an HDMI display device, the FPGA 23 converts the first signal into an HDMI format, etc. Therefore, the third signal can be displayed in the output terminal 26.

[0059] Moreover, the FPGA 23 generates a second signal in a second predetermined format based on the first signal. The FPGA 23 sends the second signal to the transmitter 22 based on the first output interface 232. The transmitter 22 converts the second signal into a second DP signal and sends the second DP signal to the loopback terminal 25, thereby realizing loopback of the DP signal provided by the DP signal source 24. For example, the transmitter 21 can be implemented as a DP Tx chip.

[0060] For example, the DP Rx chip and the DP Tx chip can include: (1) a chip supporting DisplayPort 1.4 Rx PHY and controller of T2M-IP; (2) a chip supporting DisplayPort 1.4; (3) a chip supporting DisplayPort 2.1, etc.

[0061] At the loopback end 25, troubleshooting and other applications can be performed on the second DP signal, thereby ensuring stable transmission of the DP signal provided by the DP signal source 24.

[0062] Therefore, the signal loopback is realized by the signal converter with the novel structure comprising the receiver, the transmitter and the FPGA without using the splitter, the number of link training can be reduced, the processing speed is improved, and the delay time is reduced.

[0063] In one embodiment, the second predetermined format is the same as the first predetermined format, and the FPGA 23 comprises a first circuit 234. The first circuit 234 is between the input interface 231 and the first output interface 232. The first circuit 234 is configured to copy the first signal to generate the second signal. Here, when the second predetermined format is the same as the first predetermined format, the FPGA directly performs the copying process on the first signal based on the built-in first circuit 234 to generate the second signal, further improving the processing speed and reducing the complexity.

[0064] In one embodiment, the second predetermined format is different from the first predetermined format, and the FPGA 23 comprises a first circuit 234. The first circuit 234 is between the input interface 231 and the first output interface 232. The first circuit 234 is configured to convert the format of the first signal to the second signal. Here, when the second predetermined format is different from the first predetermined format, the FPGA 23 performs the format conversion on the first signal based on the built-in first circuit 234 to convert the first signal into the second signal with the second predetermined format, so that the transmitter 22 performs the format conversion on the second signal to output the loopback DP signal.

[0065] For example, the first predetermined format can be an RGBHW format, and the second predetermined format can be a Low-Voltage Differential Signaling (LVDS) format, a Digital Visual Interface (DVI) format, an HDMI format or a Video Graphics Array (VGA) format. It can be seen that the embodiment of the utility model supports conversion of multiple types of video signal formats, and has the advantage of wide applicability.

[0066] In one embodiment, the FPGA 23 comprises a second circuit 235. The second circuit 235 is between the input interface 231 and the second output interface 233. The second circuit 235 is configured to convert the first signal into a third signal. Therefore, in the embodiment of the utility model, the FPGA 23 can conveniently convert the first signal into the third signal based on the built-in second circuit 235.

[0067] In Figure 2 In the signal converter 20 shown in the prior art, when the receiver 21 receives the first DP signal from the DP signal source 24, a link training process is performed; when the transmitter 22 sends the second DP signal to the loopback end 25, a link training process is performed. Therefore, a total of two link training processes need to be performed.

[0068] It can be seen that, compared with Figure 1 Compared with the signal converter in the prior art shown in the prior art, the signal converter 20 of the embodiment of the present application eliminates the splitter and can also reduce the number of link training processes, thereby significantly improving the signal processing speed and reducing the delay time.

[0069] With reference to Figure 2 The embodiment of the present application also proposes a signal conversion system. The signal conversion system comprises a DP signal source 24, a signal converter 20, an output end 26 and a loopback end 25.

[0070] The signal converter 20 comprises a receiver 21, an FPGA 23 and a transmitter 22. The receiver 21 is coupled with the DP signal source 24. The FPGA 23 comprises an input interface 231, a first output interface 232 and a second output interface 233. The input interface 231 is coupled with the receiver 21, the first output interface 232 is coupled with the transmitter 22, the second output interface 233 is coupled with the output end 26, and the transmitter 22 is coupled with the loopback end 25.

[0071] The receiver 21 is configured to receive a first DP signal from the DP signal source 24 and convert the first DP signal into a first signal in a first predetermined format. The FPGA 23 is configured to acquire the first signal from the receiver 21 based on the input interface 231, generate a second signal in a second predetermined format based on the first signal, and send the second signal to the transmitter 22 based on the first output interface 232. Moreover, the FPGA 23 is configured to convert the first signal into a third signal compatible with a signal format of the output end 26, and send the third signal to the output end 26 based on the second output interface 233. The transmitter 22 is configured to convert the second signal into a second DP signal and send the second DP signal to the loopback end 25.

[0072] In one embodiment, the second predetermined format is the same as the first predetermined format, and the FPGA 23 comprises a first circuit 234. The first circuit 234 is between the input interface 231 and the first output interface 232. The first circuit 234 is configured to copy the first signal to generate the second signal. Here, when the second predetermined format is the same as the first predetermined format, the FPGA 23 only needs to copy the first signal to generate the second signal.

[0073] In one embodiment, the second predetermined format is different from the first predetermined format; the FPGA 23 comprises a first circuit 234 between the input interface 231 and the first output interface 232. The first circuit 234 is configured to convert the first signal format to a second signal. Here, when the second predetermined format is different from the first predetermined format, the FPGA 23 needs to convert the format of the first signal to the second predetermined format, thereby generating the second signal. For example, the first predetermined format can be an RGBHW format; the second predetermined format can be an LVDS signal format, a DVI format, an HDMI or a VGA format, etc.

[0074] In one embodiment, the signal conversion system is connected to a medical imaging system 100, wherein the DP signal source 24 is from the medical imaging system 100. In one embodiment, the medical imaging system 100 comprises a CT system, an X-ray photography system, a magnetic resonance imaging system, an ultrasound system or an endoscope imaging system, etc.

[0075] Figure 3 is a first exemplary structure diagram of the signal converter according to the embodiments of the present application.

[0076] As shown in Figure 3 , the signal converter 20 comprises a receiver 21, an FPGA 23 and a transmitter 22. The receiver 21 is coupled to the DP signal source 24, the FPGA 23 is coupled to the receiver 21, the transmitter 22 and the output terminal 26 respectively, and the transmitter 22 is coupled to the loopback terminal 25. The FPGA 23 comprises an input interface 231, a first output interface 232 and a second output interface 233, wherein the input interface 231 is coupled to the receiver 21, the first output interface 232 is coupled to the transmitter 22, and the second output interface 233 is coupled to the output terminal 26.

[0077] The receiver 21 can receive the first DP signal from the DP signal source 24. The first DP signal can carry audio and / or video, etc. The receiver 21 converts the first DP signal into a first signal with an RGBHV format. The receiver 21 sends the first signal with the RGBHV format to the input interface 231 of the FPGA 23. The FPGA 23 obtains the first signal from the receiver 21 based on the input interface 231.

[0078] The output terminal 26 supports a data format of a DVI format. The second circuit 235 in the FPGA 23 converts the first signal with the RGBHV format into a third signal with the DVI format. The FPGA 23 sends the third signal with the DVI format to the output terminal 26 based on the second output interface 233. Therefore, the third signal with the DVI format can be displayed at the output terminal 26.

[0079] Further, the first circuit 234 in the FPGA 23 performs a copy processing on the first signal having the RGBHV format to generate a copy signal (i.e., a second signal) having the RGBHV format. The first output interface 232 in the FPGA 23 sends the second signal to the transmitter 22. The transmitter 22 converts the second signal having the RGBHV format into a second DP signal having the DP format, and then sends the second DP signal to the loopback end 25. At the loopback end 25, the second DP signal can be processed for troubleshooting and other applications, thereby ensuring stable transmission of the DP signal provided by the DP signal source 21.

[0080] Figure 4 is a second exemplary structure diagram of the signal converter according to the embodiments of the present application.

[0081] As shown in Figure 4 , the signal converter 20 comprises a receiver 21, an FPGA 23 and a transmitter 22. The receiver 21 is coupled with a DP signal source 24, the FPGA 23 is coupled with the receiver 21, the transmitter 22 and an output end 26 respectively, and the transmitter 22 is coupled with a loopback end 25. The FPGA 23 comprises an input interface 231, a first output interface 232 and a second output interface 233, wherein the input interface 231 is coupled with the receiver 21, the first output interface 232 is coupled with the transmitter 22, and the second output interface 233 is coupled with the output end 26.

[0082] The receiver 21 can receive a first DP signal from the DP signal source 24. The first DP signal can carry audio and / or video, etc. The receiver 21 converts the first DP signal into a first signal having the RGBHV format. The receiver 21 sends the first signal having the RGBHV format to the input interface 231 of the FPGA 23. The FPGA 23 acquires the first signal from the receiver 21 based on the input interface 231.

[0083] The output end 26 supports a data format of HDMI format. The second circuit 235 in the FPGA 23 converts the first signal having the RGBHV format into a third signal having the HDMI format. The FPGA 23 sends the third signal having the HDMI format to the output end 26 based on the second output interface 233. Therefore, the third signal having the HDMI format can be displayed at the output end 26.

[0084] Further, the first circuit 234 in the FPGA 23 converts the first signal in the RGBHV format into a second signal in the LVDS format. The first output interface 232 in the FPGA 23 sends the second signal in the LVDS format to the transmitter 22. The transmitter 22 converts the second signal in the LVDS format into a second DP signal in the DP format, and sends the second DP signal to the loopback end 25. At the loopback end 25, troubleshooting and other applications can be performed on the second DP signal, thereby ensuring stable transmission of the DP signal provided by the DP signal source 24.

[0085] The embodiment of the present application can be applied to various scenarios with video loopback requirements, such as broadcast television, monitoring systems, video conferencing, educational demonstrations, medical imaging, and the like. The embodiment of the present application will be described below with reference to the medical imaging scenario as an example.

[0086] Figure 5 is an exemplary structural diagram of a signal conversion system of a medical imaging system according to the embodiment of the present application. The signal conversion system includes a medical imaging system 100, a signal converter 20, a loopback end 25, and an output end 26. The medical imaging system 100 includes a DP signal source that can provide a DP signal carrying medical data. The signal converter 20 has a structure as shown in Figure 2 .

[0087] At the loopback end 25, the loopback DP signal provided by the signal converter 20 can be displayed and processed, thereby performing troubleshooting and other applications on the DP signal provided by the DP signal source, to ensure stable transmission of the DP signal provided by the DP signal source. At the output end 26, the video signal converted by the signal converter 20 based on the DP signal provided by the DP signal source can be displayed and processed.

[0088] As can be seen, the user can not only browse the video signal through the output end 26, but also understand the DP signal quality and perform troubleshooting and other applications through the loopback end 25.

[0089] For example, the medical imaging system 100 can include:

[0090] (1) X-ray photography system: The X-ray photography system is one of the common medical imaging devices, and is usually used to obtain two-dimensional images of the skeletal system and certain tissue structures. It generates bone and tissue images by emitting X-rays and receiving reflected X-rays through an inductor. The X-ray device can include a traditional X-ray machine and a digital X-ray device, such as a C-arm type X-ray device. When the medical imaging system 100 is implemented as an X-ray photography system, the DP signal source can be implemented as an image workstation in the X-ray photography system, and the medical data carried in the DP signal can be an X-ray image.

[0091] (2) CT system: CT system uses a rotating X-ray source and a sensor to perform multi-angle in vivo imaging, which can generate a digital cross-sectional image. CT scanning can provide more detailed anatomical structure and tissue information, and is widely used in diagnosis and surgical planning. When the medical imaging system 100 is implemented as a CT system, the DP signal source can be implemented as an image workstation in the CT system, and the medical data carried in the DP signal can be a CT image.

[0092] (3) Magnetic resonance imaging (MRI) system: MRI system can provide detailed anatomical structure information by using strong magnetic field and radio waves to obtain high-resolution internal images, and has high resolution for soft tissue, and can obtain multiple plane medical images. When the medical imaging system 100 is implemented as an MRI system, the DP signal source can be implemented as an image workstation in the MRI system, and the medical data carried in the DP signal can be an MRI image.

[0093] (4) Ultrasound system: Ultrasound system uses ultrasound waves to generate real-time internal images. It sends ultrasound waves to the human body and receives their echoes, forms medical images according to the propagation and reflection of sound waves in different tissues. When the medical imaging system 100 is implemented as an ultrasound system, the DP signal source can be implemented as an image workstation in the ultrasound system, and the medical data carried in the DP signal can be an ultrasound image.

[0094] (5) Endoscopic imaging system: Endoscopic imaging system usually includes an optical imaging system and an illumination system, which is used to provide light for the optical imaging system or to provide excitation light, so that the optical imaging system can image the tissue in the human body to observe the lesion or perform surgery. When the medical imaging system is implemented as an endoscopic imaging system, the VGA video signal source can be implemented as an image workstation in the endoscopic imaging system, and the medical data carried in the VGA video signal can be an endoscopic image.

[0095] The above describes the medical imaging system as an example to demonstrate the embodiments of the present application. Those skilled in the art can realize that this description is only exemplary and is not used to limit the protection scope of the embodiments of the present application. It is easy to understand that the various signal converters and signal conversion systems described by way of example in the present application can be applied to scenes where multiple medical imaging devices are applied, such as composite examination rooms or composite operating rooms. At the same time, the signal converter or signal conversion system of the embodiments of the present application can also be applied to occasions requiring high-quality video display in broadcast television, monitoring system, video conference, education demonstration, etc.

[0096] It should be noted that not all the modules in the above structural diagrams are necessary, and some modules can be ignored according to actual needs. The division of each module is only for the convenience of description of the functional division, and in actual implementation, one module can be implemented by multiple modules, and the functions of multiple modules can be implemented by the same module. These modules can be located in the same device or in different devices.

[0097] The hardware module in each embodiment can be implemented mechanically or electronically. For example, a hardware module can include a specifically designed permanent circuit or logic device (such as a special-purpose processor, such as an FPGA or an ASIC) for completing a specific operation. The hardware module can also include a programmable logic device or circuit (such as including a general-purpose processor) for performing a specific operation. As to whether to implement the hardware module mechanically, or to implement the hardware module by using a special permanent circuit, or to implement the hardware module by using a temporarily configured circuit, the decision can be made according to cost and time considerations.

[0098] The above is only a preferred embodiment of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A signal converter (20), characterized by The signal converter (20) comprises a receiver (21), a field programmable gate array (23) and a transmitter (22); the receiver (21) is coupled with a DP signal source (24); the field programmable gate array (23) comprises an input interface (231), a first output interface (232) and a second output interface (233); the input interface (231) is coupled with the receiver (21); the first output interface (232) is coupled with the transmitter (22); the second output interface (233) is coupled with an output terminal (26); the transmitter (22) is coupled with a loopback terminal (25); wherein: The receiver (21) is configured to receive a first DP signal from the DP signal source (24) and convert the first DP signal into a first signal in a first predetermined format; The field programmable gate array (23) is configured to acquire the first signal based on the input interface (231), generate a second signal in a second predetermined format based on the first signal, send the second signal to the transmitter (22) based on the first output interface (232), convert the first signal into a third signal compatible with a signal format of the output terminal (26), and send the third signal to the output terminal (26) based on the second output interface (233); The transmitter (22) is configured to convert the second signal into a second DP signal and send the second DP signal to the loopback terminal (25).

2. The signal converter (20) according to claim 1, characterized in that The second predetermined format is the same as the first predetermined format; The field programmable gate array (23) comprises a first circuit (234) between the input interface (231) and the first output interface (232); the first circuit (234) is configured to copy the first signal to generate the second signal.

3. The signal converter (20) according to claim 1, characterized in that The second predetermined format is different from the first predetermined format; The field programmable gate array (23) comprises a first circuit (234) between the input interface (231) and the first output interface (232); the first circuit (234) is configured to convert the first signal format into the second signal.

4. The signal converter (20) according to any one of claims 1-3, characterized in that, The field programmable gate array (23) comprises a second circuit (235) between the input interface (231) and the second output interface (233); the second circuit (235) is configured to convert the first signal into the third signal.

5. A signal conversion system characterized by, The signal converter (20) comprises: The DP signal source (24); The signal converter (20); The output terminal (26); The loopback terminal (25); The signal converter (20) comprises a receiver (21), a field programmable gate array (23) and a transmitter (22); the receiver (21) is coupled with the DP signal source (24), the field programmable gate array (23) comprises an input interface (231), a first output interface (232) and a second output interface (233), the input interface (231) is coupled with the receiver (21), the first output interface (232) is coupled with the transmitter (22), the second output interface (233) is coupled with the output end (26), and the transmitter (22) is coupled with the loopback end (25); wherein: the receiver (21) is configured to receive a first DP signal from the DP signal source (24) and convert the first DP signal into a first signal in a first predetermined format; the field programmable gate array (23) is configured to acquire the first signal based on the input interface (231), generate a second signal in a second predetermined format based on the first signal, send the second signal to the transmitter (22) based on the first output interface (232), convert the first signal into a third signal compatible with a signal format of the output end (26), and send the third signal to the output end (26) based on the second output interface (233); and the transmitter (22) is configured to convert the second signal into a second DP signal and send the second DP signal to the loopback end (25).

6. The signal conversion system of claim 5, wherein, The second predetermined format is the same as the first predetermined format. The field programmable gate array (23) comprises a first circuit (234) between the input interface (231) and the first output interface (232); the first circuit (234) is configured to copy the first signal to generate the second signal.

7. The signal conversion system of claim 5, wherein, The second predetermined format is different from the first predetermined format. The field programmable gate array (23) comprises a first circuit (234) between the input interface (231) and the first output interface (232); the first circuit (234) is configured to convert the first signal format into the second signal.

8. The signal conversion system of any of claims 5-7, wherein, The field programmable gate array (23) comprises a second circuit (235) between the input interface (231) and the second output interface (233); the second circuit (235) is configured to convert the first signal into the third signal.

9. The signal conversion system of any of claims 5-7, wherein, The signal conversion system is connected with a medical imaging system (100), wherein the DP signal source (24) is from the medical imaging system (100).

10. The signal conversion system of claim 9, wherein, The medical imaging system (100) comprises a computed tomography system, an X-ray photography system, a magnetic resonance imaging system, an ultrasound system or an endoscopic imaging system.

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