Abnormality detection circuit and lamp
By designing an anomaly detection circuit, including a power detection circuit, a boost circuit, and a load detection circuit, the problem that traditional power detection circuits cannot fully detect the normality of the power supply and load is solved, thus achieving comprehensive circuit detection and damage prevention.
Patent Information
- Application Number
- CN202422395472.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2034-09-30
AI Technical Summary
Traditional power supply detection circuits cannot fully detect whether the power supply and load are normal, especially when the load is abnormally open-circuited, and are prone to misjudgment.
Design an anomaly detection circuit, including a power supply detection circuit, a boost circuit, a load detection circuit, and a main control chip. By detecting the input power supply voltage, the load supply voltage, and the current, when an anomaly is determined, the main control chip controls the switch to shut down through the boost circuit to prevent circuit damage.
It enables comprehensive testing of the circuit, reducing the risk of misjudgment and circuit damage.
Smart Images
Figure CN223770366U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power supply technology, and in particular to an abnormality detection circuit and a lamp. Background Technology
[0002] Traditional methods for monitoring circuit anomalies involve simply adding a voltage detection circuit to determine if the power supply is functioning correctly. However, when the load is open-circuited, the power supply voltage remains normal, making it impossible to detect the load anomaly. Furthermore, if a detection circuit is only added to the load side to monitor its supply voltage and current, a false alarm will occur when the power supply is switched off. Conversely, if a detection circuit is only added to the power supply side to monitor the voltage, an anomaly in the circuit between the power supply and the load will not be detected. Therefore, traditional power supply circuits cannot comprehensively detect whether both the power supply and the load are functioning correctly. Utility Model Content
[0003] The purpose of this invention is to provide an abnormality detection circuit and a lamp that can detect both the voltage of the input power supply on the power supply side and the supply voltage and current on the load side. When an abnormality occurs in the circuit, the main control chip controls the switch to turn off through the boost circuit to prevent further damage to the circuit.
[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0005] One aspect of this utility model provides an anomaly detection circuit, the detection circuit comprising: a power supply detection circuit, the detection input terminal of the power supply detection circuit being connected to an input power supply; a boost circuit, the input terminal of the boost circuit being connected to the input power supply; a switch, the input terminal of the switch being connected to the output terminal of the boost circuit, the output terminal of the switch being connected to a load, the boost circuit controlling the switch to close or close; a load detection circuit, the detection input terminal of the load detection circuit being connected to a load; and a main control chip, the main control chip being connected to the detection output terminal of the power supply detection circuit, the control terminal of the boost circuit, and the detection output terminal of the load detection circuit, respectively.
[0006] In some embodiments, the boost circuit includes a first resistor, an NMOS transistor, an inductor, a diode, and a first capacitor. One end of the inductor is connected to the input power supply, and the other end of the inductor is connected to the anode of the diode and the drain of the NMOS transistor. The gate of the NMOS transistor is connected to one end of the first resistor and the main control chip. The other end of the first resistor and the source of the NMOS transistor are grounded. The cathode of the diode is connected to the anode of the first capacitor and the input terminal of the switch. The cathode of the first capacitor is grounded.
[0007] In some embodiments, the switch includes a PMOS transistor, the source of which is connected to the output of the boost circuit, the gate of which is connected to the input power supply, and the drain of which is connected to the positive terminal of the load.
[0008] In some embodiments, the switch further includes a Zener diode, the anode of which is connected to the gate of the PMOS transistor, and the cathode of which is connected to the source of the PMOS transistor.
[0009] In some embodiments, the load detection circuit includes a voltage detection circuit and a current detection circuit. The voltage detection circuit includes a second resistor, a third resistor, and a second capacitor. One end of the second resistor is connected to the positive terminal of the load, and the other end of the second resistor is connected to one end of the third resistor, one end of the second capacitor, and the main control chip. The other end of the third resistor and the other end of the second capacitor are grounded.
[0010] In some embodiments, the current detection circuit includes a fourth resistor, a fifth resistor, and a third capacitor. One end of the fourth resistor is connected to one end of the fifth resistor and the negative terminal of the load. The other end of the fourth resistor is connected to one end of the third capacitor and the main control chip. The other end of the fifth resistor and the other end of the third capacitor are grounded.
[0011] In some embodiments, the power detection circuit includes a sixth resistor, a seventh resistor, and a fourth capacitor. One end of the sixth resistor is connected to the input power supply, and the other end of the sixth resistor is connected to one end of the seventh resistor, one end of the fourth capacitor, and the main control chip. The other end of the seventh resistor and the other end of the fourth capacitor are grounded.
[0012] In some embodiments, the detection circuit further includes a rectifier and filter circuit, which includes a rectifier bridge and a fifth capacitor. The input terminal of the rectifier bridge is connected to the initial power supply, the positive output terminal of the rectifier bridge is connected to the positive terminal of the fifth capacitor, the negative output terminal of the rectifier bridge is used as the ground, and the negative terminal of the fifth capacitor is grounded.
[0013] In some embodiments, the detection circuit further includes an eighth resistor and a ninth resistor, one end of the eighth resistor being connected to the source of the PMOS transistor, the other end of the eighth resistor being connected to the drain of the PMOS transistor, one end of the ninth resistor and the positive terminal of the load, and the other end of the ninth resistor being connected to the negative terminal of the load.
[0014] One aspect of this utility model provides a lamp, which includes the detection circuit described above.
[0015] An anomaly detection circuit and lamp according to an embodiment of this utility model have at least the following beneficial effects: When the voltage is abnormal, the power supply detection circuit and voltage detection circuit can determine whether the abnormality is due to the input voltage on the power supply side or the supply voltage on the load side. When the load is abnormally open-circuited, the current detection circuit can detect the load abnormality. This application can reduce the scope of circuit maintenance. When an anomaly occurs in the circuit, the main control chip controls the switch to turn off through the boost circuit to prevent further damage to the circuit.
[0016] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of an anomaly detection circuit according to an embodiment.
[0019] The following are the annotations in the attached diagram: 1. Power supply detection circuit; 2. Boost circuit; 3. Load detection circuit; 31. Voltage detection circuit; 32. Current detection circuit. Detailed Implementation
[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0021] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.
[0022] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.
[0024] The technical solutions of the embodiments of this application are briefly described below:
[0025] According to some embodiments, such as Figure 1 As shown, this application provides an anomaly detection circuit, the detection circuit including:
[0026] Power detection circuit 1, the detection input terminal of power detection circuit 1 is connected to the input power supply Vin;
[0027] Boost circuit 2, the input terminal of boost circuit 2 is connected to the input power supply Vin;
[0028] The input terminal of the switch is connected to the output terminal of the boost circuit 2, and the output terminal of the switch is connected to the load. The boost circuit 2 controls the switch to close or close.
[0029] Load detection circuit 3, the detection input terminal of load detection circuit 3 is connected to the load;
[0030] The main control chip U is connected to the detection output terminal of the power detection circuit 1, the control terminal of the boost circuit 2, and the detection output terminal of the load detection circuit 3.
[0031] The working principle of the above embodiment is as follows: when the voltage is abnormal, the main control chip U detects the voltage of the input power supply Vin through the power supply detection circuit 1, and then detects the supply voltage OUT of the load through the load detection circuit 3. If the voltage of the input power supply Vin is abnormal, it is determined that the power supply is abnormal; if the voltage of the input power supply Vin is normal, but only the supply voltage OUT is abnormal, it is determined that the load is abnormal or the boost circuit 2 is abnormal. This reduces the scope of maintenance. Regardless of whether the power supply, boost circuit 2, or load is abnormal, the main control chip U controls the boost circuit 2 to stop working. Specifically, when the boost circuit 2 is working, the switch is on; when the boost circuit 2 stops working, the switch is off.
[0032] The following is in conjunction with the appendix to this instruction manual. Figure 1 The preferred embodiments of this disclosure will be further described in detail below.
[0033] According to some embodiments, such as Figure 1 As shown, the boost circuit 2 includes a first resistor R1, an NMOS transistor QN, an inductor L, a diode D, and a first capacitor C1. One end of the inductor L is connected to the input power supply Vin, and the other end of the inductor L is connected to the anode of the diode D and the drain of the NMOS transistor QN. The gate of the NMOS transistor QN is connected to one end of the first resistor R1 and the main control chip U, and the other end of the first resistor R1 and the source of the NMOS transistor QN are grounded. The cathode of the diode D is connected to the anode of the first capacitor C1 and the input terminal of the switch, and the cathode of the first capacitor C1 is grounded.
[0034] According to some embodiments, such as Figure 1 As shown, the switch includes a PMOS transistor QP. The source of the PMOS transistor QP is connected to the output terminal of the boost circuit 2, the gate of the PMOS transistor QP is connected to the input power supply Vin, and the drain of the PMOS transistor QP is connected to the positive terminal of the load.
[0035] The working principle based on the above embodiment is as follows: when the boost circuit 2 is working normally, the main control chip U outputs a pulse signal to the gate of the NMOS transistor QN. The NMOS transistor QN repeatedly turns on and off, the boost circuit 2 starts to boost the voltage, the source of the PMOS transistor QP receives the boosted voltage, the gate of the PMOS transistor QP is the voltage before boosting, the PMOS transistor QP turns on, and outputs the power supply voltage OUT to the load.
[0036] When boost circuit 2 stops working, the main control chip U does not output a signal to the gate of NMOS transistor QN. The gate of NMOS transistor QN is grounded through R1, NMOS transistor QN is turned off, boost circuit 2 does not work, the voltage difference between the source and gate of PMOS transistor QP cannot turn on PMOS transistor QP, and the load cannot be energized.
[0037] Furthermore, in some preferred embodiments, such as Figure 1As shown, the switch also includes a Zener diode ZD. The anode of the Zener diode ZD is connected to the gate of the PMOS transistor QP, and the cathode of the Zener diode ZD is connected to the source of the PMOS transistor QP. The Zener diode ZD is used to protect the PMMOS transistor.
[0038] According to some embodiments, such as Figure 1 As shown, the load detection circuit 3 includes a voltage detection circuit 31 and a current detection circuit 32. The voltage detection circuit 31 includes a second resistor R2, a third resistor R3, and a second capacitor C2. One end of the second resistor R2 is connected to the positive terminal of the load, and the other end of the second resistor R2 is connected to one end of the third resistor R3, one end of the second capacitor C2, and the main control chip U. The other end of the third resistor R3 and the other end of the second capacitor C2 are grounded.
[0039] Furthermore, such as Figure 1 As shown, the current detection circuit 32 includes a fourth resistor R4, a fifth resistor R5, and a third capacitor C3. One end of the fourth resistor R4 is connected to one end of the fifth resistor R5 and the negative terminal of the load. The other end of the fourth resistor R4 is connected to one end of the third capacitor C3 and the main control chip U. The other end of the fifth resistor R5 and the other end of the third capacitor C3 are grounded.
[0040] Furthermore, such as Figure 1 As shown, the power detection circuit 1 includes a sixth resistor R6, a seventh resistor R7, and a fourth capacitor C4. One end of the sixth resistor R6 is connected to the input power supply Vin, and the other end of the sixth resistor R6 is connected to one end of the seventh resistor R7, one end of the fourth capacitor C4, and the main control chip U. The other ends of the seventh resistor R7 and the other ends of the fourth capacitor C4 are grounded.
[0041] According to some embodiments, such as Figure 1 As shown, the detection circuit also includes a rectifier and filter circuit, which includes a rectifier bridge DB and a fifth capacitor C5. The input terminal of the rectifier bridge DB is connected to the initial power supply P, the positive output terminal of the rectifier bridge DB is connected to the positive terminal of the fifth capacitor C5, the negative output terminal of the rectifier bridge DB is used as ground, and the negative terminal of the fifth capacitor C5 is grounded.
[0042] According to some embodiments, such as Figure 1 As shown, the detection circuit also includes an eighth resistor R8 and a ninth resistor R9 for voltage division. One end of the eighth resistor R8 is connected to the source of the PMOS transistor QP, and the other end of the eighth resistor R8 is connected to the drain of the PMOS transistor QP. One end of the ninth resistor R9 is connected to the positive terminal of the load, and the other end of the ninth resistor R9 is connected to the negative terminal of the load.
[0043] The working principle of the above embodiment is as follows: the main control chip U detects the voltage of the input power supply Vin through the power supply detection circuit 1, detects the supply voltage OUT of the load through the voltage detection circuit 31, and detects the operating current of the load through the current detection circuit 32. If the voltage of the input power supply Vin is abnormal, it is determined that the power supply is abnormal; if the voltage of the input power supply Vin is normal, but only the supply voltage OUT is abnormal, it is determined that the load is abnormal or the boost circuit 2 is abnormal; if the voltage of the input power supply Vin is normal, the supply voltage OUT is normal, and the operating current of the load is abnormally reduced or absent, it is determined that the load is open-circuited. The abnormality detection circuit of this application can reduce the scope of maintenance. Regardless of whether the power supply, boost circuit 2, or load is abnormal, the main control chip U controls the boost circuit 2 to stop working and turns off the PMOS transistor QP to prevent further damage to the circuit.
[0044] According to some embodiments, this application provides a lamp that includes the detection circuit described above.
[0045] Specifically, the lighting fixture includes a light source, replacing the aforementioned load with the light source.
[0046] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0047] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or substance of this application, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.
Claims
1. An anomaly detection circuit, characterized by, The detection circuit comprises: a power supply detection circuit, a detection input end of the power supply detection circuit being connected to an input power supply; a boost circuit, an input end of the boost circuit being connected to the input power supply; a switch, an input end of the switch being connected to an output end of the boost circuit, an output end of the switch being connected to a load, and the boost circuit controlling the switch to be turned on or turned off; a load detection circuit, a detection input end of the load detection circuit being connected to the load; a master control chip, the master control chip being connected to a detection output end of the power supply detection circuit, a control end of the boost circuit and a detection output end of the load detection circuit respectively.
2. The detection circuit of claim 1, wherein, The boost circuit comprises a first resistor, an NMOS tube, an inductor, a diode and a first capacitor, one end of the inductor being connected to the input power supply, the other end of the inductor being connected to the anode of the diode and the drain of the NMOS tube, the gate of the NMOS tube being connected to one end of the first resistor and the master control chip, the other end of the first resistor and the source of the NMOS tube being grounded, the cathode of the diode being connected to the anode of the first capacitor and the input end of the switch, and the cathode of the first capacitor being grounded.
3. The detection circuit of claim 1, wherein, The switch comprises a PMOS tube, the source of the PMOS tube being connected to the output end of the boost circuit, the gate of the PMOS tube being connected to the input power supply, and the drain of the PMOS tube being connected to the anode of the load.
4. The detection circuit of claim 3, wherein, The switch further comprises a voltage stabilizing diode, the anode of the voltage stabilizing diode being connected to the gate of the PMOS tube, and the cathode of the voltage stabilizing diode being connected to the source of the PMOS tube.
5. The detection circuit of claim 1, wherein, The load detection circuit comprises a voltage detection circuit and a current detection circuit, the voltage detection circuit comprising a second resistor, a third resistor and a second capacitor, one end of the second resistor being connected to the anode of the load, the other end of the second resistor being connected to one end of the third resistor, one end of the second capacitor and the master control chip, and the other end of the third resistor and the other end of the second capacitor being grounded.
6. The detection circuit of claim 5, wherein, The current detection circuit comprises a fourth resistor, a fifth resistor and a third capacitor, one end of the fourth resistor being connected to one end of the fifth resistor and the cathode of the load, the other end of the fourth resistor being connected to one end of the third capacitor and the master control chip, and the other end of the fifth resistor and the other end of the third capacitor being grounded.
7. The detection circuit of claim 1, wherein, The power supply detection circuit comprises a sixth resistor, a seventh resistor and a fourth capacitor, one end of the sixth resistor being connected to the input power supply, the other end of the sixth resistor being connected to one end of the seventh resistor, one end of the fourth capacitor and the master control chip, and the other end of the seventh resistor and the other end of the fourth capacitor being grounded.
8. The detection circuit of claim 1, wherein, The detection circuit further comprises a rectification and filtering circuit, the rectification and filtering circuit comprising a rectification bridge and a fifth capacitor, the input end of the rectification bridge being connected to an initial power supply, the anode output end of the rectification bridge being connected to the anode of the fifth capacitor, the cathode output end of the rectification bridge being used as a ground point, and the cathode of the fifth capacitor being grounded.
9. The detection circuit of claim 3, wherein, The detection circuit further comprises an eighth resistor and a ninth resistor, one end of the eighth resistor is connected to the source of the PMOS tube, the other end of the eighth resistor is connected to the drain of the PMOS tube, one end of the ninth resistor and the positive pole of the load, the other end of the ninth resistor is connected to the negative pole of the load.
10. A luminaire characterized by, The lamp comprises the detection circuit as claimed in any one of claims 1 to 9.