Digital-to-analog converter of R-2R structure

Abstract

The utility model discloses a digital-to-analog converter with an R-2R structure, which solves the problem in the prior art that the precision of a DAC (Digital-to-Analog Converter) based on the R-2R architecture is limited by the cost caused by the increase of the number of unit resistors, and comprises an R-2R trapezoidal array circuit and a switch array circuit, the R-2R trapezoidal array circuit comprises a low-order branch circuit, a low-order branch circuit and a high-order branch circuit, the low-order branch comprises M small-unit resistors which are connected in series and have the same resistance value, the input end of the switch array circuit is connected with a V-I conversion circuit and a decoding unit, the output end of the switch array circuit is connected with the input end of the low-order branch, and reference voltage is connected to the input end of the V-I conversion circuit. The performance and the precision of the DAC can be improved, meanwhile, the occupied area is not too large, and the cost is saved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a digital-to-analog converter with an R-2R structure. Background Technology

[0002] Digital-to-analog converters (DACs), acting as a bridge between the digital and analog worlds, convert processed digital signals into the required analog signals. They play an indispensable role in all aspects of human society, from consumer electronics to national defense. With the development of integrated circuits towards higher integration and lower power consumption, especially with the rise of the Internet of Things and wearable devices, the need for further reduction in DAC size is increasing, especially given the demands for multi-channel, high-integration systems. Therefore, reducing the size of DACs has practical significance and application value.

[0003] R-2R structure DACs utilize a binary-weighted R-2R resistor network for digital-to-analog conversion, resulting in a simple circuit structure and low power consumption. Traditional voltage-mode R-2R trapezoidal resistor DACs switch the resistor ladder between VREF and ground, outputting at V1. Their advantages include constant output impedance, and each additional resistor ladder increases resolution by one bit. However, in high-precision DAC design, the matching performance per unit resistor is positively correlated with the resistor area; a larger unit resistor area results in higher matching performance, higher DAC linearity, and higher accuracy. In integrated circuit design, a large number of resistors with high matching requirements translates to a larger chip area and higher cost. Achieving higher accuracy and linearity in a DAC within the same chip area has become a challenge.

[0004] Another common structure for R-2R trapezoidal resistor DACs involves injecting equal current sources into the R-2R resistor network. However, similarly, the number of unit resistors and the number of unit current sources are proportional to the resolution. The accuracy of this architecture requires not only high matching between unit resistors but also even higher matching between unit current sources. Therefore, the accuracy of existing R-2R-based DACs is limited by the increased chip area cost resulting from the increased number of unit resistors. Summary of the Invention

[0005] The purpose of this invention is to solve the problem that the accuracy of existing R-2R architecture-based DACs is limited by the cost increase caused by the increase in the number of unit resistors. It provides an R-2R structure digital-to-analog converter that can improve DAC performance and accuracy without occupying too much area, thus saving costs.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] An R-2R structure digital-to-analog converter includes an R-2R trapezoidal array circuit and a switch array circuit. The R-2R trapezoidal array circuit includes a low-order branch, which includes M small unit resistors connected in series with the same resistance value. The input terminal of the switch array circuit is connected to a VI conversion circuit and a decoding unit. The output terminal of the switch array circuit is connected to the input terminal of the low-order branch. The input terminal of the VI conversion circuit is connected to a bandgap reference voltage terminal.

[0008] M=2 m , m represents the number of output bits of the low-order branch, which is a positive integer. The R-2R structure digital-to-analog converter provided by this utility model achieves a small area and high precision for a voltage-type R-2R architecture DAC, and is applicable to voltage-type R-2R architecture digital-to-analog converters of any bit width.

[0009] Preferably, the switch array circuit includes M-1 first switches, with the output terminal of a first switch connected between every two adjacent small unit resistors, the first input terminal of the first switch connected to the output terminal of the VI conversion circuit, and the second input terminal of the first switch connected to the control terminal of the decoding unit.

[0010] Preferably, the circuit also includes a unity-gain buffer, wherein the positive input of the unity-gain buffer is connected to the output of the R-2R trapezoidal array circuit, and the negative input of the unity-gain buffer is connected to the output of the unity-gain buffer.

[0011] Preferably, the R-2R trapezoidal array circuit includes x-channel middle-high branch and y-channel high branch. Each middle-high branch includes a second switch and an R-2R resistor unit. The R-2R resistor unit includes a resistor with a resistance of 2R and a resistor with a resistance of R. Each high branch includes a third switch and a resistor with a resistance of 2R.

[0012] Preferably, the VI conversion circuit includes a first conversion circuit and a second conversion circuit. The input terminal of the first conversion circuit is connected to the output terminal of a first operational amplifier. The positive input terminal of the first operational amplifier is connected to a reference voltage, and the output terminal of the first operational amplifier is grounded. The output terminal of the first conversion circuit is connected to the positive input terminal of the second operational amplifier. The input terminal of the second conversion circuit is connected to the output terminal of the second operational amplifier, and the output terminal of the second conversion circuit is connected to the first input terminal of the switch array circuit.

[0013] Preferably, the first conversion circuit includes a first N-type field-effect transistor, the second conversion circuit includes a second N-type field-effect transistor, the gate of the first N-type field-effect transistor is connected to the output terminal of the first operational amplifier, the drain of the first N-type field-effect transistor is connected to the positive input terminal of the second operational amplifier, the negative input terminal of the second operational amplifier is connected to the drain of the second N-type field-effect transistor, the gate of the second N-type field-effect transistor is connected to the output terminal of the second operational amplifier, and the drain of the second N-type field-effect transistor is connected to the first input terminal of the switching array circuit.

[0014] Preferably, the conversion circuit further includes four resistors, each with a resistance of R. One end of the first resistor is connected to the power supply, and the other two ends of the first resistor are connected to the drain of the first N-type field-effect transistor. One end of the second resistor is connected to the source of the first N-type field-effect transistor, and the other end of the second resistor is connected to one end of the third resistor, the other end of the third resistor is grounded, and one end of the fourth resistor is connected to the power supply, and the other end of the fourth resistor is connected to the drain of the second N-type field-effect transistor.

[0015] Preferably, the unity-gain buffer is a unity-gain operational amplifier.

[0016] Preferably, it includes 6 medium-high level branches and 3 high level branches; the low level branches include 64 small unit resistors with the same resistance value connected in series and 63 first switches, with the control terminal of a first switch connected between every two adjacent small unit resistors, the first input terminal of the first switch connected to the output terminal of the VI conversion circuit, and the second input terminal of the first switch connected to the control terminal of the decoding unit.

[0017] Preferably, the decoding unit is a decoder.

[0018] Therefore, the present invention has the following beneficial effects: by adopting a segmented strategy, the R-2R resistor on the left side of the traditional R-2R architecture is split into a resistor and an equal small unit resistor, while the R-2R resistor on the right side is consistent with the traditional analog voltage generation method. The decoding unit uses the current generated by the VI conversion module to control the opening and closing of the switch array connected to the small unit resistor to generate the corresponding analog voltage, so that higher precision resolution can be achieved on the same resistor area. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the digital-to-analog converter with an R-2R structure in Example 1.

[0020] Figure 2 This is a schematic diagram of the digital-to-analog converter with an R-2R structure in Example 1.

[0021] Figure 3 This is a schematic diagram illustrating the principle of low-order analog voltage generation in the R-2R structure digital-to-analog converter of Example 2. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0023] Example 1:

[0024] This embodiment provides a digital-to-analog converter with an R-2R structure, which can be applied to voltage-type R-2R architecture digital-to-analog converters with any number of bits.

[0025] like Figure 1 As shown in the figure, this embodiment provides an R-2R structure digital-to-analog converter, including: a VI conversion circuit, a decoding unit 2, an R-2R ladder array circuit, a switch array circuit, and a unity-gain buffer. The R-2R ladder array circuit includes a low-order branch, a mid-high-order branch, and a high-order branch. The input terminal of the VI conversion circuit is connected to the bandgap reference voltage terminal. The output terminal of the VI conversion circuit is connected to the first input terminal of the switch array circuit. The second input terminal of the switch array circuit is connected to the control terminal of the decoding unit. The output terminal of the switch array circuit is connected to the input terminal of the low-order branch. The low-order branch, the mid-high-order branch, and the high-order branch are connected sequentially. The output terminal of the high-order branch is connected to the unity-gain buffer.

[0026] It should be noted that the digital-to-analog converter provided in this embodiment can be applied to voltage-type R-2R architecture digital-to-analog converters with any number of bits, that is, digital-to-analog converters with R-2R architecture for n-bit binary codes, improving the accuracy of m bits, where n and m are both positive integers.

[0027] R-2R architecture digital-to-analog converters (DACs) utilize binary-weighted R-2R resistor networks for digital-to-analog conversion, resulting in a simple circuit structure and low power consumption. However, traditional R-2R architecture DACs face two challenges: First, high-precision DACs have a large area. To match the MOS switches of each bit from the least significant bit to the most significant bit and improve DAC performance, the width W of each MOS switch needs to be doubled, i.e., the area doubled. When the DAC has a high bit depth, the area of ​​the MOS switches becomes extremely large. Second, R-2R architecture DACs struggle to achieve high conversion accuracy. Due to non-ideal effects such as unit resistance error and MOS switch on-resistance mismatch, both the static and dynamic performance of the DAC are affected, posing a challenge to the design of high-precision R-2R architecture DACs.

[0028] The R-2R structure digital-to-analog converter provided in this embodiment adopts a segmented strategy, splitting the R-2R resistor on the left side of the traditional R-2R architecture into a single resistor and an equal small unit resistor. The R-2R resistor on the right side is consistent with the traditional analog voltage generation method. The decoding unit uses the current generated by the VI conversion module to control the opening and closing of the switch array connected by the small unit resistor to generate the corresponding analog voltage. This enables higher resolution to be achieved on the same resistor area, solving the problem that the number of resistors and the resistor layout area of ​​the R-2R trapezoidal resistor DAC increase with the resolution, thus limiting the accuracy.

[0029] The specific structure of the digital-to-analog converter in this embodiment will be further explained below.

[0030] like Figure 1 As shown, the VI conversion circuit includes two conversion circuits and two identical clamping op-amps, with each conversion circuit connected to a clamping op-amp.

[0031] Specifically, the VI conversion circuit includes a first conversion circuit, a second conversion circuit, a first operational amplifier AMP1, a second operational amplifier AMP2, and four resistors, each with a resistance value of R (first resistor R, second resistor R, third resistor R, and fourth resistor R). The first conversion circuit includes a first N-type field-effect transistor M. N1 The second conversion circuit includes a second N-type field-effect transistor M. N2 The positive input terminal of the first operational amplifier AMP1 is connected to the reference voltage V. REF The negative input terminal of the first operational amplifier AMP1 is connected to the first N-type field-effect transistor M. N1 The source of the first N-type field-effect transistor M N1 The source of the first N-type field-effect transistor M is connected to one end of the second resistor R, the other end of the second resistor R is connected to one end of the third resistor R, and the other end of the third resistor R is grounded. N1 The drain of the first amplifier is connected to one end of the first resistor R, and the other end of the first resistor R is connected to the power supply; the positive input terminal of the second operational amplifier AMP2 is connected to the first N-type field-effect transistor M. N1 The drain of the second operational amplifier AMP2 is connected to the drain of the second N-type field-effect transistor M. N2 The drains of the second N-type field-effect transistor M are connected. N2 The drain of the transistor is connected to one end of the fourth resistor R, and the other end of the fourth resistor R is connected to the power supply. The second N-type field-effect transistor M N2 The source is connected to the first input terminal of the switch array circuit.

[0032] Based on the voltage clamping principle of the first operational amplifier AMP1, the first N-type field-effect transistor M N1 The source voltage V2 is referenced to the voltage V. REFThe voltage magnitudes are the same, and the first N-type field-effect transistor M N1 The current in the first switching circuit is V. REF / 2R.

[0033] Based on the voltage clamping principle of the second operational amplifier AMP2, the voltage V3 connected to the positive input terminal of the second operational amplifier AMP2 and the voltage V4 connected to the negative input terminal of the second operational amplifier AMP2 are of the same magnitude. Since the resistance between points V3 and V4 and the power supply voltage is R, the current in the two conversion circuits of the VI conversion circuit is equal, both being V. REF / 2R. Therefore, the output current of the VI conversion circuit is V. REF / 2R, and the current direction is downward.

[0034] In this embodiment, the decoding unit uses a decoder, and the decoder is m-2. m Decoder.

[0035] like Figure 1 As shown, the low-level branch includes 2 m A series of small unit resistors R with the same resistance value 0,1 ~R 0,2 m The switch array includes 2 m -1 First switch S 0,1 ~S2 m -1 Each pair of adjacent small unit resistors is connected to the output of a first switch. The first input of the first switch is connected to the output of the VI conversion circuit, and the second input of the first switch is connected to the control terminal of the decoder. The small unit resistor at the tail end is connected to the middle and high-order branch, and the small unit resistor at the head end is grounded.

[0036] In this embodiment, the middle-high branch and the high branch are R-2R trapezoidal mesh resistor networks, including x middle-high branches and y high branches. Each middle-high branch includes a second switch, an R resistor with a resistance of R, and a 2R resistor with a resistance of 2R. Each high branch includes a second switch and a 2R resistor with a resistance of 2R.

[0037] Therefore, the middle-high branch and the high branch together include (x+y) second switches, (x+y) 2R resistors, and x R resistors. In this embodiment, the 2R resistor is obtained by connecting two R resistors in series, so the middle-high branch and the high branch together include (2x+y) R resistors. The number of binary code bits for the digital-to-analog converter is: n = m + x + y - 1.

[0038] exist Figure 1 In this context, to represent the resistance relationship between resistor 2R and resistor R, resistor 2R is represented by two resistors R connected in series. The number of bits in a digital-to-analog converter is n = m + N + 3.

[0039] In this embodiment, the resistance of the small unit resistor is 2R. m One-third, that is: R 0,1～2 m =2R / 2 m .

[0040] The process of obtaining analog voltage by performing digital-to-analog conversion using the digital-to-analog converter in this embodiment is as follows, taking the high-output circuit as a three-way circuit, i.e., y=3 as an example:

[0041] In this embodiment, the low-order resistance ladder control codeword b0 obtained by the low-order branch is... B ~b m B The code is a binary code, and the high-order resistance ladder control codeword b1 obtained from the high-order branch is... T ~b3 T For the thermometer code, the control code b of the middle and high-level resistance ladder obtained from the middle and high-level branch. m B ~b n-3 B It is in binary code.

[0042] When the thermometer code b1 T ~b3 T When it is 1, switch S T0 ~S T2 Switch to V REF At one end, when the thermometer code b1 T ~b3 T When it is 0, switch S T0 ~S T2 Switch to ground, thermometer code b1 T ~b3 T With the high-order binary code b n-2 B ~b n-1 B The relationship is:

[0043] b1 T =b n-2 B +b n-1 B b2 T =b n-1 B b3 T =b n-2 B *b n-1 B .

[0044] Among them, the high-order binary code b m B ~b n-3B When it is 1, switch S m ~S n-3 Switch to V REF One end, where the high-order binary code b m B ~b n-3 B When it is 0, switch S m ~S n-3 Switch to ground.

[0045] The high-order binary code and the middle-high-order binary code control the switch array S m ~S n-3 With S T0 ~S T2 The generated analog voltage is consistent with the traditional R-2R architecture, as follows:

[0046] V R-2R =(b m B *2 0 +b m+1 B *2 1 +b m+2 B *2 2 +…+b n-2 B *2 n-m-2 +b n-1 B *2 n-m-1 )*V REF / 2 n-m .

[0047] Among them, V R-2R For the R-2R architecture itself, by switching the resistor ladder to V REF Or the analog voltage generated at the output terminal V1, b m B ~b n-1 B For the m-th to n-1th bits of the DAC's binary codeword, V REF The reference voltage can typically be generated by the internal reference bandgap module of the chip, or it can be provided by an external reference voltage source.

[0048] In this embodiment, the decoding unit is a 6-64 decoder, which decodes the binary codeword b0 from bits 0 to m. B ~b m B Convert to 2 m Choosing the code 1 makes S 0,1 ~S2 m -1 The Kth switch S in the switch array 0,MWhen closed, all other switches are open, including b0. B ~b m B The relationship with K is:

[0049] K = b0 B *2 0 +b1 B *2 1 +……+b m-2 B *2 m-2 +b m-1 B *2 m-1 .

[0050] When K = 0, S 0,1 ~S2 m -1 All switches in the switch array are open, K = 1, 2, ..., 2 m-1 .

[0051] Low-order binary code b0 B ~b m B The decoding unit controls the opening and closing of all switches in the switch array, and adjusts the position of the output current of the VI conversion circuit injected into the small unit resistor in the low-order branch to generate a low-order binary weighted analog voltage.

[0052] Using the reciprocity theorem, in a linear circuit with only one current source and no controlled source, the voltmeter reading remains unchanged when the positions of the current source and the voltmeter are interchanged. Similarly, by interchangering the output current injection position of the VI converter circuit with the output position of the R-2R trapezoidal array circuit, according to the characteristics of the R-2R trapezoidal resistor, the current falling on the small unit resistor in the lower branch is 1 / 2. n-m I represents the output current of the VI conversion circuit.

[0053] And: V I =(1 / 2) n-m I)n*2R / 64.

[0054] Let I = V REF Substituting the formulas for / 2R and K into the above equation, we get:

[0055] V I =(b0) B *2 0 +b1 B *2 1 +……+b m-1 B *2 m-1 )*V REF / 2 n .

[0056] Where V I This represents the low-order binary code b0. B ~b m B The analog output voltage generated under control.

[0057] According to the superposition theorem, binary codeword b0 B ~b n-1 B The resulting analog output voltage, i.e., the output voltage obtained by the digital-to-analog converter provided in this embodiment, is:

[0058] V OUT =V1=(b0) B *2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 2 +...+b n-2 B *2 n-2 +b n-1 B *2 n-1 )*V REF / 2 n .

[0059] The digital-to-analog converter with an R-2R structure provided in this embodiment splits the leftmost 2R resistor in the traditional R-2R architecture into an R resistor and an unchanged 2... m A small unit resistor is used, while the R-2R resistor on the right side remains unchanged, for high-order and mid-high-order codeword control. Therefore, the high-order and mid-high-order codeword control is the same as that of a traditional R-2R architecture, while the low-order control is achieved through the decoder controlling the current V. REF / 2R generates corresponding low-bit binary weighted analog voltages for the turning off and closing of all switches in the switch array. This allows for an increase in resolution to m bits on the same resistor area, improving accuracy while reducing cost.

[0060] Example 2:

[0061] This embodiment provides a digital-to-analog converter with an R-2R structure. Based on the first embodiment, it takes a voltage-type R-2R architecture digital-to-analog converter with 14 (0-13) bits of binary code as an example to improve the accuracy of 6 bits.

[0062] That is, in this embodiment, based on embodiment one, n=14, m=6, x=6, y=3.

[0063] like Figure 2As shown, it includes: a VI conversion circuit, a decoding unit 2, an R-2R ladder array circuit, a switch array circuit, and a unity-gain buffer. The R-2R ladder array circuit includes a low-order branch, a mid-high-order branch, and a high-order branch. The input terminal of the VI conversion circuit is connected to the bandgap reference voltage terminal. The output terminal of the VI conversion circuit is connected to the first input terminal of the switch array circuit. The second input terminal of the switch array circuit is connected to the control terminal of the decoding unit. The output terminal of the switch array circuit is connected to the input terminal of the low-order branch. The low-order branch, mid-high-order branch, and high-order branch are connected sequentially. The output terminal of the high-order branch is connected to the unity-gain buffer.

[0064] During operation, the middle and high-order branches and the high-order branch adopt the traditional R-2R architecture digital-to-analog converter method to control the middle and high-order codewords and the high-order codewords respectively; the low-order codeword is controlled by the decoding unit to control the current of the VI conversion circuit to generate the corresponding low-order binary weighted analog voltage. The analog voltages obtained from the low-order codeword, the middle and high-order codewords, and the high-order codeword are combined to obtain the final output analog voltage of the R-2R structure digital-to-analog converter provided in this embodiment.

[0065] The technical solution and effects of the present invention will be further illustrated below through specific circuit structures. The following examples are for the purpose of explaining the present invention, but the present invention is not limited to the following examples.

[0066] This embodiment provides an R-2R structure digital-to-analog converter to solve the problem that the number of resistors and the resistor layout area of ​​an R-2R trapezoidal resistor DAC continuously increase with the increase of resolution, thus limiting the accuracy. This allows for an increase of 6 bits of resolution to be achieved on the same resistor area.

[0067] Therefore, as Figure 1 As shown, the architecture of the VI conversion circuit is the same as that of the VI conversion circuit in Embodiment 1, and the decoding unit adopts 6-2 6 Decoder.

[0068] Among them, the switch array circuit has 63 first switches S 0,1 ~S 0,63 The lower-order branch consists of 64 small unit resistors R connected in series with the same resistance value. 0,1 ~R 0,64 Each pair of adjacent small unit resistors is connected to the output terminal of a first switch. The first input terminal of the first switch is connected to the VI conversion circuit, the second input terminal of the first switch is connected to the control terminal of the decoder, the small unit resistor at the tail end is connected to the middle and high level branch, and the small unit resistor at the head end is grounded.

[0069] Specifically, such as Figure 1 As shown, the small unit resistance R 0,1 One end is grounded, with a small unit resistance R0,1 The other end is connected to the first switch S. 0,1 Output terminal, small unit resistance R 0,2 One end is connected to the first switch S. 0,1 The input terminals are connected to the decoder and the VI conversion circuit respectively; the small unit resistor R 0,2 The other end is connected to the first switch S. 0,2 Output terminal, small unit resistance R 0,3 One end is connected to the first switch S. 0,2 The input terminals are connected to the decoder, VI conversion circuit, and so on, with the small unit resistance R... 0,63 The other end is connected to the first switch S. 0,63 Output terminal, small unit resistance R 0,64 One end is connected to the first switch S. 0,63 The input terminals are connected to the decoder and the VI conversion circuit respectively; the small unit resistor R 0,64 The other end connects to the middle and high-level branch.

[0070] The middle-high level branches and high-level circuits are R-2R trapezoidal mesh resistor networks. In this embodiment, there are 6 middle-high level branches and 3 high-level branches. Each middle-high level branch includes an R resistor, a 2R resistor, and a second switch. The 6 middle-high level output resistors together include the second switches S6-S6. 11 Each high-level branch includes a resistor R with a resistance of R and a second switch. The three high-level branches together include the second switch S. T0 -S T1 .

[0071] Specifically, such as Figure 1 As shown, the input terminal of the second switch S6 is grounded or connected to a reference voltage, and the output terminal of the second switch S6 is connected to one end of a 2R resistor. The other end of the 2R resistor is connected to one end of a resistor R, forming a high-level branch; the input terminal of the second switch S7 is grounded or connected to a reference voltage, and the output terminal of the second switch S7 is connected to one end of a 2R resistor. The other end of the 2R resistor is connected to one end of a resistor R, forming a high-level branch; ...; the second switch S T2 Input terminal grounded or reference voltage, second switch S T2 The output terminal is connected to one end of a 2R resistor, and the other end of the 2R resistor is connected to one end of an R resistor, forming a high-order branch. This process continues, with each high-order branch connected by an R resistor within another high-order branch, resulting in a total of 6 branches. The R resistor in the first high-order branch is also connected to a small unit resistor R. 0,64The other end is connected to the R resistor in the high-level branch of the 6th channel, which is also connected to the unity-gain buffer. The high-level branch is located on the far right. One end of the 2R resistor in the high-level branch is connected to the unity-gain buffer, and the other end of the 2R resistor is connected to the output terminal of the second switch. The input terminal of the second switch is grounded or connected to the reference voltage.

[0072] exist Figure 1 In this example, to represent the resistance relationship between the 2R resistor and the R resistor, the 2R resistor is represented by two R resistors connected in series. In other embodiments, the 2R resistor can be a single resistor with a resistance of 2R, or it can be a resistor unit with a resistance of 2R obtained by connecting multiple resistors with different resistance values ​​in series.

[0073] In this embodiment, the resistance of the small unit resistor is 1 / 64th of the resistance of the 2R resistor, that is: R 0,1～64 =2R / 64.

[0074] In this embodiment, the middle and high-level branches, the high-level branches, and the switches in the switch array (i.e., the first switch and the second switch) have the same structure, each including an NMOS switch, a PMOS switch, and two CMOS inverters. The resistance value of each switch represents a conducting resistance with a resistance value of R.

[0075] In this embodiment, the unity-gain buffer is a unity-gain operational amplifier. The negative input terminal of the unity-gain operational amplifier is connected to its output terminal, and the positive output terminal is connected to the output terminal of the R-2R ladder array circuit. The unity-gain buffer can increase the driving capability of the DAC, reduce the output impedance of the DAC, and make the analog output voltage of the DAC more stable.

[0076] Based on the above architecture, the output process of the digital-to-analog converter with the R-2R structure provided in this embodiment is as follows:

[0077] During operation, the middle-high and high-level branches use a traditional R-2R architecture digital-to-analog converter to control the middle-high and high-level codewords. This is achieved by controlling the second switches S6 to S7 through 2R resistors in each channel. 11 With S T0 ~S T2 At reference voltage V REF Switching between ground and high-order bits generates analog voltages with binary weights in the high and mid-high order bits. The VI conversion circuit uses an operational amplifier clamp to generate V. REF / 2R current, the low-order codeword is controlled by the decoder current V REF / 2R pairs the first switch S in the switch array 0,1 ~S 0,63 The switching on and off of the circuit generates analog voltages with corresponding low-order binary weights.

[0078] Specifically:

[0079] In this embodiment, the low-order resistance ladder control codeword b0 obtained by the low-order branch is... B ~b5 B The code is a binary code, and the high-order resistance ladder control codeword b1 obtained from the high-order branch is... T ~b3 T For the thermometer code, the control code b6 for the resistance ladder obtained from the middle and high-level branch is... B ~b 11 B It is in binary code.

[0080] When the thermometer code b1 T ~b3 T When it is 1, switch S T0 ~S T2 Switch to V REF At one end, when the thermometer code b1 T ~b3 T When it is 0, switch S T0 ~S T2 Switch to ground, thermometer code b1 T ~b3 T With the high-order binary code b 12 B ~b 13 B The relationship is:

[0081] b1 T =b 12 B +b 13 B b2 T =b 12 B b3 T =b 12 B *b 13 B .

[0082] Among them, the high-order binary code b6 B ~b 11 B When the value is 1, switches S6 to S7 11 Switch to V REF One end, with the high-order binary code b6 B ~b 11 B When the value is 0, switches S6 to S7 11 Switch to ground.

[0083] The high-order binary code and the middle-high-order binary code control the switch array S6~S 11 With S T0 ~S T2The generated analog voltage is consistent with the traditional R-2R architecture, as follows:

[0084] V R-2R = (b6) B *2 0 +b7 B *2 1 +b8 B *2 2 +b9 B *2 3 +b 10 B *2 4 +b 11 B *2 5 +b 12 B *2 6 +b 13 B *2 7 )*V REF / 2 8 .

[0085] Among them, V R-2R For the R-2R architecture itself, by switching the resistor ladder to V REF Or the analog voltage generated at the output terminal V1, b6 B ~b 13 B For the 6th to 13th bits of the DAC's binary codeword, V REF The reference voltage can typically be generated by the internal reference bandgap module of the chip, or it can be provided by an external reference voltage source.

[0086] In this embodiment, the decoding unit is a 6-64 decoder, which decodes the 0th to 5th bits of the binary codeword b0. B ~b5 B Converting to a 64-choose-1 codeword, makes S 0,1 ~S 0,63 The Kth switch S in the switch array 0,n When the switch is closed, all other switches are open, where K represents the switch number in the switch array, K = 1, 2, ..., 63. Therefore, b0 B ~b5 B The relationship with K is:

[0087] K = b0 B *2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 3 +b4 B *24 +b5 B *2 5 .

[0088] When M = 0, S 0,1 ~S 0,63 All switches in the switch array are open.

[0089] Low-order binary code b0 B ~b5 B The switch array S is controlled by a 6-64 decoding module. 0,1 ~S 0,63 The turn-off and turn-on regulation of the VI conversion module output current is injected into the low-order branch R. 0,1 ~R 0,64 The position thus generates a low-bit binary weighted analog voltage.

[0090] Using the reciprocity theorem, in a linear circuit containing only one current source and no controlled sources, if the positions of the current source and the voltmeter are interchanged, the voltmeter reading remains unchanged. For example... Figure 3 As shown, the output current injection position of the VI conversion circuit is interchanged with the output position of the R-2R trapezoidal array circuit. Based on the characteristics of the R-2R trapezoidal resistor, the current falls in the lower branch R. 0,1 ~R 0,64 The current on it is 1 / 256I, where I represents the output current of the VI conversion circuit.

[0091] And: V I = (1 / 256I)n*2R / 64.

[0092] Let I = V REF Substituting the formulas for / 2R and K into the above equation, we get:

[0093] V I =(b0) B *2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 3 +b4 B *2 4 +b5 B *2 5 )*V REF / 2 14 .

[0094] Where V I This represents the low-order binary code b0. B ~b5 B The analog output voltage generated under control.

[0095] According to the superposition theorem, binary codeword b0 B ~b 13 B The resulting analog output voltage, i.e., the output voltage obtained by the digital-to-analog converter provided in this embodiment, is:

[0096] V OUT =V1=(b0) B *2 0 +b1 B *2 1 +b2 B *2 2 +b3 B *2 2 +...+b 12 B *2 12 +b 13 B *2 13 )*V REF / 2 14 .

[0097] The R-2R structure digital-to-analog converter provided in this embodiment splits the leftmost 2R resistor in the traditional R-2R architecture into an R resistor and 64 small unit resistors that remain unchanged, while the R-2R resistor on the right side remains unchanged, for high-order and mid-high-order codeword control. Therefore, the control of the high-order and mid-high-order codewords is the same as that of the traditional R-2R architecture, and the control of the low-order bits is achieved by controlling the current V through the decoder. REF / 2R to switch array S 0,1 ~S 0,63 The switching on and off of the resistor generates corresponding low-order binary weighted analog voltages. This allows for a 6-bit increase in resolution within the same resistor area, improving accuracy while reducing cost.

[0098] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Other variations and modifications are possible without departing from the technical solutions described in the claims.

Claims

1. An R-2R structure digital-to-analog converter, characterized by, The application relates to a circuit comprising an R-2R ladder circuit and a switch array circuit, the R-2R ladder circuit comprising a low-bit branch, the low-bit branch comprising M small unit resistors connected in series and having the same resistance, the switch array circuit being connected with a V-I conversion circuit and a decoding unit at the input end and connected with the input end of the low-bit branch at the output end, and the input end of the V-I conversion circuit being connected with a reference voltage.

2. The R-2R structure digital-to-analog converter according to claim 1, wherein, The switch array circuit comprises M-1 first switches, the output end of each first switch being connected between every two adjacent small unit resistors, the first input end of each first switch being connected with the output end of the V-I conversion circuit, and the second input end of each first switch being connected with the control end of the decoding unit.

3. The R-2R structure digital-to-analog converter according to claim 1, wherein, The application further comprises a unit gain buffer, the positive input end of the unit gain buffer being connected with the output end of the R-2R ladder circuit, and the negative input end of the unit gain buffer being connected with the output end of the unit gain buffer.

4. The R-2R structure digital-to-analog converter of claim 1, wherein, The R-2R ladder circuit comprises x middle high-bit branches and y high-bit branches, each middle high-bit branch comprising a switch and an R-2R resistor unit, and each high-bit branch comprising a switch and a resistor with a resistance of 2R.

5. The R-2R structure digital-to-analog converter according to claim 1, wherein, The V-I conversion circuit comprises a first conversion circuit and a second conversion circuit, the input end of the first conversion circuit being connected with the output end of a first operational amplifier, the positive input end of the first operational amplifier being connected with a reference voltage, the output end of the first operational amplifier being grounded, the output end of the first conversion circuit being connected with the positive input end of a second operational amplifier, and the input end of the second conversion circuit being connected with the output end of the second operational amplifier.

6. The R-2R structure digital-to-analog converter according to claim 5, wherein, The first conversion circuit comprises a first N-type field effect transistor, the second conversion circuit comprises a second N-type field effect transistor, the gate of the first N-type field effect transistor being connected with the output end of the first operational amplifier, the drain of the first N-type field effect transistor being connected with the positive input end of the second clamping operational amplifier, the negative input end of the second clamping operational amplifier being connected with the drain of the second N-type field effect transistor, the gate of the second N-type field effect transistor being connected with the output end of the second clamping operational amplifier, and the drain of the second N-type field effect transistor being connected with the first input end of the switch array circuit.

7. The R-2R structure digital-to-analog converter according to claim 6, wherein, The conversion circuit further comprises four resistors with the same resistance R, one end of a first resistor being connected with a power supply, the other end of the first resistor being connected with the drain of the first N-type field effect transistor, one end of a second resistor being connected with the source of the first N-type field effect transistor, the other end of the second resistor being connected with one end of a third resistor, the other end of the third resistor being grounded, one end of a fourth resistor being connected with the power supply, and the other end of the fourth resistor being connected with the drain of the second N-type field effect transistor.

8. The R-2R structure digital-to-analog converter according to claim 3, wherein, The unit gain buffer is a unit gain operational amplifier.

9. The R-2R structure digital-to-analog converter according to any one of claims 1-8, characterized in that, It comprises 6 middle-high bit branches and 3 high bit branches; the low bit branch comprises 64 small unit resistors with same resistance value connected in series and 63 first switches, a control end of each first switch is connected between every two adjacent small unit resistors, a first input end of each first switch is connected with an output end of a V-I conversion circuit, and a second input end of each first switch is connected with a control end of a decoding unit.

10. The R-2R structure digital-to-analog converter of claim 9, wherein, The decoding unit is a decoder.

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