Integrated circuit

Abstract

An integrated circuit includes a front-side power rail in a front-side metal layer over a substrate, a back-side signal line in a first back-side metal layer under the substrate, a back-side power rail in a second back-side metal layer under the first back-side metal layer, and a back-side via connection through the substrate. The first front-side power rail and the first back-side via connection are conductively connected to a source terminal of the first-type transistor. A second front-side power rail and a second back-side via connection are conductively connected to a source terminal of the second-type transistor. The first extension via connector is directly connected between the first backside via connector and the first backside power rail. The second extension via connection is directly connected between the second backside via connection and the second backside power rail.

Description

Technical Field

[0001] An embodiment of this utility model relates to an integrated circuit. Background Technology

[0002] The latest trend in miniaturized integrated circuits (ICs) has resulted in smaller components that consume less power but deliver more functionality at higher speeds. Miniaturization processes also bring more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits, while ensuring compliance with standard cell layout design and manufacturing specifications. Utility Model Content

[0003] This utility model embodiment provides an integrated circuit comprising: a first type of active region structure and a second type of active region structure each extending along a first direction on a substrate; a first terminal conductor intersecting the first type of active region structure at the source region of the first type of transistor; a second terminal conductor intersecting the second type of active region structure at the source region of the second type of transistor; a first front power rail and a second front power rail each extending along the first direction and located in a front metal layer above the first type of active region structure and the second type of active region structure; a back-side signal line located in a first back-side metal layer below the substrate; a first back-side power rail and a second back-side power rail each extending along the first direction and located in a second back-side metal layer below the first back-side metal layer; a first back-side via connector conductively connected to the source region of the first type of transistor; a first extended via connector directly connected between the first back-side via connector and the first back-side power rail; a second back-side via connector conductively connected to the source region of the second type of transistor; and a second extended via connector directly connected between the second back-side via connector and the second back-side power rail.

[0004] In some embodiments, the integrated circuit further includes: a first front-side via connector directly connected between the first terminal conductor and the first front-side power rail; and a second front-side via connector directly connected between the second terminal conductor and the second front-side power rail. In some embodiments, the integrated circuit further includes: a third terminal conductor intersecting the first type of active region structure or the second type of active region structure at the drain region of the transistor; and a third back-side via connector directly connected between the third terminal conductor and the back-side signal line. In some embodiments, the integrated circuit further includes: a gate conductor intersecting the first type of active region structure or the second type of active region structure at the channel region of the transistor; and a third back-side via connector directly connected between the gate conductor and the back-side signal line. In some embodiments, the back-side signal line is a two-dimensional signal line having a first signal segment extending along the first direction and a second signal segment extending along a second direction perpendicular to the first direction.

[0005] This utility model embodiment provides an integrated circuit including: a first type of active region structure and a second type of active region structure each extending along a first direction on a substrate; a first front power rail and a second front power rail each extending along the first direction and located in a front metal layer above the first type of active region structure and the second type of active region structure; a back-side signal line located in a first back-side metal layer below the substrate; a first back-side power rail and a second back-side power rail each extending along the first direction and located in a second back-side metal layer below the first back-side metal layer; and a multi-level cell having a first logic gate and a second... A logic gate, wherein a first logic gate and a second logic gate are connected in series between the input terminal of the first logic gate and the output terminal of the second logic gate, such that the input terminal of the second logic gate is configured to receive a logic signal from the output terminal of the first logic gate; a first type of transistor in the multi-level unit has a source region in a first type of active region structure, the source region being conductively connected to a first back-side power rail through one or more through-hole connectors; and a second type of transistor in the multi-level unit has a source region in a second type of active region structure, the source region being conductively connected to a second back-side power rail through one or more through-hole connectors.

[0006] In some embodiments, the integrated circuit further includes: a first back-side via connector conductively connected to the source region of the first type of transistor; a first extended via connector directly connected between the first back-side via connector and the first back-side power rail; a second back-side via connector conductively connected to the source region of the second type of transistor; and a second extended via connector directly connected between the second back-side via connector and the second back-side power rail. In some embodiments, the multi-level cell has a first vertical cell boundary and a second vertical cell boundary extending in a second direction perpendicular to the first direction, and wherein each of the first vertical cell boundary and the second vertical cell boundary passes through a first boundary isolation region in the first type of active region structure and a second boundary isolation region in the second type of active region structure. In some embodiments, the integrated circuit further includes: a single-stage unit, wherein the single-stage unit is a buffer unit, an inverter unit, a NAND unit, a NOR unit, an AND unit, or an OR unit, and wherein the single-stage unit includes: a second first-type transistor having a source region located in the first-type active region structure and conductively connected to the first front-side power rail; a first back-side power line located in the first back-side metal layer and electrically connected to the source region of the second first-type transistor; a second second-type transistor having a source region located in the second-type active region structure and conductively connected to the second front-side power rail; and a second back-side power line located in the first back-side metal layer and electrically connected to the source region of the second second-type transistor. In some embodiments, the integrated circuit further includes: a first back-side via connector conductively connecting the first back-side power line and the source region of the second first-type transistor; and a second back-side via connector conductively connecting the second back-side power line and the source region of the second second-type transistor. In some embodiments, the integrated circuit further includes: a power pickup unit, wherein the power pickup unit does not contain transistors or each transistor therein is implemented as a dummy transistor, and the power pickup unit includes: a first terminal conductor intersecting the first type of active region structure; a first front-side via connector directly connected between the first terminal conductor and the first front-side power rail; and a first back-side via connector conductively connected between the first terminal conductor and the first back-side power rail. In some embodiments, the power pickup unit further includes: a first back-side conductor formed in the first back-side metal layer, wherein the first back-side via connector is conductively connected to the first back-side power rail through the first back-side conductor. In some embodiments, the power pickup unit further includes: a first extended via connector directly connected between the first back-side via connector and the first back-side power rail.In some embodiments, the power pickup unit further includes: a second terminal conductor intersecting the second type of active region structure; a second front-side via connector directly connected between the second terminal conductor and the second front-side power rail; and a second back-side via connector conductively connected between the second terminal conductor and the second back-side power rail. In some embodiments, the power pickup unit has a first vertical cell boundary and a second vertical cell boundary extending in a second direction perpendicular to the first direction, wherein each of the first vertical cell boundary and the second vertical cell boundary passes through a first boundary isolation region in the first type of active region structure and a second boundary isolation region in the second type of active region structure. In some embodiments, the multi-level cell includes a plurality of gate conductors extending in a second direction below the front metal layer, and two adjacent gate conductors are separated by a spacing distance equal to the contact polysilicon pitch (CPP), wherein the power pickup unit has a cell width equal to or less than four CPPs. In some embodiments, the power pickup unit further includes: a third terminal conductor intersecting with one of the first type of active region structure or the second type of active region structure; a third front through-hole connector directly connecting the third terminal conductor to one of the first front power rail or the second front power rail; and a first back through-hole connector conductively connected between the third terminal conductor and one of the first back power rail and the second back power rail. Attached Figure Description

[0007] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a layout diagram of an integrated circuit having a front power rail and a back power rail according to some embodiments.

[0009] Figures 2A to 2D and Figures 3A to 3D It is according to some embodiments along Figure 1 Cross-sectional views of integrated circuits with various cut planes.

[0010] Figure 4 This is a layout diagram of an integrated circuit having an array of back-side power rails according to some embodiments.

[0011] Figure 5 It is a layout diagram of an integrated circuit with selectively marked geometric relationships according to some embodiments.

[0012] Figures 6A to 6BThis is a layout diagram of circuit units connected to the front power rail and the rear power rail according to some embodiments.

[0013] Figures 7A to 7C This is a layout diagram of a power pickup unit according to some embodiments.

[0014] Figure 7D It is according to some embodiments along Figures 7A to 7C A cross-sectional view of the power pickup unit on the cutting plane AA'.

[0015] Figures 8A to 8B This is a layout diagram of a single-level unit in the form of a DSP unit according to some embodiments.

[0016] Figure 8C It is based on some embodiments having Figure 8A The front layout diagram is an alternative to the rear layout diagram of a single-level unit.

[0017] Figure 9 This is a layout diagram of an integrated circuit having single-level and multi-level units according to some embodiments.

[0018] Figure 10A This is another example implementation of the power pickup unit according to some embodiments.

[0019] Figure 10B It is according to some embodiments along Figure 10A A cross-sectional view of the power pickup unit on the cutting plane AA'.

[0020] Figure 11 This is a flowchart of a method for producing an integrated circuit with a back-side power rail according to some embodiments.

[0021] Figure 12 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0022] Figure 13 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0023] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0024] The following disclosure discloses numerous different embodiments or instances for implementing various features of the subject matter. The components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are also expected. For example, the following description includes embodiments where the first feature is formed on or on a second feature, wherein the first and second features are formed in direct contact, and further includes embodiments where an additional feature is formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters are repeatedly used in various instances in this disclosure. This repetition is for the purpose of brevity and clarity, and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of explanation, this document may use spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. Elements may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0026] In some embodiments, an integrated circuit includes a front-side power rail and a back-side power rail extending along a first direction. Some circuit cells in the integrated circuit include back-side signal lines formed in a first back-side metal layer (e.g., BMO) on the back side of a substrate. The front-side power rail is formed in a front-side metal layer (e.g., M0) on the front side of the substrate, while the back-side power rail is formed in a second back-side metal layer (e.g., BM1). The first back-side metal layer (e.g., BMO) is located between the second back-side metal layer (e.g., BM1) and the substrate. Each of the first front-side power rail and the first back-side power rail is configured to be maintained at a first supply voltage (e.g., VDD), and each of the second front-side power rail and the second back-side power rail is configured to be maintained at a second supply voltage (e.g., VSS).

[0027] The integrated circuit also includes a first back-side via connector, a second back-side via connector, a first extended via connector, and a second extended via connector. Each back-side via connector passes through the substrate. Each extended via connector passes through both the first back-side metal layer (e.g., BMO) and the interlayer dielectric between the first back-side metal layer (e.g., BMO) and the second back-side metal layer (e.g., BMO). The source terminal of the PMOS transistor is conductively connected to both the first front-side power rail and the first back-side via connector, and the first extended via connector is directly connected between the first back-side via connector and the first back-side via connector, thereby forming a conduction path between the first front-side power rail and the first back-side power rail. The source terminal of the NMOS transistor is conductively connected to both the second front-side power rail and the second back-side via connector, and the second extended via connector is directly connected between the second back-side via connector and the second front-side via connector, thereby forming a conduction path between the second front-side power rail and the second back-side power rail. Increasing the number of conduction paths between the front and back power rails can reduce IR drop, thereby improving the power and speed performance of integrated circuits.

[0028] Figure 1 This is a layout diagram of an integrated circuit having a front power rail and a back power rail according to some embodiments. Figure 1 The layout diagram includes specifications for p-type active region structures (82p and 84p) and n-type active region structures (82n and 84n) extending entirely along the X-direction, gate conductors (151A-159A and 151B-159B) extending entirely along the Y-direction, terminal conductors (132Ap-132Bp, 132N, 138Ap-138Bp, 138N, 134Ap-136Ap, 134An-136An, 134B, 135Bn-136Bn, and 135Bp-136Bp) extending entirely along the Y-direction, and various through-hole connectors. In the XY coordinate system, the X and Y directions are perpendicular to each other. Figure 1 In the middle, two adjacent gate conductors (e.g., gate conductors 152A and 154A) are separated by a spacing distance equal to the contact polysilicon pitch (CPP).

[0029] Figure 1 The integrated circuit includes a circuit cell 100 defined by two vertical cell boundaries 101 and 109 extending along the Y direction and two horizontal cell boundaries 102 and 108 extending along the X direction. Dummy gate conductors 151A and 151B are located at vertical cell boundary 101, and dummy gate conductors 159A and 159B are located at vertical cell boundary 109.

[0030] Figure 1The layout diagram also includes layout concept patterns for specifying the rear power rails (20A, 40A, and 20B) extending along the X direction, the front power rails (22A, 42A, and 22B) extending along the X direction, and the front signal lines (122A-126A and 122B-126B) extending along the X direction. Figure 1 In the layout concept diagram, the full length of each back-side power rail (20A, 40A, or 20B) is not directly depicted, although the vertical position of each individual back-side power rail and its width along the Y direction are faithfully specified. In fact, the length of each back-side power rail (20A, 40A, and 20B) is greater than the width of the circuit cell 100 defined by the two vertical cell boundaries 101 and 109, and each back-side power rail (20A, 40A, and 20B) extends through the vertical cell boundaries 101 and 109. Figure 4 In the example layout diagram, each back-side power rail (20A, 40A, and 20B) extends along the X direction and passes through multiple circuit units. Specifically, back-side power rail 20A extends across circuit units 410A, 410B, and 410C. Back-side power rail 40A extends across circuit units 410A, 420A, 410B, 410C, and 420C. Back-side power rail 20B extends across circuit units 420A, 410B, 430A, 430B, 420C, and 430C.

[0031] Similarly, in Figure 1 In the layout concept diagram, the full length of each front power rail (22A, 42A, or 22B) is not directly depicted, although the vertical position of each individual front power rail and its width along the Y direction are faithfully specified. Figure 1 In the layout concept pattern, the full length of each front signal line (122A-126A and 122B-126B) is not directly depicted, although the vertical position of each front signal line and the width of each front signal line along the Y direction are faithfully specified by the layout concept pattern.

[0032] Figure 1 The layout diagram also includes layout patterns for specifying backside signal lines 162 and 164. Backside signal line 164 is a one-dimensional signal line extending along the X direction. Backside signal line 162 is a two-dimensional signal line having a first signal segment 162H extending along the X direction and a second signal segment 162V extending along the Y direction.

[0033] exist Figure 1In the PMOS transistor, at least one of the gate conductors (151A-159A and 151B-159B) intersects with either the p-type active region structure 82p or 84p in the channel region. At least one of the gate conductors (151A-159A and 151B-159B) intersects with either the n-type active region structure 82n or 84n in the channel region. At least one of the terminal conductors intersects with either the p-type active region structure 82p or 84p in the source region of the PMOS transistor. At least one of the terminal conductors intersects with either the n-type active region structure 82n or 84n in the source region of the NMOS transistor. At least one of the terminal conductors intersects with either the p-type active region structure 82p or 84p in the drain region of the PMOS transistor. At least one of the terminal conductors intersects with either the n-type active region structure 82n or 84n in the drain region of the NMOS transistor.

[0034] In some embodiments, Figure 1 The various active region structures are formed by fin structures. The PMOS transistors formed in the p-type active region structures (82p and 84p) and the NMOS transistors formed in the n-type active region structures (82n and 84n) are FinFETs. In some embodiments, Figure 1 The various active region structures are formed from nanosheet structures. The PMOS transistors formed in the p-type active region structures (82p and 84p) and the NMOS transistors formed in the n-type active region structures (82n and 84n) are nanosheet transistors. In some embodiments, Figure 1 The various active region structures are formed by nanowire structures. The PMOS transistors formed in the p-type active region structures (82p and 84p) and the NMOS transistors formed in the n-type active region structures (82n and 84n) are nanowire transistors.

[0035] exist Figure 1 In integrated circuits, various active region structures are formed on the substrate. Front-side power rails and signal lines are formed on the front side of the substrate, while back-side power rails and signal lines are formed on the back side of the substrate. These are depicted in cross-sectional views along various cut planes of the integrated circuit, such as... Figures 2A-2D and Figures 3A-3D As shown.

[0036] exist Figures 2A-2D and Figures 3A-3DIn the substrate 30, p-type active region structures (82p and 84p) and n-type active region structures (82n and 84n) are formed. Each terminal conductor (132Ap-132Bp, 132N, 138Ap-138Bp, 138N, 134Ap-136Ap, 134An-136An, 134B, 135Bn-136Bn, and 135Bp-136Bp) intersects with one or more p-type active region structures (82p and 84p) and n-type active region structures (82n and 84n). Each gate conductor (151A-159A and 151B-159B) also intersects with one or more p-type active region structures (82p and 84p) and n-type active region structures (82n and 84n). The front power rails (22A, 42A, and 22B) and front signal lines (122A-126A and 122B-126B) are formed in the front metal layer M0, which is located above the terminal conductors, gate conductors, and active region structure. The back signal lines (162 and 164) are formed in the back metal layer BM0 below the substrate 30. The back power rails (20A, 40A, and 20B) are formed in the back metal layer BM1 below the back metal layer BM0.

[0037] Figure 2A It is according to some embodiments along Figure 1 A cross-sectional view of the integrated circuit with cutting plane AA'. Figure 2A In the configuration, terminal conductor 132Ap is directly connected to the front power rail 22A via front through-hole connector VD, and terminal conductor 132N is directly connected to the front power rail 42A via front through-hole connector VD. Back through-hole connector 191A is conductively connected to terminal conductor 132Ap. Terminal conductor 132Ap intersects with the p-type active region structure 82p at the source region of the PMOS transistor, and extended through-hole connector BV0 is directly connected between back through-hole connector 191A and back power rail 20A. Back through-hole connector 192A is conductively connected to terminal conductor 132N. Terminal conductor 132N intersects with the n-type active region structure 82n at the source region of the NMOS transistor, and extended through-hole connector BV0 is directly connected between back through-hole connector 192A and back power rail 40A.

[0038] Figure 2B It is according to some embodiments along Figure 1 A cross-sectional view of the integrated circuit with the cutting plane BB'. Figure 2B In the middle, the back-side signal line 162 is directly connected to the back-side through-hole connector 191B, and the back-side through-hole connector 191B is further electrically connected to the terminal conductor 134Ap that intersects with the p-type active region structure 82p.

[0039] Figure 2C It is according to some embodiments along Figure 1A cross-sectional view of the integrated circuit with the cutting plane CC'. Figure 2C In the middle, the terminal conductor 135An is directly connected to the front power rail 42A through the front through-hole connector VD.

[0040] Figure 2D It is according to some embodiments along Figure 1 A cross-sectional view of an integrated circuit with the cutting plane DD'. Figure 2D In the configuration, the back-side signal line 164 is directly connected to the back-side via connector BVG, which is further conductively connected to the gate conductor 154B. The gate conductor 154B intersects with the p-type active region structure 84p in the channel region of the PMOS transistor and with the n-type active region structure 84n in the channel region of the NMOS transistor.

[0041] Figure 3A It is according to some embodiments along Figure 1 A cross-sectional view of an integrated circuit with a cut plane PP'. Figure 3A In this configuration, the back-side via connector 191A is conductively connected to the terminal conductor 132Ap. The terminal conductor 132Ap intersects with the p-type active region structure 82p at the source region of the PMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 191A and the back-side power rail 20A. The back-side via connector 191E is conductively connected to the terminal conductor 138Ap. The terminal conductor 138Ap intersects with the p-type active region structure 82p at the source region of the PMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 191E and the back-side power rail 20A. The back-side signal line 162 is directly connected to the back-side via connector 191B, and the back-side via connector 191B is further conductively connected to the terminal conductor 134Ap, which intersects with the p-type active region structure 82p.

[0042] Figure 3B It is according to some embodiments along Figure 1 A cross-sectional view of an integrated circuit with a cut plane QQ'. Figure 3BIn this configuration, the back-side via connector 192A is conductively connected to the terminal conductor 132N. The terminal conductor 132N intersects with the n-type active region structure 82n at the source region of the NMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 192A and the back-side power rail 40A. The back-side via connector 192E is conductively connected to the terminal conductor 138N. The terminal conductor 138N intersects with the n-type active region structure 82n at the source region of the NMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 192E and the back-side power rail 40A. The back-side signal line 162 is directly connected to the back-side via connector 192D, and the back-side via connector 192D is further conductively connected to the terminal conductor 136An, which intersects with the n-type active region structure 82n.

[0043] Figure 3C It is according to some embodiments along Figure 1 A cross-sectional view of an integrated circuit with the cutting plane MM'. Figure 3C In this configuration, the back-side via connector 193A is conductively connected to the terminal conductor 132N. The terminal conductor 132N intersects with the n-type active region structure 84n at the source region of the NMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 193A and the back-side power rail 40A. The back-side via connector 193E is conductively connected to the terminal conductor 138N. The terminal conductor 138N intersects with the n-type active region structure 84n at the source region of the NMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 193E and the back-side power rail 40A. The back-side signal line 162 is directly connected to the back-side via connector 193C, and the back-side via connector 193C is further conductively connected to the terminal conductor 135Bn, which intersects with the n-type active region structure 84n.

[0044] Figure 3D It is according to some embodiments along Figure 1 A cross-sectional view of an integrated circuit with a cutting plane NN'. Figure 3DIn this configuration, the back-side via connector 194A is conductively connected to terminal conductor 132Bp. Terminal conductor 132Bp intersects with the p-type active region structure 84p at the source region of the PMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 194A and the back-side power rail 20B. The back-side via connector 194E is conductively connected to terminal conductor 138Bp. Terminal conductor 138Bp intersects with the p-type active region structure 84p at the source region of the PMOS transistor, and the extended via connector BV0 is directly connected between the back-side via connector 194E and the back-side power rail 20B. The back-side signal line 164 is directly connected to the back-side via connector 194D, which is further conductively connected to terminal conductor 136Bp, which intersects with the p-type active region structure 84p. The back-side signal line 164 is also directly connected to the back-side via connector BVG, which is further electrically connected to the gate conductor 154B.

[0045] exist Figures 3A-3B In the above, dummy gate conductors 151A and 159A are correspondingly connected to, for example... Figure 1 The vertical cell boundaries 101 and 109 shown are aligned. The boundary isolation region i151Ap in the p-type active region structure 82p and the boundary isolation region i151An in the n-type active region structure 82n are fabricated below the dummy gate conductor 151A. The boundary isolation region i159Ap in the p-type active region structure 82p and the boundary isolation region i159An in the n-type active region structure 82n are fabricated below the dummy gate conductor 159A. Figures 3C-3D In the process, dummy gate conductors 151B and 159B are correspondingly connected to, for example... Figure 1 The vertical cell boundaries 101 and 109 shown are aligned. The boundary isolation region i151Bp in the p-type active region structure 84p and the boundary isolation region i151Bn in the n-type active region structure 84n are fabricated below the dummy gate conductor 151B. The boundary isolation region i159Bp in the p-type active region structure 84p and the boundary isolation region i159Bn in the n-type active region structure 84n are fabricated below the dummy gate conductor 159B.

[0046] Figure 1 The vertical cell boundary 101 of the circuit cell 100 is defined by the isolation regions i151Ap, i151An, i151Bn and i151Bp. Figure 1 The vertical cell boundary 109 of the circuit cell 100 is defined by isolation regions i159Ap, i159An, i159Bn and i159Bp.

[0047] Each p-type active region structure 82p and 84p includes the active regions (e.g., source, drain, and channel regions) of one or more PMOS transistors. Each n-type active region structure 82n and 84n includes the active regions (e.g., source, drain, and channel regions) of one or more NMOS transistors. Figure 3A In this circuit, boundary isolation regions i151Ap and i159Ap isolate the active regions of the PMOS transistors in circuit unit 100 (in the p-type active region structure 82p) from the active regions of other PMOS transistors in adjacent circuit units. Figure 3B In this circuit, boundary isolation regions i151An and i159An isolate the active regions of the NMOS transistors in circuit unit 100 (in the n-type active region structure 82n) from the active regions of other NMOS transistors in adjacent circuit units. Figure 3C In this circuit, boundary isolation regions i151Bn and i159Bn isolate the active regions of the NMOS transistors in circuit unit 100 (in the n-type active region structure 84n) from the active regions of other NMOS transistors in adjacent circuit units. Figure 3D In the circuit, boundary isolation regions i151Bp and i159Bp isolate the active regions of the PMOS transistors in circuit unit 100 (in the p-type active region structure 84p) from the active regions of other PMOS transistors in adjacent circuit units.

[0048] exist Figure 1 In this embodiment, circuit unit 100 is a dual-height unit, implemented by two parallel-positioned p-type active region structures (i.e., 82p and 84p) and two parallel-positioned n-type active region structures (i.e., 82n and 84n), with each vertical unit boundary 101 and 109 passing through four isolation regions. In some other embodiments, circuit unit 100 is a single-height unit, implemented by one p-type active region structure and one n-type active region structure, and thus the vertical unit boundary of the single-height unit passes through two isolation regions. That is, the vertical unit boundary of the single-height unit passes through one isolation region of the p-type active region structure and one isolation region of the n-type active region structure.

[0049] Figure 1 The integrated circuit shown contains only one circuit cell 100, which is connected to the back-side power rails 20A, 40A, and 20B. Integrated circuits typically include multiple circuit cells located in one or two cell rows, and the integrated circuit comprises multiple cell rows.

[0050] Figure 4This is a layout diagram of an integrated circuit having an array of back-side power rails according to some embodiments. The integrated circuit includes back-side power rails 20A-20D and back-side power rails 40A-40C. Each back-side power rail is formed in a second back-side metal layer BM1, which is located below a first metal layer BM0 on the back side of a substrate. Each back-side power rail 20A-20D is configured to receive a first supply voltage (e.g., an upper supply voltage VDD), and each back-side power rail 40A-40C is configured to receive a second supply voltage (e.g., a lower supply voltage VSS). Figure 4 The integrated circuit also includes back-side signal lines formed in the first metal layer BMO and includes various circuit units. The back-side signal lines formed in the first metal layer BMO include 462A-462C, 463A-463C, 464A, 465A-465B, 466A, and 467A-467C. Figure 4 The integrated circuits in the circuit include circuit units 410A-410C, 420A, 420C, 430A-430C, 440A, 450A-450C, 460A, and 460C.

[0051] Circuit units 410A, 410C, 420A, 420C, 430A-430C, 440A, 450A, 450C, 460A, and 460C are single-height units. Circuit units 410B and 450B are dual-height units. Rear power rail 20A is conductively connected to circuit units 420A-410C. Rear power rail 40A is conductively connected to circuit units 410A-410C, 420A, and 420C. Rear power rail 20B is conductively connected to circuit units 420A, 410B, 420C, and 430A-430C. Rear power rail 40B is conductively connected to circuit units 430A-430C and 440A. Rear power rail 20C is conductively connected to circuit units 440A and 450A-450C. The rear power rail 40C is conductively connected to circuit units 450A-450C, 460A, and 460C. The rear power rail 20D is conductively connected to circuit units 460A, 450B, and 460C.

[0052] Figure 5 It is a layout diagram of an integrated circuit with selectively marked geometric relationships according to some embodiments. Figure 5 and Figure 1 The layout diagrams that share some common layout components are for the same layout design of integrated circuits. Figure 5 and Figure 1Circuit cell 100 is a double-height cell. The cell height of a double-height cell is twice the cell height (i.e., Cell-Height) of a single-height cell. The width of each rear power rail (20A, 40A, and 20B) is “BM1_W”, and the spacing between two adjacent rear power rails is “BM1_S”. The single cell height (Cell-Height) satisfies the following equation: Cell-Height = BM1_W + BM1_S. The width of each front power rail (22A, 42A, and 22B) is “BM1_W”, and the spacing between two adjacent front power rails is “M0_PG_W”. The spacing between two front signal lines (e.g., 122A-126A) is “M0_pitch”, and the spacing between the front signal line and the front power rail is “M0_S”. The cell height satisfies the following formula: Cell Height = M0_PG_W + M0_S + n * M0_pitch, where the integer "n" is the number of front signal lines between two adjacent front power rails. Figure 5 and Figure 1 In the example, there are three front signal lines between two adjacent front power rails.

[0053] exist Figure 5 and Figure 1 In the layout diagram, the width of each active region structure (e.g., p-type active region structure 82p or n-type active region structure 82n) is "OD_W", and the space between two adjacent n-type active region structures (e.g., 82n and 84n) is "OD_S". The width "BM1_W" of the back-side power rail 40A satisfies the following formula: BM1_W >= OD_S + 2*(0.5*OD_W). In some embodiments, the width of the back-side via connector (e.g., 191B, 183C, 192D, or 194D) is equal to the width "OD_W" of the active region structure, and the width of the back-side via connector BVG (e.g., the back-side via connector BVG conductively connected to the gate conductor 154B) is also equal to the width "OD_W" of the active region structure.

[0054] Figures 6A to 6B This is a layout diagram of a circuit unit 600 connected to the front power rail and the rear power rail according to some embodiments. Figure 6A The front layout diagram includes layout patterns for specifying p-type active region structures 82p and n-type active region structures 82n extending along the X direction, terminal conductors 632p-638p and 632-638n extending along the Y direction, and front power rails 22A and 42A extending along the X direction. Figure 6AThe front layout diagram also includes layout patterns for specifying dummy gate conductors 651 and 659. Dummy gate conductor 651 is located at the first vertical cell boundary of circuit cell 600, while dummy gate conductor 659 is located at the second vertical cell boundary of circuit cell 600. Each active region structure has an isolation region (below dummy gate conductors 651 and 659) that isolates the active region of the transistor in circuit cell 600 from the active regions of other transistors in adjacent circuit cells.

[0055] Figure 6B The backside layout includes a pattern for specifying backside power rails 20A and 40A extending along the X direction, backside signal lines 662 extending along the X direction, backside through-hole connectors (694A and 694B), and extended through-hole connectors (684A and 684B). The backside signal lines 662 are formed in a first backside metal layer beneath the substrate. The backside power rails 20A and 40A are formed in a second backside metal layer beneath the first backside metal layer.

[0056] exist Figure 6A In this configuration, front power rail 22A is configured to maintain at the upper supply voltage VDD, while front power rail 42A is configured to maintain at the lower supply voltage VSS. Terminal conductor 634p intersects with the p-type active region structure 82p at the source region of the PMOS transistor and is connected to front power rail 22A. Each terminal conductor 632n and 638n intersects with the n-type active region structure 82n at the source region of the NMOS transistor and is connected to front power rail 42A. Figure 6A Each terminal conductor 632p, 635p, and 638p intersects with the p-type active region structure 82p at the source or drain region of the PMOS transistor.

[0057] exist Figure 6B In this configuration, back-side power rail 20A is configured to be maintained at the upper supply voltage VDD, while back-side power rail 40A is configured to be maintained at the lower supply voltage VSS. Each terminal conductor 632p, 635p, and 638p is connected to the back-side signal line 662 via one of back-side via connectors 692A, 692B, and 692C, respectively. Terminal conductor 632n is conductively connected to a back-side via connector 694A that passes through the substrate. Back-side via connector 694A is further connected to back-side power rail 40A via an extension via connector 684A. Terminal conductor 638n is conductively connected to a back-side via connector 694B that passes through the substrate. Back-side via connector 694B is further connected to back-side power rail 40A via an extension via connector 684B.

[0058] In circuit unit 600, each terminal conductor 632n and 638n is conductively connected to both the front power rail 42A and the back power rail 40A. Each conductive connection from the front power rail 42A to the back power rail 40A via a terminal conductor (e.g., via terminal conductor 632n or via terminal conductor 638n) forms a conduction path between the front power rail 42A and the back power rail 40A. Increasing the number of conduction paths between the front power rail 42A and the back power rail 40A reduces the IR voltage drop between them, thereby improving the performance of the integrated circuit having circuit unit 600.

[0059] Similarly, the conductive connection from the front power rail 22A to the back power rail 20A via the terminal conductor will form a conductive path between the front power rail 22A and the back power rail 20A. Increasing the number of conductive paths between the front power rail 22A and the back power rail 20A can reduce the IR voltage drop between them. However, in circuit unit 600, the conductive connection from the front power rail 22A to the back power rail 20A is not formed via the terminal conductor 634p. Figures 6A to 6B In the specific embodiment of the circuit unit 600 shown, due to some design rule restrictions caused by the positioning of the back-side signal line 662, the terminal conductor 634p is not connected to the back-side power rail 20A through one or more back-side through-hole connectors below the terminal conductor 634p.

[0060] In some embodiments, the layout design of the circuit cells (e.g., circuit cell 600) is optimized to increase the number of conduction paths from the front power rail 42A to the back power rail 40A or from the front power rail 22A to the back power rail 20A. In some embodiments, increasing the number of conduction paths between the front power rail and the corresponding back power rail can improve the performance of an integrated circuit having the optimized circuit cells.

[0061] In the layout of an integrated circuit, multiple functional circuit units are typically located in one or two cell rows, and the integrated circuit comprises multiple cell rows. Dummy cells are positioned along one or two cell rows in some layout area between multiple functional circuit units. A functional circuit includes at least one logic gate or at least one analog circuit configured to have a second signal at an output node in response to a first signal at an input node. In some embodiments, dummy cells are implemented as fill cells or power pickup cells. Dummy cells (e.g., power pickup cells) do not contain transistors, or each transistor is included in a dummy cell to function as a dummy transistor. Dummy transistors do not receive any time-varying signal at their gate, or do not transmit signals as time-varying signals to other components at their drain or source. Dummy cells contain non-functional logic gates. A functional logic gate is a logic gate that generates a time-varying logic output signal in response to a time-varying logic input signal received at an input. An example implementation of a power pickup cell is illustrated in... Figures 7A-7C The layout diagram.

[0062] Figures 7A to 7C This is a layout diagram of a power pickup unit according to some embodiments. Figures 7A-7C Each front-side layout includes a layout pattern for specifying p-type active region structures 82p and n-type active region structures 82n extending along the X direction, front-side power rails 22A and 44A extending along the X direction, dummy gate conductors 751 and 759 extending along the Y direction, and various terminal conductors extending along the Y direction.

[0063] The dummy gate conductor 751 is located at the boundary of the first vertical cell, while the dummy gate conductor 759 is located at the boundary of the second vertical cell. Each active region structure has an isolation region (below the dummy gate conductors 751 and 759) that isolates the active region of the transistor in the power pickup cell from the active regions in adjacent circuit cells. Figure 7A The power pickup unit in the middle has a cell width of one CPP. Figure 7B The power pickup unit in the middle has a unit width of two CPPs. Figure 7B The power pickup unit in the middle has a unit width of two CPPs, and Figure 7C The cell width has a cell width of four CPPs.

[0064] exist Figure 7A In the front layout diagram, terminal conductor 732p intersects with p-type active region structure 82p, and terminal conductor 732n intersects with n-type active region structure 82n. Figure 7B In the front layout diagram, each terminal conductor 732p-734p intersects with the p-type active region structure 82p, and each terminal conductor 732n-734n intersects with the n-type active region structure 82n. Figure 7CIn the front layout diagram, each terminal conductor 732p-738p intersects with the p-type active region structure 82p, and each terminal conductor 732n-738n intersects with the n-type active region structure 82n.

[0065] Figures 7A-7C Each backside configuration includes a layout pattern specifying backside power rails 20A and 40A extending along the X direction, various backside via connectors, and various extended via connectors located on the backside of the substrate. Backside power rails 20A and 40A are formed in a second backside metal layer, which lies beneath a first backside metal layer on the backside of the substrate. Each backside via connector passes through the substrate. Each extended via connector directly connects one of the backside power rails 20A and 40A to one of the backside via connectors.

[0066] exist Figures 7A-7B In the configuration, front power rail 22A is configured to maintain a first supply voltage (e.g., VDD), and front power rail 42A is configured to maintain a second supply voltage (e.g., VSS). Rear power rail 20A is configured to maintain a first supply voltage (e.g., VDD), and rear power rail 40A is configured to maintain a second supply voltage (e.g., VSS).

[0067] Figures 7A-7C In this configuration, the front power rail 22A is conductively connected to the terminal conductor 732p, and the rear through-hole connector 792A is also conductively connected to the terminal conductor 732p. The extended through-hole connector 782A is directly connected between the rear through-hole connector 792A and the rear power rail 20A. The front power rail 42A is conductively connected to the terminal conductor 732n, and the rear through-hole connector 792B is also conductively connected to the terminal conductor 732n. The extended through-hole connector 782B is directly connected between the rear through-hole connector 792B and the rear power rail 40A.

[0068] In addition, Figures 7B-7C In this configuration, the front power rail 22A is conductively connected to the terminal conductor 734p, and the rear through-hole connector 794A is also conductively connected to the terminal conductor 734p. The extended through-hole connector 784A is directly connected between the rear through-hole connector 794A and the rear power rail 20A. The front power rail 42A is conductively connected to the terminal conductor 734n, and the rear through-hole connector 794B is also conductively connected to the terminal conductor 734n. The extended through-hole connector 784B is directly connected between the rear through-hole connector 794B and the rear power rail 40A.

[0069] In addition, Figure 7CIn this configuration, the front power rail 22A is conductively connected to terminal conductor 736p, and the rear through-hole connector 796A is also conductively connected to terminal conductor 736p. An extended through-hole connector 786A is directly connected between the rear through-hole connector 796A and the rear power rail 20A. The front power rail 42A is conductively connected to terminal conductor 736n, and the rear through-hole connector 796B is also conductively connected to terminal conductor 736n. The extended through-hole connector 786B is directly connected between the rear through-hole connector 796B and the rear power rail 40A. The front power rail 22A is conductively connected to terminal conductor 738p, and the rear through-hole connector 798A is also conductively connected to terminal conductor 738p. The extended through-hole connector 788A is directly connected between the rear through-hole connector 798A and the rear power rail 20A. The front power rail 42A is conductively connected to the terminal conductor 738n, and the rear through-hole connector 798B is also conductively connected to the terminal conductor 738n. The extended through-hole connector 788B is directly connected between the rear through-hole connector 798B and the rear power rail 40A.

[0070] Figure 7D It is according to some embodiments along Figures 7A to 7C A cross-sectional view of the power pickup unit on the cutting plane AA'. Figure 7D In this configuration, a conductive path passing through terminal conductor 732p is formed between the front power rail 22A and the rear power rail 20A. Specifically, the front power rail 22A is connected to terminal conductor 732p via front through-hole connector VD, and terminal conductor 732p makes conductive contact with the active region P-EPI of the p-type active region structure 82p. The rear through-hole connector 792A is connected to the active region P-EPI of the p-type active region structure 82p, and the extended through-hole connector 782A is directly connected between the rear through-hole connector 792A and the rear power rail 20A. Similarly, in Figure 7D In this configuration, a conductive path passing through the terminal conductor 732n is formed between the front power rail 42A and the rear power rail 40A. Specifically, the front power rail 42A is connected to the terminal conductor 732n via the front through-hole connector VD, and the terminal conductor 732n makes conductive contact with the active region N-EPI of the n-type active region structure 82n. The rear through-hole connector 792B is connected to the active region N-EPI of the n-type active region structure 82n, and the extended through-hole connector 782B is directly connected between the rear through-hole connector 792B and the rear power rail 40A.

[0071] exist Figures 7A-7C In each power pickup unit, one or more conduction paths are formed between the front power rail 22A and the back power rail 20A, and one or more conduction paths are formed between the front power rail 42A and the back power rail 40A. Increasing the number of power pickup units in the integrated circuit can reduce the IR voltage drop between the front power rail and the back power rail, thereby improving the performance of the integrated circuit.

[0072] exist Figure 7A In the power pickup unit, a conductive path passing through terminal conductor 732p is formed between the front power rail 22A and the back power rail 20A, and a conductive path passing through terminal conductor 732n is formed between the front power rail 42A and the back power rail 40A. Figure 7B In the power pickup unit, two conduction paths (corresponding to those passing through terminal conductors 732p-734p) are formed between the front power rail 22A and the rear power rail 20A, and two conduction paths (corresponding to those passing through terminal conductors 732n-734n) are formed between the front power rail 42A and the rear power rail 40A. Figure 7C In the power pickup unit, four conduction paths (corresponding to those passing through terminal conductors 732p-738p) are formed between the front power rail 22A and the rear power rail 20A, and four conduction paths (corresponding to those passing through terminal conductors 732p-738p) are formed between the front power rail 42A and the rear power rail 40A.

[0073] exist Figures 7A-7C and Figure 7D In this embodiment, at least one conductive path between the front power rail and the rear power rail is implemented using an extended through-hole connector directly connected to the rear through-hole connector and the rear power rail. In some alternative embodiments, the conductive path between the front power rail and the rear power rail is implemented using a rear conductor in a first rear metal layer. One rear through-hole connector is conductively connected between the front power rail and the rear conductor, while another rear through-hole connector is conductively connected between the rear conductor and the rear power rail.

[0074] exist Figures 7A-7C and Figure 7D In this embodiment, each power pickup unit has at least one conductive path between the front power rail 22A and the rear power rail 20A, and at least one conductive path between the front power rail 22A and the rear power rail 40A. In some alternative embodiments, the power pickup unit has at least one conductive path between the front power rail 22A and the rear power rail 20A, but can be implemented using any conductive path between the front power rail 22A and the rear power rail 40A. In some alternative embodiments, the power pickup unit has at least one conductive path between the front power rail 22A and the rear power rail 40A, but can be implemented using any conductive path between the front power rail 22A and the rear power rail 20A.

[0075] In some integrated circuit layout designs, single-level cells are implemented as dual-side power supply cells (DSP cells) with back-side power lines in a first back-side metal layer (e.g., BMO) beneath the substrate, while multi-level cells are implemented with back-side signal lines in the first back-side metal layer (e.g., BMO) and with back-side power rails in a second back-side metal layer (e.g., BMO) below the first back-side metal layer (e.g., BMO). Examples of single-level cells include buffer cells, inverter cells, NAND cells, NOR cells, AND cells, or OR cells. Examples of multi-level cells include AND-OR-invert (AOI), flipflops, or multiple single-level gates connected in series. In one example, a multi-level cell is formed by three inverters connected in series to perform an inverter function. In some embodiments, a multi-level cell includes a first logic gate and a second logic gate connected in series between the input of a first logic gate and the output of a second logic gate, such that the input of the second logic gate is configured to receive a logic signal from the output of the first logic gate.

[0076] Figures 8A to 8B This is a layout diagram of a single-stage cell 800 in the form of a DSP cell according to some embodiments. The DSP cell has back-side power lines 862 and 864 in a back-side metal layer BMO beneath the substrate. Figures 8A-8B The single-level cell 800 in the diagram is an implementation of the NAND gate.

[0077] exist Figure 8A In the front layout diagram, terminal conductors 832p-834p and 836p-838p intersect with the p-type active region structure 82p; terminal conductors 832n-834n and 836n-838n intersect with the n-type active region structure 82n; and terminal conductor 835 intersects with both the p-type and n-type active region structures 82p and 82n. Gate conductor gA1 intersects with the p-type and n-type active region structures 82p and 82n respectively at the channel regions of PMOS transistor TA1p and NMOS transistor TA1n. Gate conductor gB1 intersects with the p-type and n-type active region structures 82p and 82n respectively at the channel regions of PMOS transistor TB1p and NMOS transistor TB1n. Gate conductor gB2 intersects with p-type active region structure 82p and n-type active region structure 82n respectively in the channel regions of PMOS transistor TB2p and NMOS transistor TB2n. Gate conductor gA2 intersects with p-type active region structure 82p and n-type active region structure 82n respectively in the channel regions of PMOS transistor TA2p and NMOS transistor TA2n.

[0078] Gate conductors gA1 and gA2 are connected together and configured to receive the first input signal "A". Gate conductors gB1 and gB2 are connected together and configured to receive the second input signal "B". Terminal conductor 835 is configured to generate the output signal "Z".

[0079] Front-side power rails 22A and 42A, extending along the X direction, are formed in the front-side metal layer M0 above the terminal conductors and gate conductors. Front-side signal lines 822, also extending along the X direction, are also formed in the front-side metal layer M0. Figure 8A The diagram is conceptually represented by wires connected to terminal conductors 832p, 835, and 838p. Each terminal conductor 832p, 835, and 838p is connected to the front signal line 822 via a corresponding front-side through-hole connector VD, thereby connecting the drain terminals of PMOS transistors TA1p, TBp1, TB2p, and TA2p together.

[0080] Front power rail 22A is configured to be maintained at the upper supply voltage VDD, and front power rail 42A is configured to be maintained at the lower supply voltage VSS. Terminal conductors 834p and 836p are connected to front power rail 22A, thereby connecting the source terminals of PMOS transistors TA1p, TBp1, TB2p, and TA2p to the upper supply voltage VDD. Terminal conductors 832n and 838n are connected to front power rail 42A, thereby connecting the source terminals of NMOS transistors TA1n and TA2n to the lower supply voltage VSS.

[0081] exist Figure 8B In the backside layout diagram, backside power lines 862 and 864 extending along the X direction are formed in a backside metal layer BM0 below the substrate. Backside power rails 20A and 40A extending along the X direction are formed in a backside metal layer BM1 below the backside metal layer BM0. Backside power rail 20A is configured to be maintained at the upper supply voltage VDD, while backside power rail 40A is configured to be maintained at the lower supply voltage VSS. Each terminal conductor portion 634p and 636p is electrically connected to the backside power line 862 via one of the backside via connectors 892A and 892B. Each terminal conductor 632n and 638n is electrically connected to the backside power line 864 via one of the backside via connectors 894A and 894B. Figure 8B In this configuration, neither of the back-side power lines 862 nor 864 extends across the vertical cell boundary of the single-level cell. The length of each back-side power line 862 and 864 (along the X direction) is less than the cell width of the single-level cell 800, where the cell width is measured along the X direction between the two vertical cell boundaries.

[0082] In another embodiment, such as Figure 8CAs shown in the rear-side layout diagram, the single-stage unit 800 also includes rear-side through-hole connectors 872A and 872B, as well as rear-side through-hole connectors 874A and 874B. Each rear-side through-hole connector 872A, 872B is directly connected between the rear-side power line 862 and the rear-side power rail 20A. Each rear-side through-hole connector 874A, 874B is directly connected between the rear-side power line 864 and the rear-side power rail 40A. Through the rear-side through-hole connectors 872A, 872B and the rear-side power line 862, the number of conductive paths between the front-side power rail 22A and the rear-side power rail 20A can be increased, thereby reducing the IR voltage drop between the front-side power rail 22A and the rear-side power rail 20A. By using the rear-side through-hole connectors 874A and 874B and the rear-side power line 864, the number of conductive paths between the front-side power rail 42A and the rear-side power rail 40A can be increased, thereby reducing the IR voltage drop between the front-side power rail 42A and the rear-side power rail 40A.

[0083] exist Figures 8A-8B In this implementation, when the single-stage cell 800 is implemented as a DSP cell, the back-side power lines 862 and 864 in the back-side metal layer BMO have the beneficial effect of reducing the IR drop associated with the power rails. Although the single-stage cell 800 does not include back-side signal lines (such as back-side signal line 662 similar to Figure 6), the beneficial effect of reducing the IR drop associated with the power rails offsets the loss of the benefit of placing an opposite phase signal in the back-side signal lines.

[0084] Figure 9 This is a layout diagram of an integrated circuit 900 having single-level and multi-level cells according to some embodiments. The integrated circuit 900 includes back-side power rails 20A-20D and back-side power rails 40A-40C. Each back-side power rail is formed in a second back-side metal layer BM1, which is located below a first metal layer BM0 on the back side of a substrate. Each back-side power rail 20A-20D is configured to receive a first supply voltage (e.g., an upper supply voltage VDD), and each back-side power rail 40A-40C is configured to receive a second supply voltage (e.g., a lower supply voltage VSS).

[0085] Figure 9The integrated circuits in the design include circuit units 910A-910C, 920A-920C, 930A-930D, 940A-940B, 950A-950B, and 960A-960B. Some circuit units are single-level units, while others are multi-level units. Single-level units include circuit units 910A, 920C, 930A-930C, 940A, and 950B. Each single-level unit has a back-side power line in a first back-side metal layer beneath the substrate. Multi-level units include circuit units 910B-910C, 920A-920B, 930D, 940B, 950A, and 960A-960B. Each multi-level unit has one or more back-side signal lines (BSLs). Each back-side signal line (BSL) is located in a first back-side metal layer beneath the substrate. Figure 9 The integrated circuit also includes power pickup units 910P1-910P2, 920P1, 930P1-930P2, 940P1-940P2, 950P1, and 960P1-960P2. Some exemplary embodiments of the power pickup units are as follows: Figures 7A-7C The layout diagram is shown below.

[0086] Figure 10A This is another example implementation of the power pickup unit according to some embodiments. Figure 10A The power pickup unit in the middle is from Figure 7C This was derived from a modification of the power pickup unit. The modifications altered the conductive connections of each back-side through-hole connector 792A, 794A, 796A, and 798A to the back-side power rail 20A, and also changed the conductive connections of each back-side through-hole connector 792B, 794B, 796B, and 798B to the back-side power rail 40A.

[0087] exist Figure 10A In this configuration, back-side conductors 1062 and 1064 are formed in a first back-side metal layer BM0 beneath the substrate, while back-side power rails 20A and 40A are formed in a second back-side metal layer BM1 beneath the first back-side metal layer BM0. Each back-side via connector 792A, 794A, 796A, and 798A is connected to the back-side conductor 1062, and the back-side conductor 1062 is also correspondingly connected to the back-side power rail 20A via one of the back-side via connectors 1072A, 1074A, 1076A, and 1078A (which passes through the interlayer dielectric between the first back-side metal layer BM0 and the second back-side metal layer BM1). Each back-side through-hole connector 792B, 794B, 796B, and 798B is connected to the back-side conductor 1064, and the back-side conductor 1064 is also connected to the back-side power rail 40A via one of the back-side through-hole connectors 1072B, 1074B, 1076B, or 1078B (which passes through the interlayer dielectric between the first back-side metal layer BM0 and the second back-side metal layer BM1).

[0088] Figure 10B It is according to some embodiments along Figure 10A A cross-sectional view of the power pickup unit on the cutting plane AA'. When Figure 10B The power pickup unit in the figure is modified from the power pickup unit in Figure 7. The conduction path from the front power rail 22A through the terminal conductor 732p to the rear power rail 20A is modified, and the conduction path from the front power rail 42A through the terminal conductor 732n to the rear power rail 40A is also modified.

[0089] In the conduction path from the front power rail 22A through terminal conductor 732p to the rear power rail 20A, such as Figure 10B As shown, the back-side through-hole connector 792A is connected to the back-side conductor 1062, and the back-side conductor 1062 is further connected to the back-side power rail 20A via the back-side through-hole connector 1072A. In the conduction path from the front-side power rail 42A through the terminal conductor 732n to the back-side power rail 40A, as... Figure 10B As shown, the back-side through-hole connector 792B is connected to the back-side conductor 1064, and the back-side conductor 1064 is further connected to the back-side power rail 40A through the back-side through-hole connector 1072B.

[0090] Figure 11 This is a flowchart of a method 1100 for producing an integrated circuit with a back-side power rail according to some embodiments. Figure 11 The described sequence of operations for method 1100 is for illustrative purposes only; the operation of method 1100 can be performed in conjunction with... Figure 11 The different orders described in the text can be executed. It should be understood that... Figure 11 Additional operations are performed before, during, and / or after the method 1100 described in the text, and some other operations can be performed... Figure 11 The method described in 1100 is executed, and some other processes are only briefly described here.

[0091] In operation 1110 of method 1100, the standard cell is designed as a DSP cell. Each DSP cell has a back-side power line in a first back-side metal layer (e.g., BMO) beneath the substrate and a back-side power rail (e.g., 20A, 40A) in a second back-side metal layer (e.g., BMO) beneath the first back-side metal layer (e.g., BMO). DSP cells with dual-side power rails can be designed during operation or obtained from an existing library of standard cells. An example layout design for the DSP cell is shown in... Figures 8A-8B The layout diagram is shown. Figures 8A-8B The DSP unit has back-side power lines 862 and 864 in the first back-side metal layer BMO.

[0092] In the operations following operation 1110, cell-level optimization is performed on the standard cells generated and analyzed in operation 1110. If the standard cell is a single-level cell (e.g., the FOM cell is implemented as an inverter, NAND gate, or NOR gate), then in operation 1129, the single-level cell is stored in the library for calibration.

[0093] If the standard cell is a multi-level cell, then in operation 1122, the back-side signal line of the multi-level cell is redesigned to eliminate various stray capacitances (e.g., Miller capacitance, or stray capacitance due to cross-coupling between two or more conductors). For example, to eliminate stray capacitance due to capacitive coupling between two parallel conductors carrying signals of opposite phase, one of the two parallel conductors is replaced with a back-side signal line in a first back-side metal layer (e.g., BMO) beneath the substrate, and the signal originally carried by the replacement conductor is rerouted to the newly implemented back-side signal line. Figure 9 In the example layout, Figure 9 Each multi-level unit in an integrated circuit has one or more back-side signal lines (BSL). For example... Figures 6A-6B As shown in the example, the back-side signal line 662 is implemented to carry signals, thereby reducing capacitive coupling between some wires carrying opposite-phase signals. After operation 1122, operation 1124 is performed on the redesigned multi-stage cell.

[0094] In operation 1124, if there is still space in the layout design to add more rear-side through-hole connectors and / or extended through-hole connectors, one or more conduction paths from the front power rail to the rear power rail can be added to the redesigned multi-stage cell obtained in operation 1122. In such cases... Figures 6A-6B In the example shown, two conductive paths are formed from the front power rail 42A to the rear power rail 40A. One conductive path passes through terminal conductor 632n, rear via connector 694A, and extended via connector 684A. The other conductive path passes through terminal conductor 638n, rear via connector 694B, and extended via connector 684B. After operation 1124, library calibration is performed in operation 1130, design flow is performed in operation 1140, and timing closure is performed in operation 1150.

[0095] Next, in operations 1160 and 1170, the fill cells in the layout design obtained in operation 1140 are swapped with power pickup units, thereby reducing the IR voltage drop associated with the front and rear power rails. Specifically, in operation 1160, fill cells are searched in the layout design obtained in operation 1140, and for each detected fill cell, the cell width of the detected fill cell is determined. Based on the cell width of the detected fill cell, in operation 1161, a matching power pickup unit is used as a replacement. Then, in operation 1170, each detected fill cell is replaced with a matched power pickup unit. The cell width of the matched power pickup unit is less than or equal to the cell width of the detected fill cell to be replaced. In some embodiments, each detected fill cell is replaced with a matching power pickup unit having the same cell width. For example, in some embodiments, each detected one-CPP-width fill cell is replaced with... Figure 7A In the power pickup unit, each detected two CPP-wide fill cells are replaced with Figure 7B The power pickup unit in the middle, and each of the four detected CPP-wide fill units is replaced with Figure 7C The power pickup unit is located within the system. Following operation 1170, in operation 1180, physical verification of the layout design is performed. Examples of physical verification include Design Rule Check (DRC), Layout and Schematic Verification (LVS), Antenna Check, and Electrical Rule Check (ERC).

[0096] Figure 12 This is a flowchart of a method 1200 for manufacturing an integrated circuit according to some embodiments. Figure 12 The operational sequence of method 1200 described herein is for illustrative purposes only; the operation of method 1200 can be performed in conjunction with... Figure 12 The different orders described in the text can be executed. It should be understood that... Figure 12 Additional operations are performed before, during, and / or after the method described in section 1200, and some other operations can be performed within this timeframe. Figure 12 The method described in section 1200 is executed, and some other processes are only briefly described here.

[0097] In operation 1210 of method 1200, a first type of active region structure and a second type of active region structure are fabricated on a substrate. Figure 2A and Figures 3A-3B In the example shown, the p-type active region structure 82p and the n-type active region structure 82n are fabricated on the substrate 30.

[0098] In operation 1215 of method 1200, a first terminal conductor and a second terminal conductor are manufactured. Figure 2A and Figures 3A-3BIn the example shown, terminal conductor 132Ap intersects with p-type active region structure 82p and terminal conductor 132N intersects with n-type active region structure 82n.

[0099] In operation 1225 of method 1200, a first front power rail and a second front power rail are manufactured in the front metal layer above the first type of active region structure and the second type of active region structure. Figure 2A and Figures 3A-3B In the example shown, front power rails 22A and 42A are fabricated in a first front metal layer M0, and an interlayer dielectric layer covering p-type active region structure 82p and n-type active region structure 82n is overlaid on the first front metal layer M0. Terminal conductor 132Ap is connected to front power rail 22A through a corresponding front via connector VD, and terminal conductor 132N is connected to front power rail 42A through a corresponding front via connector VD.

[0100] In operation 1230 of method 1200, a first back-side through-hole connector and a second back-side through-hole connector are formed. In such a way... Figure 2A and Figures 3A-3B In the example shown, back-side via connectors 191A and 192A are formed through the substrate 30. Back-side via connector 191A is connected to the active region P-EPI of the p-type active region structure 82p, and the active region P-EPI is in conductive contact with the terminal conductor 132Ap. Back-side via connector 192A is connected to the active region N-EPI of the n-type active region structure 82n, and the active region N-EPI is in conductive contact with the terminal conductor 132N.

[0101] In operation 1245 of method 1200, a back-side signal line is fabricated in a first back-side metal layer on the back side of the substrate. As shown in... Figure 2A and Figures 3A-3B In the example shown, the back-side signal line 162 is fabricated in the first back-side metal layer BMO on the back side of the substrate 30.

[0102] In operation 1250 of method 1200, a first extended through-hole connector and a second extended through-hole connector are formed. Figure 2A and Figures 3A-3B In the example shown, an extended through-hole connector BV0 connected to the back-side through-hole connector 191A and an extended through-hole connector BV0 connected to the back-side through-hole connector 192A are formed to pass through both the first back-side metal layer BM0 and the interlayer dielectric in contact with the first back-side metal layer BM0.

[0103] In operation 1265 of method 1200, a first back-side power rail and a second back-side power rail are fabricated in a second back-side metal layer. Figure 2A and Figures 3A-3BIn the example shown, back-side power rails 20A and 40A are fabricated in a second back-side metal layer BM1, which is deposited on an interlayer dielectric in contact with a first back-side metal layer BM0. Back-side power rail 20A is directly connected to back-side through-hole connector 191A via an extended through-hole connector BV0 that contacts back-side through-hole connector 192A. Back-side power rail 40A is directly connected to back-side through-hole connector 192A via an extended through-hole connector BV0 that contacts back-side through-hole connector 192A.

[0104] Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0105] In some embodiments, the EDA system 1300 includes an automated placement and routing (APR) system. The design layout method described herein represents a wiring configuration according to one or more embodiments, for example, implemented using the EDA system 1300 according to some embodiments.

[0106] In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. The storage medium 1304 is also encoded (i.e., stored) with computer program code 1306 (i.e., an executable instruction set) among other things. Execution (at least partially) of the instructions 1306 by the hardware processor 1302 represents an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter referred to as the proposed process and / or method).

[0107] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is further electrically coupled to I / O interface 1310 via bus 1308. Network interface 1312 is further electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314, enabling processor 1302 and computer-readable storage medium 1304 to be connected to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304 so that system 1300 can be used to perform part or all of the proposed process and / or method. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0108] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1304 includes semiconductor memory or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0109] In one or more embodiments, storage medium 1304 stores computer program code 1306 configured to enable system 1300 (where such execution (at least partially) represents an EDA tool) to perform some or all of the proposed processes and / or methods. In one or more embodiments, storage medium 1304 further stores information facilitating the implementation of some or all of the proposed processes and / or methods. In one or more embodiments, storage medium 1304 stores a standard cell library 1307 including such standard cells disclosed herein. In one or more embodiments, storage medium 1304 stores one or more layout diagrams 1309 corresponding to one or more layouts disclosed herein.

[0110] EDA system 1300 includes I / O interface 1310. I / O interface 1310 is coupled to an external circuit system. In one or more embodiments, I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0111] EDA system 1300 further includes a network interface 1312 coupled to processor 1302. Network interface 1312 enables system 1300 to communicate with a network 1314 connected to one or more other computer systems. Network interface 1312 includes wireless network interfaces such as Bluetooth, Wireless Fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or Wideband Code Division Multiple Access (WCDMA); or wired network interfaces such as Ethernet, Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers (IEEE) 1364. In one or more embodiments, some or all of the proposed processes and / or methods are implemented in two or more systems 1300.

[0112] System 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. The information is transmitted to processor 1302 via bus 13013. EDA system 1300 is configured to receive information related to the user interface (UI) via I / O interface 1310. This information is stored as UI 1342 on computer-readable media 1304.

[0113] In some embodiments, a portion or all of the proposed process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, a portion or all of the proposed process and / or method is implemented as a software application as part of an additional software application. In some embodiments, a portion or all of the proposed process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the proposed process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, a portion or all of the proposed process and / or method is implemented as a software application used by EDA system 1300. In some embodiments, tools (e.g., available from Cadence Design Systems) are used. (or another suitable layout generation tool) to generate a layout diagram that includes standard cells.

[0114] In some embodiments, the process is achieved in the form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, and one or more of the like.

[0115] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system 1400 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, the manufacturing system 1400 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0116] exist Figure 14In this IC manufacturing system 1400, entities such as design studio 1420, mask room 1430, and IC manufacturing plant (“fab”) 1450 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC components 1460. The entities in system 1400 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and supplies services to and / or receives services from one or more other entities. In some embodiments, a single, larger company owns two or more of design studio 1420, mask room 1430, and IC manufacturing plant 1450. In some embodiments, two or more of design studio 1420, mask room 1430, and IC manufacturing plant 1450 coexist in a common facility and use common resources.

[0117] Design studio (or design team) 1420 generates IC design layout 1422. IC design layout 1422 includes various geometric patterns designed for IC element 1460. These geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers constituting various components of the IC element 1460 to be fabricated. These layers are combined to form various IC features. For example, a portion of IC design layout 1422 includes various IC features (e.g., active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings in bonding pads) to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1420 performs appropriate design procedures to form IC design layout 1422. These design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1422 is presented in one or more data files containing information about geometric patterns. For example, IC design layout 1422 is expressed in GDSII or DFII file format.

[0118] Mask chamber 1430 includes data preparation 1432 and mask fabrication 1444. Mask chamber 1430 uses an IC design layout 1422 to fabricate one or more masks 1445 for fabricating various layers of an IC device 1460. Mask chamber 1430 performs mask data preparation 1432, in which the IC design layout 1422 is translated into a representative data file (RDF). Mask data preparation 1432 supplies the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask 1445 or a semiconductor wafer 1453). Mask data preparation 1432 manipulates the IC design layout 1422 to conform to the specific characteristics of the mask plotter and / or the requirements of the IC manufacturer 1450. Figure 14 In this design, mask data preparation 1432 and mask fabrication 1444 are illustrated as separate components. In some embodiments, mask data preparation 1432 and mask fabrication 1444 may be collectively referred to as mask data preparation.

[0119] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, interference, other process effects, and similar reasons). OPC adjusts the IC design layout 1422. In some embodiments, mask data preparation 1432 further includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution adjustment features, phase-shift masks, other suitable techniques, and similar techniques or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further utilized, treating OPC as an inverse imaging problem.

[0120] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that checks the IC design layout 1422, which has undergone processes in the OPC, using a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes and similar factors. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for the effects of photolithography implementation during mask fabrication 1444, thereby reversing some modifications implemented in the OPC to meet the mask creation rules.

[0121] In some embodiments, mask data preparation 1432 includes lithography process checking (LPC), which simulates the processes to be performed by IC manufacturer 1450 to fabricate IC device 1460. LPC simulates these processes based on IC design layout 1422 to fabricate simulated finished devices, such as IC device 1460. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors or combinations thereof. In some embodiments, after simulated finished devices have been fabricated using LPC, if the shape similarity of the simulated devices is insufficient to meet design rules, OPC and / or MRC are repeated to further improve IC design layout 1422.

[0122] For clarity, the above description of mask data preparation 1432 has been simplified. In some embodiments, mask data preparation 1432 includes additional features, such as modifying the logic operation (LOP) of IC design layout 1422 according to manufacturing rules. Additionally, the processes applied to IC design layout 1422 during data preparation 1432 can be performed in various different sequences.

[0123] After mask data preparation 1432 and during mask fabrication 1444, mask 1445 or a group of masks 1445 is fabricated based on the modified IC design layout 1422. In some embodiments, an electron beam (e-beam) or a mechanism consisting of multiple electron beams is used to pattern the mask (photomask or stencil) 1445 based on the modified IC design layout 1422. Mask 1445 is formed using various techniques. In some embodiments, mask 1445 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (e.g., ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, a phase-shifting technique is used to form mask 1445. In the phase-shift mask (PSM) version of mask 1445, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask is a decaying PSM or an alternating PSM. The mask produced by mask fabrication 1444 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0124] IC manufacturing plant 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for producing various different IC products. In some embodiments, IC manufacturing plant 1450 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end fabrication (front-end-of-line, FEOL) of multiple IC products, a second manufacturing facility for back-end fabrication (back-end-of-line, BEOL) of interconnects and packages of IC products, and a third manufacturing facility for providing other services to the foundry.

[0125] IC manufacturing plant 1450 includes manufacturing tools 1452 configured to perform various manufacturing operations on semiconductor wafers 1453, such as manufacturing IC devices 1460 according to a mask (e.g., mask 1445). In various embodiments, manufacturing tools 1452 include one or more wafer steppers, ion implanters, photoresist coaters, processing chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0126] IC fabrication plant 1450 uses a mask (or multiple masks) 1445, fabricated by mask chamber 1430, to fabricate IC device 1460. Therefore, IC fabrication plant 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, IC fabrication plant 1450 uses mask 1445 to fabricate semiconductor wafer 1453 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer further includes one or more of various doped regions, dielectric features, multi-level interconnects, and similar features (formed at subsequent fabrication steps).

[0127] This disclosure relates to an integrated circuit. The integrated circuit includes a first type of active region structure, a second type of active region structure, a first terminal conductor, and a second terminal conductor. Each of the first type of active region structure and the second type of active region structure extends on a substrate along a first direction. The first terminal conductor intersects the first type of active region structure at the source region of the first type of transistor, and the second terminal conductor intersects the second type of active region structure at the source region of the second type of transistor. The integrated circuit also includes a first front-side power rail and a second front-side power rail, each extending along the first direction. The first and second front-side power rails are located in a front-side metal layer above the first and second type of active region structures. The integrated circuit also includes a back-side signal line, a first back-side power rail extending along the first direction, and a second back-side power rail extending along the first direction, all located in a first back-side metal layer below the substrate. The first and second back-side power rails are located in a second back-side metal layer below the first back-side metal layer. The integrated circuit also includes a first back-side through-hole connector, a first extended through-hole connector, a second back-side through-hole connector, and a second extended through-hole connector. The first back-side through-hole connector is conductively connected to the source region of a first type of transistor. The first extended through-hole connector is directly connected between the first back-side through-hole connector and a first back-side power rail. The second back-side through-hole connector is conductively connected to the source region of a second type of transistor. The second extended through-hole connector is directly connected between the second back-side through-hole connector and a second back-side power rail.

[0128] In some embodiments, the integrated circuit further includes: a first front-side via connector directly connected between the first terminal conductor and the first front-side power rail; and a second front-side via connector directly connected between the second terminal conductor and the second front-side power rail. In some embodiments, the integrated circuit further includes: a third terminal conductor intersecting the first type of active region structure or the second type of active region structure at the drain region of the transistor; and a third back-side via connector directly connected between the third terminal conductor and the back-side signal line. In some embodiments, the integrated circuit further includes: a gate conductor intersecting the first type of active region structure or the second type of active region structure at the channel region of the transistor; and a third back-side via connector directly connected between the gate conductor and the back-side signal line. In some embodiments, the back-side signal line is a two-dimensional signal line having a first signal segment extending along the first direction and a second signal segment extending along a second direction perpendicular to the first direction.

[0129] Another aspect of this disclosure relates to an integrated circuit. This integrated circuit includes a first type of active region structure and a second type of active region structure, each extending along a first direction on a substrate. The integrated circuit includes a first front-side power rail extending along the first direction, a second front-side power rail extending along the first direction, a back-side signal line, a first back-side power rail extending along the first direction, and a second back-side power rail extending along the first direction. The first and second front-side power rails are located in a front-side metal layer above the first and second type active region structures. The back-side signal line is located in a first back-side metal layer below the substrate. The first and second back-side power rails are located in a second back-side metal layer below the first back-side metal layer. The integrated circuit also includes a multi-level cell having a first logic gate and a second logic gate, which are connected in series between the input of the first logic gate and the output of the second logic gate, such that the input of the second logic gate is configured to receive a logic signal from the output of the first logic gate. In the multi-level cell, a first type of transistor has a source region in a first type of active region structure, which is conductively connected to a first back-side power rail through one or more through-hole connectors, and a second type of transistor has a source region in a second type of active region structure, which is conductively connected to a second back-side power rail through one or more through-hole connectors.

[0130] In some embodiments, the integrated circuit further includes: a first back-side via connector conductively connected to the source region of the first type of transistor; a first extended via connector directly connected between the first back-side via connector and the first back-side power rail; a second back-side via connector conductively connected to the source region of the second type of transistor; and a second extended via connector directly connected between the second back-side via connector and the second back-side power rail. In some embodiments, the multi-level cell has a first vertical cell boundary and a second vertical cell boundary extending in a second direction perpendicular to the first direction, and wherein each of the first vertical cell boundary and the second vertical cell boundary passes through a first boundary isolation region in the first type of active region structure and a second boundary isolation region in the second type of active region structure. In some embodiments, the integrated circuit further includes: a single-stage unit, wherein the single-stage unit is a buffer unit, an inverter unit, a NAND unit, a NOR unit, an AND unit, or an OR unit, and wherein the single-stage unit includes: a second first-type transistor having a source region located in the first-type active region structure and conductively connected to the first front-side power rail; a first back-side power line located in the first back-side metal layer and electrically connected to the source region of the second first-type transistor; a second second-type transistor having a source region located in the second-type active region structure and conductively connected to the second front-side power rail; and a second back-side power line located in the first back-side metal layer and electrically connected to the source region of the second second-type transistor. In some embodiments, the integrated circuit further includes: a first back-side via connector conductively connecting the first back-side power line and the source region of the second first-type transistor; and a second back-side via connector conductively connecting the second back-side power line and the source region of the second second-type transistor. In some embodiments, the integrated circuit further includes: a power pickup unit, wherein the power pickup unit does not contain transistors or each transistor therein is implemented as a dummy transistor, and the power pickup unit includes: a first terminal conductor intersecting the first type of active region structure; a first front-side via connector directly connected between the first terminal conductor and the first front-side power rail; and a first back-side via connector conductively connected between the first terminal conductor and the first back-side power rail. In some embodiments, the power pickup unit further includes: a first back-side conductor formed in the first back-side metal layer, wherein the first back-side via connector is conductively connected to the first back-side power rail through the first back-side conductor. In some embodiments, the power pickup unit further includes: a first extended via connector directly connected between the first back-side via connector and the first back-side power rail.In some embodiments, the power pickup unit further includes: a second terminal conductor intersecting the second type of active region structure; a second front-side via connector directly connected between the second terminal conductor and the second front-side power rail; and a second back-side via connector conductively connected between the second terminal conductor and the second back-side power rail. In some embodiments, the power pickup unit has a first vertical cell boundary and a second vertical cell boundary extending in a second direction perpendicular to the first direction, wherein each of the first vertical cell boundary and the second vertical cell boundary passes through a first boundary isolation region in the first type of active region structure and a second boundary isolation region in the second type of active region structure. In some embodiments, the multi-level cell includes a plurality of gate conductors extending in a second direction below the front metal layer, and two adjacent gate conductors are separated by a spacing distance equal to the contact polysilicon pitch (CPP), wherein the power pickup unit has a cell width equal to or less than four CPPs. In some embodiments, the power pickup unit further includes: a third terminal conductor intersecting with one of the first type of active region structure or the second type of active region structure; a third front through-hole connector directly connecting the third terminal conductor to one of the first front power rail or the second front power rail; and a first back through-hole connector conductively connected between the third terminal conductor and one of the first back power rail and the second back power rail.

[0131] Another aspect of this disclosure relates to a method for manufacturing an integrated circuit. The method includes fabricating a first-type active region structure and a second-type active region structure, each extending along a first direction, on a substrate, and fabricating a first terminal conductor and a second terminal conductor. The first terminal conductor intersects the first-type active region structure at the source region of a first-type transistor, and the second terminal conductor intersects the second-type active region structure at the source region of a second-type transistor. The method further includes fabricating a first front-side power rail and a second front-side power rail in a front-side metal layer above the first-type and second-type active region structures. Each of the first and second front-side power rails extends along the first direction. The method further includes forming a first back-side via connector electrically connected to the source region of the first-type transistor, and forming a second back-side via connector electrically connected to the source region of the second-type transistor; fabricating a back-side signal line in a first back-side metal layer on the back side of the substrate; and forming a first extended via connector and a second extended via connector. The method further includes fabricating a first back-side power rail and a second back-side power rail in a second back-side metal layer. The first back-side metal layer is located between the second back-side metal layer and the substrate. The first back-side power rail extending along the first direction is directly connected to the first back-side through-hole connector through the first extended through-hole connector, while the second back-side power rail extending along the first direction is directly connected to the second back-side through-hole connector through the second extended through-hole connector.

[0132] In some embodiments, the method further includes: fabricating a back-side signal line in the first back-side metal layer before fabricating the first back-side power rail and the second back-side power rail. In some embodiments, fabricating the back-side signal line includes: fabricating the back-side signal line as a two-dimensional signal line having a first signal segment extending along the first direction and a second signal segment extending along a second direction perpendicular to the first direction.

[0133] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or to achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this invention, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of this invention.

Claims

1. An integrated circuit, comprising: first-type active-region structures and second-type active-region structures each extending along a first direction on a substrate; a first terminal conductor intersecting the first-type active-region structures at source regions of first-type transistors; a second terminal conductor intersecting the second-type active-region structures at source regions of second-type transistors; first and second front-side power rails each extending along the first direction and located in a front-side metal layer above the first-type and second-type active-region structures; a backside signal line located in a first backside metal layer below the substrate; first and second backside power rails each extending along the first direction and located in a second backside metal layer below the first backside metal layer; a first backside via connection conductively connected to a source region of a first-type transistor; a first extension via connection directly connected between the first backside via connection and the first backside power rail; a second backside via connection conductively connected to a source region of a second-type transistor; and a second extension via connection directly connected between the second backside via connection and the second backside power rail. further comprising:

2. The integrated circuit of claim 1, wherein, a first front-side via connection directly connected between the first terminal conductor and the first front-side power rail; and a second front-side via connection directly connected between the second terminal conductor and the second front-side power rail. further comprising: a third terminal conductor intersecting the first-type active-region structures or the second-type active-region structures at drain regions of transistors; and 3. The integrated circuit of claim 1, wherein, a third backside via connection directly connected between the third terminal conductor and the backside signal line. further comprising: a gate conductor intersecting the first-type active-region structures or the second-type active-region structures at channel regions of transistors; and a third backside via connection directly connected between the gate conductor and the backside signal line.

4. The integrated circuit of claim 1, wherein, the backside signal line is a two-dimensional signal line having a first signal line segment extending along the first direction and a second signal line segment extending along a second direction perpendicular to the first direction.

6. An integrated circuit, comprising: first-type active-region structures and second-type active-region structures each extending along a first direction on a substrate; first and second front-side power rails each extending along the first direction and located in a front-side metal layer above the first-type and second-type active-region structures; 5. The integrated circuit of claim 1, wherein, a backside signal line located in a first backside metal layer below the substrate; first and second backside power rails each extending along the first direction and located in a second backside metal layer below the first backside metal layer; a multi-level cell having first and second logic gates connected in series between an input of the first logic gate and an output of the second logic gate such that an input of the second logic gate is configured to receive a logic signal from an output of the first logic gate; ​ ​ ​ ​ a first type of transistor in the multi-level cell having a source region in the first type of active region structure, the source region being conductively connected to the first backside power rail through one or more via connections; and a second type of transistor in the multi-level cell having a source region in the second type of active region structure, the source region being conductively connected to the second backside power rail through one or more via connections.

7. The integrated circuit of claim 6, wherein, Also included are: a power pickup unit, wherein the power pickup unit does not contain transistors or each transistor therein is implemented as a dummy transistor, and the power pickup unit includes: a first terminal conductor intersecting the first type of active region structure; a first frontside via connection directly connected between the first terminal conductor and the first frontside power rail; and a first backside via connection conductively connected between the first terminal conductor and the first backside power rail.

8. The integrated circuit of claim 7, wherein, The power pickup unit further includes: a first backside conductor formed in the first backside metal layer, wherein the first backside via connection is conductively connected to the first backside power rail through the first backside conductor.

9. The integrated circuit of claim 7, wherein, The power pickup unit further includes: a first extension via connection directly connected between the first backside via connection and the first backside power rail.

10. The integrated circuit of claim 7, wherein, The power pickup unit further includes: a second terminal conductor intersecting the second type of active region structure; a second frontside via connection directly connected between the second terminal conductor and the second frontside power rail; and a second backside via connection conductively connected between the second terminal conductor and the second backside power rail.

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