Integrated circuit

Abstract

The integrated circuit includes a device region and an overlay mark region. The device region includes a plurality of transistors and a metal connection structure over the transistors. The overlapping mark area comprises a first diffraction grating of a first conductive structure, a shielding grating of a long and thin structure and a second diffraction grating of a second conductive structure located above the shielding grating and the first diffraction grating. A plurality of first conductive structures are laterally located between each pair of adjacent second conductive structures.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit. Background Technology

[0002] Integrated circuits provide computing power in smartphones, tablets, desktop computers, notebook computers, and many other types of electronic devices. As the demand for computing power in electronic devices continues to increase, one way to improve the computing power of integrated circuits is to increase the number of transistors and other integrated circuit components that can be contained within a given area of ​​a semiconductor substrate.

[0003] However, as the dimensions of transistor components and their corresponding metal interconnect structures shrink, alignment tolerances decrease. As one example, vias are used to contact the source / drain contacts and the gate electrode. When a via is misaligned with the source / drain contacts and the gate electrode, the via will not make the expected contact with the source / drain contacts or the gate electrode. Furthermore, metal lines are formed in metal layers (e.g., metal layer 0, metal layer 1, etc.) to contact the vias. Misalignment of the metal layer with the via or the underlying metal layer will cause the integrated circuit to malfunction. Utility Model Content

[0004] The embodiments disclosed herein provide an integrated circuit, which includes an overlapping marking region. The overlapping marking region includes a masking grating with an elongated structure, a first diffraction grating with a plurality of first conductive structures, and a second diffraction grating with a plurality of second conductive structures. The first diffraction grating includes a plurality of first conductive structures in a first group. The second diffraction grating is located above the first diffraction grating and the masking grating of the first conductive structures. The second diffraction grating is laterally positioned between each pair of adjacent second conductive structures, corresponding to each first conductive structure in the first group.

[0005] The embodiments disclosed herein provide an integrated circuit including a device region and an overlapping marking region. The device region includes source / drain regions of a transistor and a first metal interconnect structure electrically coupled to the source / drain regions. The overlapping marking region includes a first diffraction grating of a plurality of first conductive structures and a second diffraction grating of a plurality of second conductive structures located above and offset from the first conductive structures. The first conductive structures are laterally located between each pair of adjacent second conductive structures.

[0006] The embodiments disclosed herein provide an integrated circuit including an overlapping marking region and a device region. The overlapping marking region includes a plurality of semiconductor fins, a first diffraction grating of a plurality of first conductive structures located on the semiconductor fins, and a second diffraction grating of a plurality of second conductive structures located above and offset from the first conductive structures. Furthermore, the first conductive structures corresponding to the second diffraction gratings are laterally disposed between each pair of adjacent second conductive structures. The device region includes a plurality of first metal connection structures and a plurality of second metal connection structures in contact with the first metal connection structures. Attached Figure Description

[0007] The embodiments disclosed herein can be better understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practice, the features are not drawn to scale. In fact, the dimensions of various features can be arbitrarily increased or decreased for clarity of illustration.

[0008] Figures 1A to 1F These are top and cross-sectional views of the overlapping marking area and device area of ​​an integrated circuit according to some embodiments;

[0009] Figure 1G This is a block diagram of a lithography system according to some embodiments;

[0010] Figure 1H This is a top view of a wafer according to some embodiments;

[0011] Figure 1I This is a simplified top view of an integrated circuit according to some embodiments;

[0012] Figures 2A to 2B This is a cross-sectional view of the masking overlap area according to some embodiments;

[0013] Figure 3 This is a top view of the overlapping marking area of ​​an integrated circuit according to some embodiments; and

[0014] Figure 4 This is a flowchart of a method for forming an integrated circuit according to some embodiments.

[0015] [Symbol Explanation]

[0016] 100: EUV lithography system / Extreme Ultraviolet lithography system

[0017] 101: Wafer

[0018] 102: Integrated Circuits

[0019] 104: Overlapping Marker Area

[0020] 105: Device Area

[0021] 106: Slender structure / semiconductor fin

[0022] 107: Semiconductor Fin

[0023] 108, 109, 110: Conductive structures

[0024] 108a, 108b: Slender conductive structures

[0025] 111: Source / Drain Contact

[0026] 113: Conductive via

[0027] 120:Substrate

[0028] 122: Sacrificial Semiconductor Layer

[0029] 123: Sacrificial Semiconductor Nanostructures

[0030] 124: Semiconductor layer

[0031] 125: Channel

[0032] 126, 128, 132: Interlayer dielectric layers

[0033] 130: Dielectric layer

[0034] 134: Source / Drain Region

[0035] 136: Inner spacer

[0036] 137: Transistor

[0037] 140: EUV generator

[0038] 142: Scanner

[0039] 144: EUV light

[0040] 146: Scanner Optical Components

[0041] 148: Light Mask Stage

[0042] 150: Light Mask

[0043] 152: Wafer Stage

[0044] 154: Diffraction-based Overlap Measurement System

[0045] 156: Control System

[0046] 151, 153, 155, 157: Interlayer dielectric layers

[0047] 208, 308: Conductive structure

[0048] 400: Method

[0049] 402, 404, 406, 408: Steps

[0050] D1, D2, D3, D4, D5: Dimensions

[0051] D6, D7, D8, D9, D10: Size

[0052] D11, D12, D14, D15, D16: Dimensions

[0053] D13: Distance

[0054] DX, DY, OX, OY: Section lines

[0055] X, Y, Z: Direction Detailed Implementation

[0056] The following description illustrates various thicknesses and materials of layers and structures within an integrated circuit die. Dimensions and materials are specifically disclosed through examples of various embodiments. Based on this disclosure, those skilled in the art will understand that other dimensions and materials may be used in other embodiments without departing from the scope of this disclosure.

[0057] This disclosure provides various embodiments or examples of configurations to achieve different features of the subject matter. The specific examples of components and configurations described below are for the purpose of simplifying this disclosure; of course, these are merely exemplary and not limiting. For example, the first feature formed above or on the second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where other features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat referenced numbers and / or letters in various examples; such repetition is for simplicity and clarity and is not in itself intended to limit the relationship between the various embodiments and / or configurations described.

[0058] Furthermore, for ease of explanation, spatially related terms (e.g., "below," "below," "lower," "above," "upper," etc.) used in this disclosure describe the relationship between one component or feature and another component or feature as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and therefore the spatially relative descriptive terms used in this disclosure can be interpreted accordingly.

[0059] In the following description, certain specific details are described to provide a thorough understanding of the various embodiments of this disclosure. However, those skilled in the art will understand that this disclosure can be implemented without these specific details. In other instances, this disclosure does not describe in detail well-known structures related to electronic components and manufacturing techniques to avoid unnecessarily obscuring the description of the embodiments of this disclosure.

[0060] Unless the context otherwise requires, throughout the specification and the scope of the following claims, the term “comprising” and its variations, such as “including” and “having”, shall be interpreted in an open and inclusive sense, meaning “including but not limited to”.

[0061] For example, the use of ordinal numbers such as first, second, and third is not intended to specify the order of devices, structures, or processes, but rather to distinguish multiple operations or structures as examples.

[0062] Throughout this specification, references to "some embodiments" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with that embodiment is incorporated in at least some embodiments. Therefore, "some embodiments" or "an embodiment" appearing throughout this disclosure do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0063] As used in this specification and the appended claims, the singular forms “a” and “the” include multiple objects unless otherwise expressly stated. It should also be noted that the term “or” generally includes the meaning of “and / or” unless otherwise expressly stated.

[0064] This disclosure provides a method and structure configured to improve component alignment in a wafer fabrication process. The embodiments of this disclosure provide an improved overlap marking region that improves overlap measurements based on diffraction (scatterometry) for subsequent mask alignment. When fabricating a wafer, the wafer includes device areas corresponding to functional circuitry of an integrated circuit and an overlap marking region. The overlap marking region includes periodic structures or gratings configured for diffraction-based scatterometry measurements, enabling alignment to form subsequent features. The overlap marking region includes a masking grating of an elongated structure, a bottom grating of a first elongated conductive structure, and a top grating of a second elongated conductive structure located above the bottom grating of the first elongated conductive structure. Multiple first conductive structures can be laterally positioned between each pair of adjacent second conductive structures. This improves the alignment of subsequently formed conductive structures (e.g., vias and metal lines). Therefore, wafer yield is improved, resulting in better-functioning integrated circuits.

[0065] Figure 1A This is a top view of integrated circuit 102 at an intermediate stage of process according to some embodiments. More specifically, Figure 1A A top view of the overlapping marker region 104 of integrated circuit 102. Figure 1B is a top view of the device region of integrated circuit 102 according to some embodiments. As described in more detail later, multiple components of the overlapping marker region 104 are configured to jointly perform a diffraction-based overlapping scan to facilitate accurate alignment of the mask in subsequent feature-forming processes.

[0066] Before describing the details of the overlapping marking region 104 and the device region 105, it is advantageous to briefly explain the different functions of the device region 105 and the overlapping marking region 104 for the subsequent description. Device region 105 includes circuitry constituting integrated circuit 102. For example, when integrated circuit 102 is fabricated, device region 105 may include multiple transistors, each transistor including a channel region, a source / drain region, and a gate region. When device region 105 is fabricated, it may include multiple metal layers stacked above the transistors, each metal layer formed on a corresponding interlayer dielectric layer. When device region 105 is fabricated, it may include multiple conductive vias embedded in the interlayer dielectric layer, and these conductive vias connect source / drain contacts or gate contacts to a metal base layer (M0), connect a first metal layer (M1) to a second metal layer (M2), and so on.

[0067] When fabricating integrated circuit 102, feature patterns in integrated circuit 102 can be formed using a large number of photomasks (or masks). Before performing lithography on integrated circuit 102 using masks, one or more alignment processes are performed. Through the alignment process, features previously formed by masking and lithography processes can be properly aligned with features to be formed subsequently by lithography processes.

[0068] The overlapping marker region 104 assists in performing alignment processes throughout the fabrication process of the integrated circuit 102. More specifically, the overlapping marker region 104 assists in performing an overlap-based diffraction (scattering measurement) measurement process to aid alignment. The overlapping marker region 104 includes multiple grating structures. Through the diffraction-based overlap measurement process, light of a specific wavelength is selected to illuminate the overlapping marker region 104 and the scattered light is measured. This scattered light has characteristics formed by light diffracted from the uppermost grating. The characteristics of the scattered light help ensure accurate alignment during the next lithography exposure.

[0069] Figure 1AThe process stages shown correspond to the stages following the formation of the source / drain regions of the transistor and the formation of the source / drain contact structures that contact the source / drain regions. Using a diffraction-based overlap measurement process with overlap marker region 104, a mask for forming conductive vias that contact the source / drain can be configured for alignment. Figure 1B The device area 105 for subsequent process stages is illustrated, in which a conductive via is formed by combining a diffraction-based overlapping process and an overlapping marking area 104.

[0070] Figure 1A and Figure 1B An example is illustrated of aligning and forming a conductive via in contact with the source / drain metal using the principles of this disclosure. However, the principles of this disclosure can be configured to provide an overlap marking region, which is configured to provide alignment marks during the formation of a first metal layer including a metal trace contacting the top of the conductive via. Therefore, Figure 1A The structure of the overlapping marking area 104 shown in the process stage will be used to ensure that an effective diffraction-based overlapping process can be performed to align the next photomask, so that the subsequently formed structure can be correctly aligned and contact the previously formed structure.

[0071] Please see Figure 1A The overlapping marking region 104 includes a masking grating, which includes a plurality of elongated structures 106 extending in the X direction. In some embodiments, the plurality of elongated structures 106 of the masking grating correspond to a plurality of semiconductor fins, but other types of elongated structures may be used for the masking grating without departing from the scope of this disclosure. For example, the elongated structures 106 of the masking grating may include dielectric fins, photoresist fins, conductive fins, metal wires, or other types of elongated structures.

[0072] The elongated structures 106 of the masking grating extend in the X direction and are spaced apart from each other in the Y direction. Although in Figure 1A While not clearly visible, the elongated structure 106 of the masking grating can be disposed on the substrate. The spacing of the elongated structure 106 of the masking grating in the Y direction is between 10 nanometers (nm) and 50 nm, but other spacing values ​​may be used without departing from the scope of this disclosure. The width of the elongated structure 106 of the masking grating in the Y direction is between 10 nm and 50 nm, but other width values ​​may be used without departing from the scope of this disclosure. Further details regarding the material of the elongated structure 106 of the masking grating will be provided below. As described in more detail later, the elongated structure 106 can be formed using the same process and from the same material as the semiconductor fin, and the channel region and source / drain region of the transistor are formed in the semiconductor fin of the device region 105.

[0073] The overlapping marking region 104 includes a bottom grating of elongated conductive structures 108 extending in the X direction and spaced apart from each other in the Y direction. Although Figure 1A Not shown in the figure, but the bottom grating of the elongated conductive structure 108 is located on the substrate between adjacent elongated structures 106. The elongated conductive structures 108 have different spacing in the Y direction, as described in more detail later.

[0074] Before providing further details regarding the bottom grating of the elongated conductive structure 108, it is advantageous to describe the top grating of the elongated conductive structure 110 for the subsequent explanation. The elongated conductive structures 110 extend in the Y direction and are spaced apart from each other in the X direction. The overlapping marking region 104 includes the top grating of the first conductive structure 110. The first metal structure is disposed directly above the semiconductor fin 106. Although Figure 1A Not shown, but the first conductive structure 110 is formed on a dielectric layer covering the semiconductor fin 106. A plurality of first conductive structures 110 extend in the X direction and are spaced apart from each other in the Y direction. The spacing between the plurality of first conductive structures 110 is between 20 nm and 100 nm, but other spacing values ​​may be used without departing from the scope of this disclosure. The width of each first conductive structure 110 in the Y direction is between 10 nm and 50 nm, but other width values ​​may be used without departing from the scope of this disclosure.

[0075] In one possible solution, a single elongated conductive structure 108 exists between each pair of elongated conductive structures 110. However, Figure 1A The overlapping marking region 104 includes a bottom grating of conductive structure 108, wherein multiple conductive structures are laterally arranged between the top gratings of each pair of conductive structures 110. This solution offers the following advantages. For example, due to the different pattern sizes of the bottom and top gratings, material differences (n / k) and interference ranges arise. Therefore, the accuracy of diffraction-based overlap alignment processes can be improved. In particular, due to the different sensitivities of the polarization source to vertical and horizontal patterns, this solution further enhances the accuracy of diffraction-based overlap alignment processes.

[0076] In some embodiments, the spacing between the conductive structures 108 of the bottom grating is different from the spacing between the conductive structures 110 of the top grating. Figure 1AIn the example, the leftmost conductive structure 108 in the bottom grating between the leftmost conductive structure 110 in the top grating and the middle conductive structure 110 is referred to as the first conductive structure 108. The first conductive structure 108 in the bottom grating is spaced from the leftmost conductive structure 110 in the top grating by dimension D1. The second conductive structure 108 is spaced from the first conductive structure 108 by dimension D2. The third conductive structure 108 is spaced from the second conductive structure 108 by dimension D3. The fourth conductive structure 108 is spaced from the third conductive structure 108 by dimension D4. The fifth conductive structure 108 is spaced from the fourth conductive structure 108 by dimension D5. The sixth conductive structure 108 is spaced from the fifth conductive structure 108 by dimension D5. The seventh conductive structure 108 is spaced from the sixth conductive structure 108 by dimension D4. The eighth conductive structure 108 is spaced from the seventh conductive structure 108 by dimension D3. The ninth conductive structure 108 is spaced from the eighth conductive structure 108 by dimension D2. The second conductive structure 110 of the top grating may be spaced apart from the ninth conductive structure 108 by dimension D1.

[0077] In some embodiments, dimension D1 is smaller than dimension D2. Dimension D2 is smaller than dimension D3. Dimension D3 is smaller than dimension D4. Dimension D4 is smaller than dimension D5. Alternatively, dimension D1 and dimension D2 may be equal. Dimension D3 and dimension D4 may be equal. Dimension D5 and dimension D4 may be equal.

[0078] In some embodiments, dimension D1 is between 0 nm and 30 nm. In some embodiments, dimension D2 is between 24 nm and 76 nm. In some embodiments, dimension D3 is between 24 nm and 76 nm. In some embodiments, dimension D4 is between 24 nm and 76 nm. In some embodiments, dimension D5 is between 24 nm and 76 nm. Other dimensions may be used without departing from the scope of this disclosure. Without departing from the scope of this disclosure, the conductive structures 108 of the bottom grating located between adjacent pairs of conductive structures 110 of the top grating may be of other numbers.

[0079] In some embodiments, the conductive structure 108 of the bottom grating between each pair of conductive structures 110 in the top grating may have different widths. For example... Figure 1A The conductive structure 108 of the bottom grating between the middle conductive structure 110 and the right conductive structure 110 in the top grating shown can have a size D6. The conductive structure 108 to the right of the middle conductive structure 108 can have a size D7. The next conductive structure 108 to the right can have a size D8. The next conductive structure 108 to the right can have a size D9. The next conductive structure 108 to the right (closest to the right conductive structure 110 in the top grating) can have a size D10.

[0080] In some embodiments, dimension D10 is smaller than dimension D9. Dimension D9 is smaller than dimension D8. Dimension D8 is smaller than dimension D7. Dimension D7 is smaller than dimension D6. Alternatively, dimensions D8, D9, and D10 may be equal. Dimension D6 and D7 may be equal.

[0081] In some embodiments, dimension D6 is between 24 nm and 80 nm. In some embodiments, dimension D7 is between 24 nm and 80 nm. In some embodiments, dimension D8 is between 24 nm and 80 nm. In some embodiments, dimension D9 is between 24 nm and 80 nm. In some embodiments, dimension D10 is between 24 nm and 80 nm. Other dimensions may be used without departing from the scope of this disclosure.

[0082] The conductive structure 108 may comprise polysilicon or another material. As described in more detail later, in some embodiments, the conductive structure 108 is formed using the same material and the same process as the dummy gate structure, which is located in device region 105 and corresponds to the location of the gate metal to be formed subsequently. In some embodiments, the first conductive structure 110 is formed of the same metal as the source / drain contacts formed in device region 105 and in the same deposition process. The first conductive structure 110 may comprise tungsten, titanium, tantalum, aluminum, copper, gold, or other suitable conductive materials.

[0083] Please see Figure 1B Device region 105 includes semiconductor fins 107. Semiconductor fins 107 correspond to the channel region and source / drain region of the transistor formed within them, respectively. Semiconductor fins 107 extend in the X direction and are spaced apart from each other in the Y direction. Semiconductor fins 107 are initially formed using the same process as semiconductor fins 106 forming the overlapping marking region, but subsequent processes alter the composition of semiconductor fins 107, as described in more detail later.

[0084] Device region 105 includes a conductive structure 109. The conductive structure 109 corresponds to the location of the gate metal formed in a subsequent process. Although in Figure 1B Not shown, but the conductive structure 109 is formed on the same substrate as the semiconductor fin 107. However, the conductive structure 109 is formed after the semiconductor fin 107. Furthermore, when the conductive structure 109 intersects with the semiconductor fin 107, the conductive structure 109 covers the semiconductor fin 107. The semiconductor fin 107 can be described as a dummy gate structure. The conductive structure 109 is first formed using the same process as the conductive structure 108 in the bottom grating that forms the overlapping marker region 104.

[0085] Device region 105 includes source / drain contacts 111. Source / drain contacts 111 cover the source / drain regions formed in the semiconductor fin 107. Figure 1B (Not shown in the diagram) and contacts the source / drain region. The source / drain contact 111 is made of the same material as the first conductive structure 110 of the overlapping marking region 104 and is formed in the same deposition process. The source / drain contact 111 corresponds to a metal connection structure.

[0086] As mentioned above, Figure 1B It is illustrated Figure 1A The subsequent process stage of the device area 105. Specifically, through Figure 1A The overlapping marking area 104 is used to perform a diffraction-based overlapping process to align the configuration and form a mask for the conductive via 113 that contacts the source / drain contacts 111. Therefore, Figure 1B The diagram illustrates a device region 105 where an alignment process has been performed and a conductive via 113 has been formed. The conductive via 113 contacts the top of the source / drain contacts 111 and provides an electrical connection to the source / drain contacts 111. The conductive via 113 corresponds to a metal connection structure. Other metal wires or other types of connection structures that can be formed according to the principles of this disclosure and provide electrical connections to various locations in the device region 105 are also within the scope of this disclosure.

[0087] Figure 1C This is a cross-sectional view of the overlapping marked region 104 taken along the cross-sectional line OY according to some embodiments. Integrated circuit 102 includes a substrate 120. The substrate 120 may be a semiconductor substrate, such as a bulk semiconductor or other type of semiconductor substrate, and the substrate 120 may be doped (e.g., by p-type or n-type dopant) or undoped. The semiconductor material of the substrate 120 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multilayer, or gradient substrates, may also be used.

[0088] An elongated structure 106 is located on a substrate 120. In some embodiments, the elongated structure 106 is a semiconductor fin, and the elongated structure 106 includes a plurality of alternating semiconductor layers 124 and sacrificial semiconductor layers 122. In some embodiments, the semiconductor layers 124 may be formed of a first semiconductor material suitable for semiconductor nanostructure transistors, such as silicon, silicon germanium, silicon carbide, etc., while the sacrificial semiconductor layer 122 may be formed of a second semiconductor material having etchability selectivity relative to the material of the semiconductor layers 124, such as silicon germanium, silicon, etc. Each layer of the semiconductor fin 106 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), and molecular beam epitaxy (MBE).

[0089] The conductive structure 108 is located on the substrate 120. The conductive structure 108 is located between the semiconductor fins 106. Although in Figure 1C While not clearly visible, the interlayer dielectric layer 126 is located on the substrate 120 and between the elongated structure 106 and the conductive structure 108. Furthermore, the top surface of the interlayer dielectric layer 126 is substantially coplanar with the top surface of the conductive structure 108 (see [reference]). Figure 1D The interlayer dielectric layer 126 may include silicon oxide, silicon nitride, SiCO, SiCN, SiCON or other suitable dielectric materials.

[0090] Integrated circuit 102 includes an interlayer dielectric layer 128 on an interlayer dielectric layer 126. The interlayer dielectric layer 128 may include silicon oxide, silicon nitride, SiCO, SiCN, SiCON, or other suitable dielectric materials. The top surface of the interlayer dielectric layer 128 is substantially coplanar with the top surface of the conductive structure 110.

[0091] Integrated circuit 102 includes an interlayer dielectric layer 128 and a dielectric layer 130 on conductive structure 110. The interlayer dielectric layer 128 may include silicon nitride or other suitable dielectric materials.

[0092] Integrated circuit 102 includes an interlayer dielectric layer 132 on dielectric layer 130. Interlayer dielectric layer 132 may include silicon oxide, silicon nitride, SiCO, SiCN, SiCON or other suitable dielectric materials.

[0093] Figure 1D It is along Figure 1AThe cross-sectional view of the overlapping marked area 104 is taken by the cross-sectional line OX. The first conductive structure 110 is located on the top surface of the interlayer dielectric layer 126. The first conductive structure 110 may include Al, W, Ti, TiN, Ta, Co, or other suitable conductive materials. The height of the first conductive structure 110 in the Z direction is between 5 nm and 100 nm, but other height values ​​may be used without departing from the scope of this disclosure. The first conductive structure 110 may be made of other materials and other thicknesses without departing from the scope of this disclosure.

[0094] Integrated circuit 102 includes an interlayer dielectric layer 128 located on interlayer dielectric layer 126. Interlayer dielectric layer 128 may include silicon oxide, silicon nitride, SiCO, SiCN, SiCON or other suitable dielectric materials. The top surface of interlayer dielectric layer 128 is substantially coplanar with the top surface of conductive structure 110.

[0095] Integrated circuit 102 includes a dielectric layer 130 located on an interlayer dielectric layer 128 and a conductive structure 110. The dielectric layer 130 may include silicon nitride or other suitable dielectric materials.

[0096] Integrated circuit 102 includes an interlayer dielectric layer 132 located on dielectric layer 130. Interlayer dielectric layer 132 may include silicon oxide, silicon nitride, SiCO, SiCN, SiCON or other suitable dielectric materials.

[0097] Figure 1E and Figure 1F This is a cross-sectional view of the device region 105 of the integrated circuit 102 according to some embodiments. Figure 1E It is along Figure 1B The view captured by the section line DX in the diagram. Figure 1F It is along Figure 1B The section line DY is used to cut the data.

[0098] Please see Figure 1E The semiconductor fin 107 has been fabricated into a gate-all-around field-effect transistor (GAT), and the GAT has stacked channels 125 and source / drain regions 134. Sacrificial semiconductor nanostructures 123 are located between the stacked channels 125. The material of the channels 125 is the same as the material of the semiconductor layer 124. The material of the sacrificial semiconductor nanostructures 123 is the same as the material of the sacrificial semiconductor layer 122.

[0099] Channel 125 may correspond to a semiconductor nanostructure and can be patterned using any suitable method. For example, one or more lithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the structure. Generally, dual-patterning or multi-patterning processes combine lithography with self-alignment processes, and can achieve patterns with smaller spacing compared to, for example, using a single lithography process directly. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern a nanostructure transistor structure.

[0100] Channel 125 may also be referred to as a semiconductor nanosheet, but other types of semiconductor nanostructures may be used without departing from the scope of this disclosure. Channel 125 may comprise a single-crystal semiconductor material, such as silicon, silicon germanium, or other semiconductor materials. Channel 125 may be an intrinsic semiconductor material or a doped semiconductor material. The semiconductor nanostructure may comprise nanosheets, nanowires, or other types of nanostructures. The thickness of channel 125 in the Z direction may be between 2 nm and 5 nm. The width of channel 125 in the X direction may be between 5 nm and 15 nm. Channel 125 may be made of other materials and have other sizes without departing from the scope of this disclosure.

[0101] An inner spacer 136 is also formed in the recess of the sacrificial semiconductor nanostructure 123. The inner spacer 136 may include silicon oxide, silicon nitride, SiCN, SiCON, SiCO or other suitable dielectric materials. The inner spacer 136 electrically isolates the source / drain region 134 from the gate metal (not shown).

[0102] Although Figure 1B The conductive structure 109 and the sacrificial semiconductor nanostructure 123 are illustrated, but in reality, in Figure 1B In the process stages shown, the conductive structure 109 and the sacrificial semiconductor nanostructure 123 may have been replaced by one or more gate metals, and one or more gate metals wrap the channel 125 and fill the space left after the removal of the sacrificial semiconductor nanostructure 123 and the conductive structure 109.

[0103] The source / drain region 134 can be formed by etching the semiconductor fin 107 outside the channel 125 and then performing epitaxial growth. The source / drain region 134 can be formed by in-situ doping with P-type or N-type dopant during the epitaxial growth process.

[0104] Transistor 137 may include a gate dielectric (not shown) located between channel 125 and gate metal. Channel 125 extends along the X direction between source / drain regions 134.

[0105] Source / drain contacts 111 are located on source / drain regions 134. Source / drain contacts 111 correspond to the metallic structure electrically and physically coupled to source / drain regions 134. Source / drain contacts 111 are made of the same material as the first conductive structure 110 and formed in the same deposition process. Although Figure 1E Although not shown in the figure, the silicide layer can be directly disposed between the source / drain region 134 and the source / drain contact 111. Figure 1E Also Figure 1C The diagram shows interlayer dielectric layers 128 and 132 and dielectric layer 130.

[0106] Transistor 137 can typically be operated as follows. A gate voltage can be applied to the gate metal (not shown) to turn channel 125 on or off. In the example of an N-channel transistor, a grounded gate voltage can turn off transistor 137, while a VDD gate voltage can turn it on. In the example of a P-channel transistor, a grounded gate voltage can turn on transistor 137, while a VDD gate voltage will turn it off. If transistor 137 is on and there is a voltage difference between the source and drain regions 134, current can flow between the source and drain regions 134 through each channel 125. Voltage can be applied to the source and drain regions 134 through portions of the source / drain contacts 111. Conductive via 113 in Figure 1E It is not shown in the text.

[0107] Figure 1F The interlayer dielectric layer 126 located between the source / drain regions 134 in the Y direction is illustrated. Figure 1F The source / drain contacts 111 located on the interlayer dielectric layer 126 are also shown. Figure 1F A conductive via 113 is shown that extends through the interlayer dielectric layer 132 and the dielectric layer 130 and is connected to the source / drain contact 111.

[0108] As mentioned above, the conductive via 113 is formed using a diffraction-based overlay measurement process, which utilizes the bottom grating of the conductive structure 108 and the top grating of the conductive structure 110 in the overlay marking region 104. Following this process, the bottom grating of the conductive structure 108 and the top grating of the conductive structure 110 in the overlay marking region 104 can be used as diffraction gratings for the diffraction-based overlay measurement process. The multiple conductive structures 108 of the bottom grating present between each pair of conductive structures 110 in the top grating help ensure that the diffraction-based overlay measurement process effectively assists in the alignment process to form subsequent metal lines.

[0109] Figure 1GThis is a block diagram of an extreme ultraviolet (EUV) lithography (EUV) system 100 according to some embodiments. The description of the EUV lithography system 100 helps to understand the part of the process where diffraction-based overlay measurement plays a role in the overall lithography process. It is worth noting that the EUV lithography system 100 includes an EUV generator 140, a scanner 142, and a diffraction-based overlay measurement system 154 located within the scanner 142. As used in this disclosure, the terms "EUV light" and "EUV radiation" are used interchangeably. Although... Figure 1F The explanation mainly concerns EUV lithography, but the principles disclosed herein can be extended to lithography processes other than EUV lithography.

[0110] EUV generator 140 generates EUV light. EUV generator 140 may include a droplet generator, an EUV light generation chamber, a droplet receiver, a scanner 142, and a laser. The droplet generator provides droplets to the EUV light generation chamber. The laser irradiates the droplets with laser pulses within the EUV light generation chamber. The irradiated droplets emit EUV light 144. EUV light 144 is collected by a collector and reflected toward scanner 142. Scanner 142 modulates EUV light 144 and reflects it from photomask 150 (including a mask pattern), focusing EUV light 144 onto wafer 101. EUV light 144 patternes layers on wafer 101 according to the pattern of photomask 150. The various processes will be described in more detail below. Wafer 101 includes multiple integrated circuits 102.

[0111] Scanner 142 includes scanner optics 146. Scanner optics 146 includes a series of optical adjustment devices to guide EUV light 144 to photomask 150. Scanner optics 146 may include refractive optics, such as lenses or a lens system with multiple lenses (zone plates). Scanner optics 146 may include reflective optics, such as a single mirror or a mirror system with multiple mirrors. Scanner optics 146 guides ultraviolet light from the EUV light generation chamber to photomask 150.

[0112] Figure 1G The image shows a photomask 150 in the scanner 142. The photomask 150 is mounted on a photomask stage 148. The photomask stage 148 can be translated in the X, Y, and Z directions to ensure proper alignment with the wafer 101.

[0113] During the EUV exposure process, EUV light 144 is reflected from photomask 150 to another optical element of scanner optics 146. In some embodiments, scanner optics 146 includes a projection optics box. The projection optics box may have refractive optics, reflective optics, or a combination of refractive and reflective optics. The projection optics box guides EUV light 144 onto wafer 101 (e.g., a semiconductor wafer).

[0114] EUV light 144 includes a pattern from photomask 150. Specifically, photomask 150 includes a pattern to be defined in wafer 101. After reflection from photomask 150, EUV light 144 will contain the pattern of photomask 150. During extreme ultraviolet lithography, a photoresist layer typically covers wafer 101. The photoresist helps to pattern the surface of semiconductor wafer 101 according to the pattern of the photomask.

[0115] The wafer stage 152 can carry the wafer 101 during the lithography process. The wafer stage 152 can be translated in the X, Y and Z directions to facilitate the alignment of the photomask 150 and the wafer 101.

[0116] The diffraction-based overlap measurement system 154 facilitates the alignment of the photomask 150 and the wafer 101 during a diffraction-based overlap measurement process. The wafer 101 may include a large number of integrated circuits 102. Since each exposure can pattern a single integrated circuit, the diffraction-based overlap measurement system 154 can perform diffraction-based overlap measurements on the individual integrated circuits of the wafer 101. The diffraction-based overlap measurement system 154 illuminates the wafer 101 with light of a specific wavelength, such as light with wavelengths between 400 nm and 850 nm. More specifically, the diffraction-based overlap measurement system 154 illuminates the overlap marking region 104 of the integrated circuits 102 being aligned. A grating of a second metal structure is used as a diffraction grating and receives the light from the diffraction-based overlap measurement system 154. The diffraction-based overlap measurement system 154 senses the diffracted light and calculates whether alignment is achieved based on the diffracted light.

[0117] Scanner 142 may include control system 156, which controls the components of EUV lithography system 100. Control system 156 may be coupled to diffraction-based overlay measurement system 154 and may adjust the positions of wafer 101 and photomask 150 to at least partially control diffraction-based overlay measurement system 154.

[0118] Figure 1H This is a top view of wafer 101 according to some embodiments. Wafer 101 may correspond to a semiconductor wafer comprising a plurality of identical integrated circuits 102. During patterning, each integrated circuit 102 may be individually exposed to EUV light 144 via photomask 150 (e.g., as shown in the image). Figure 1G (As shown).

[0119] Figure 1I A simplified top view of an integrated circuit 102 on a wafer 101 according to some embodiments is illustrated. The integrated circuit 102 includes an overlap marking region 104 and a device region 105. The overlap marking region 104 may include, for example... Figure 1A , Figure 1C and Figure 1D The structure shown. Although Figure 1I Only a single overlapping marker region 104 is shown, but in reality, integrated circuit 102 may include multiple overlapping marker regions 104. Device region 105 may include, for example... Figures 1B to 1E and Figure 1F The features and structures shown also include other features and structures not shown.

[0120] Figure 2A and Figure 2B According to some embodiments Figure 1A A cross-sectional view of the overlapping marked area 104. Figure 2A and Figure 2B In the design, an elongated structure 106 of the shielding grating is formed on the top surface of the interlayer dielectric layer 151 and is covered by the interlayer dielectric layer 153. A conductive structure 108 of the bottom grating is formed on the top surface of the interlayer dielectric layer 153 and is covered by the interlayer dielectric layer 155. A conductive structure 110 of the top grating is formed on the top surface of the interlayer dielectric layer 155 and is covered by the interlayer dielectric layer 157. Figure 1A , Figure 1C and Figure 1D The dimensions D1-D10 shown can be used in this embodiment. Figure 2A and Figure 2B The horizontal spacing can be with Figure 1A , Figure 1C and Figure 1D The lateral spacing shown is the same. The materials of the elongated structure 106, conductive structure 108, and conductive structure 110 may be the same as or different from those described above. In some embodiments, the conductive structure 108 of the bottom grating and the conductive structure 110 of the top grating may be configured to align the mask to pattern metal lines or form conductive vias. The materials of the interlayer dielectric layers 151, 153, 155, and 157 may be the same as those of the aforementioned interlayer dielectric layers 126, 128, 132, and dielectric layer 130.

[0121] Figure 3 An overlapping marking region 104 of an integrated circuit 102 according to some embodiments is illustrated. The overlapping marking region 104 includes a masking grating of an elongated structure 106. The elongated structure 106 can be substantially as follows: Figure 1A , Figure 1C and Figure 1D or Figure 2A and Figure 2B The same as described above. The process, components, structure, and relative vertical position of the overlapping marking area 104 can be the same as, for example... Figures 1A to 2B The same as described above.

[0122] The overlapping marking region 104 includes a bottom grating of an elongated conductive structure 108. The bottom grating of the conductive structure 108 includes elongated conductive structures 108a and 108b. The material of the conductive structure 108 can be... Figure 1A , Figure 1C and Figure 1D or Figure 2A and Figure 2B The materials used are the same. The conductive structure 108 can also be formed on the same substrate 120 as the elongated structure 106, such as... Figure 1C And as described in 1D. Alternatively, the conductive structure 108 can be formed on different interlayer dielectric layers, such as Figure 2A and Figure 2B As stated above.

[0123] The overlapping marking region 104 includes a top grating of an elongated conductive structure 110. The material of the conductive structure 110 can be similar to... Figure 1A , Figure 1C and Figure 1D The materials described are the same. The conductive structure 110 can also be formed on the interlayer dielectric layer, such as... Figure 1C and the first or Figure 2A and Figure 2B As stated above.

[0124] The bottom grating of the conductive structure 108 includes multiple patterns. A first pattern includes multiple groups of conductive structures 208. A second pattern includes multiple groups of conductive structures 308. The conductive structures 208 extend in the Y direction and are spaced apart from each other in the X direction. Each group of conductive structures 208 includes four conductive structures 208. Each conductive structure 208 extends across multiple elongated structures 106 of the grating. Figure 3 In this embodiment, the conductive structures 208 in each group have the same dimension D12, and are spaced apart by a dimension D11. Dimension D11 can be between 24 nm and 76 nm. Dimension D12 can be between 24 nm and 80 nm. However, in some embodiments, the widths of the conductive structures 208 in each group can be different, and they can be spaced apart by different dimensions. Furthermore, the number of conductive structures 208 in each group differs from the number of conductive structures 208 in other groups.

[0125] Conductive structures 308 extend in the X direction and are spaced apart from each other in the Y direction. Each group of conductive structures 308 includes two conductive structures 308 located between adjacent pairs of conductive structures 110. Each conductive structure 308 overlaps with the same elongated structure 106. Each conductive structure 110 of the top grating is offset from the adjacent conductive structure 308 by a distance D13. Each conductive structure 308 in each group is spaced apart from each other in the Y direction by dimension D14. Each conductive structure 308 is spaced apart from the conductive structure 308 of the adjacent top grating in the Y direction by dimension D15. Each pair of conductive structures 110 is spaced apart by dimension D16. The distance D13 may be between 105 nm and 145 nm. Dimension D14 may be between 42 nm and 72 nm. Dimension D15 may be between 1 nm and 31 nm. Dimension D16 may be between 180 nm and 240 nm. Other distances / dimensions may be used without departing from the scope of this disclosure.

[0126] The adjacent groups of the conductive structure 308 of the bottom grating and the conductive structure 110 of the top grating can be good columns. The conductive structures 308 of the bottom grating and the conductive structures 110 of the top grating in each column can be located between adjacent groups of the conductive structures 208 of the bottom grating.

[0127] Figure 3 The overlapping marking area 104 shown can be configured to form Figure 1B , Figure 1E and Figure 1F Device area 105 or such Figure 2A and Figure 2B The aforementioned metal interconnect or conductive via.

[0128] Figure 4 This is a flowchart of method 400 according to some embodiments. Method 400 can be performed as follows: Figures 1A to 3 The components, processes, and systems described above are used to achieve this. In step 402, method 400 includes forming a first diffraction grating of a first conductive structure in an overlapping marking region of an integrated circuit through a first deposition process. One example of an overlapping marking region is... Figure 1A The overlapping marking region 104. One example of the first diffraction grating of the first conductive structure is... Figure 1A The first conductive structure 108 has a diffraction grating. In step 404, method 400 includes forming a second diffraction grating of the second conductive structure in an overlapping marked region by a second deposition process, wherein the second diffraction grating is located above and laterally offset from the first conductive structure, wherein corresponding plurality of first conductive structures are laterally located between each pair of adjacent second conductive structures. One example of the second diffraction grating of the second conductive structure is... Figure 1AThe top grating of the second conductive structure 110. In step 406, method 400 includes forming a first metallic connection structure in the device region by a second deposition process. One example of the device region is... Figure 1E Device area 105. One example of the first metal connection structure is... Figure 1E The source / drain contact 111. In step 408, method 400 includes forming a second metal connection structure in the device region by a third deposition process, wherein the second metal connection structure contacts the first metal connection structure and is aligned according to the positions of the first and second diffraction gratings. One example of the second metal connection structure is... Figure 1F Conductive via 113.

[0129] This disclosure provides a method and structure configured to improve component alignment in a wafer fabrication process. The embodiments of this disclosure provide an improved overlap marking region that improves diffraction-based overlap measurements for subsequent mask alignment. When fabricating a wafer, the wafer includes device areas corresponding to functional circuitry of an integrated circuit and overlap marking regions. The overlap marking regions include periodic structures or gratings configured for diffraction-based scattering measurements, enabling alignment to form subsequent features. The overlap marking regions include semiconductor fins extending in a first direction and spaced apart from each other, a dummy gate structure extending in the same direction and located between the semiconductor fins, a grating (made of source / drain contact material) aligned above the semiconductor fins with a first metal structure, and a grating (made of conductive via material) with a second metal structure aligned above the dummy gate structure and above the first metal structure.

[0130] Using a grating with a first metal structure in the overlap marking region helps ensure that the second metal structure has a specific height after the subsequent chemical mechanical planarization (CMP) process. This specific height is sufficient to ensure that subsequent diffraction-based overlap measurement processes can provide a sufficiently strong signal to accurately align the mask configured to form contact source / drain vias in subsequent processes. Accurate alignment ensures reliable contact between the metal lines and the conductive vias. If the grating with the first metal structure is not present in the overlap marking region, the second metal structure may not have sufficient height after the CMP process to provide a sufficiently strong signal for diffraction-based overlap measurement processes. Therefore, using a grating with a first metal structure in the overlap marking region enables better-functioning integrated circuits and higher wafer yields.

[0131] In some embodiments, the integrated circuit includes an overlapping marking region comprising a shielding grating having an elongated structure, a first diffraction grating of a plurality of first conductive structures, and a second diffraction grating of a plurality of second conductive structures. The first diffraction grating includes a plurality of first groups of first conductive structures. A second diffraction grating is located above the first diffraction grating and the shielding grating of the first conductive structures. The second diffraction grating is laterally positioned between each pair of adjacent second conductive structures corresponding to the first conductive structures of each first group. In some embodiments, the elongated structure extends in a first direction, and the first and second conductive structures extend in a second direction perpendicular to the first direction. In some embodiments, each first group includes first conductive structures of different widths. In some embodiments, the first group includes different plurality of spacing distances between adjacent pairs of first conductive structures. In some embodiments, the elongated structure, the first conductive structures of each first group, and the second conductive structures all extend in the first direction. In some embodiments, the first diffraction grating includes a plurality of second groups of first conductive structures, wherein the first conductive structures of each second group extend in a second direction perpendicular to the first direction. In some embodiments, the first conductive structures of each second group extend above the elongated structure. In some embodiments, each second group is located between two adjacent columns of the first group. In some embodiments, the second conductive structure and the first conductive structures of each first group have the same length. In some embodiments, the integrated circuit further includes a substrate, and the first conductive structure and the elongated structure are located on the top surface of the substrate. In some embodiments, the integrated circuit further includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer being located on the elongated structure, and the first conductive structure being located on the top surface of the first interlayer dielectric layer; the second interlayer dielectric layer being located on the first conductive structure, and the second conductive structure being located on the top surface of the second interlayer dielectric layer.

[0132] In some embodiments, the integrated circuit includes a device region. The device region includes source / drain regions of a transistor and a first metal interconnect structure electrically coupled to the source / drain regions, the first metal interconnect structure being made of a first material. The integrated circuit includes an overlapping marking region. The overlapping marking region includes a first diffraction grating of a plurality of first conductive structures and a second diffraction grating of a plurality of second conductive structures located above and offset from the first conductive structures, the second diffraction grating being made of the first material. The first conductive structures are laterally located between each pair of adjacent second conductive structures. In some embodiments, the device region includes a second metal interconnect structure made of a second material and in contact with the first metal interconnect structure. In some embodiments, the first metal interconnect structure is a source / drain contact. In some embodiments, the overlapping marking region includes a shielding grating having a plurality of elongated structures located below the second diffraction grating. In some embodiments, the elongated structures are semiconductor fins. In some embodiments, the first conductive structures are polysilicon.

[0133] In some embodiments, a method of manufacturing an integrated circuit includes forming a first diffraction grating of a plurality of first conductive structures in an overlapping marking region of the integrated circuit using a first deposition process. The method includes forming a second diffraction grating of a plurality of second conductive structures in the overlapping marking region using a second deposition process, wherein the second diffraction gratings of the second conductive structures are located above and offset from the first conductive structures, and the first conductive structures corresponding to the second diffraction gratings are laterally disposed between each pair of adjacent second conductive structures. The method includes forming a plurality of first metal interconnect structures in a device region using a second deposition process, and forming a plurality of second metal interconnect structures in the device region using a third deposition process, wherein the second metal interconnect structures are contacted with the first metal interconnect structures based on aligned first and second diffraction gratings. In some embodiments, the method further includes aligning the first and second conductive structures using an overlapping alignment process based on the diffraction of the first and second diffraction gratings. In some embodiments, the method further includes forming a masking grating having a plurality of elongated structures below the second diffraction gratings.

[0134] In some embodiments, the integrated circuit includes a device region. The device region includes source / drain regions of a transistor and a first metal interconnect structure electrically coupled to the source / drain regions. The integrated circuit includes an overlapping marking region. The overlapping marking region includes a first diffraction grating of a plurality of first conductive structures and a second diffraction grating of a plurality of second conductive structures located above and offset from the first conductive structures. The first conductive structures are laterally located between each pair of adjacent second conductive structures. In some embodiments, the device region includes a second metal interconnect structure and contacts the first metal interconnect structure.

[0135] In some embodiments, an integrated circuit includes an overlapping marking region and a device region. The overlapping marking region includes a plurality of semiconductor fins, a first diffraction grating of a plurality of first conductive structures located on the semiconductor fins, and a second diffraction grating of a plurality of second conductive structures located above and offset from the first conductive structures. The second diffraction gratings are laterally disposed between each pair of adjacent second conductive structures corresponding to the first conductive structures. The device region includes a plurality of first metal connection structures and a plurality of second metal connection structures in contact with the first metal connection structures.

[0136] The foregoing description of the features of various embodiments enables those skilled in the art to better understand the various implementations disclosed herein. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made by those skilled in the art without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, characterized by Comprising: an overlay mark region comprising: a shadow mask of a plurality of elongated structures; a first diffraction grating of a plurality of first conductive structures comprising a plurality of first groups of the plurality of first conductive structures; and a second diffraction grating of a plurality of second conductive structures over the first diffraction grating of the plurality of first conductive structures and the shadow mask, wherein each of the first groups of the plurality of first conductive structures is laterally between each pair of adjacent ones of the plurality of second conductive structures.

2. The integrated circuit of claim 1, wherein, wherein the plurality of elongated structures extend in a first direction, wherein the plurality of first conductive structures and the plurality of second conductive structures extend in a second direction perpendicular to the first direction.

3. The integrated circuit of claim 1, wherein, wherein the plurality of elongated structures, each of the first groups of the plurality of first conductive structures, and the plurality of second conductive structures all extend in a first direction.

4. The integrated circuit of claim 3, wherein, wherein the first diffraction grating comprises a plurality of second groups of the plurality of first conductive structures, wherein each of the second groups of the plurality of first conductive structures extends in a second direction perpendicular to the first direction.

5. The integrated circuit of claim 1, wherein, further comprising: a first interlayer dielectric layer over the plurality of elongated structures, wherein the plurality of first conductive structures are on a top surface of the first interlayer dielectric layer; and a second interlayer dielectric layer over the plurality of first conductive structures, wherein the plurality of second conductive structures are on a top surface of the second interlayer dielectric layer. Comprising:

6. An integrated circuit, characterized by a device region comprising: a source / drain region of a transistor; and a first metal connection structure electrically coupled to the source / drain region; and an overlay mark region comprising: a first diffraction grating of a plurality of first conductive structures; and a second diffraction grating of a plurality of second conductive structures over and offset from the plurality of first conductive structures, wherein the plurality of first conductive structures are laterally between each pair of adjacent ones of the plurality of second conductive structures. wherein the device region comprises a second metal connection structure, and the second metal connection structure is in contact with the first metal connection structure.

7. The integrated circuit of claim 6, wherein, wherein the first metal connection structure is a source / drain contact.

8. The integrated circuit of claim 7, wherein, wherein the overlay mark region comprises a shadow mask having a plurality of elongated structures, and the shadow mask is under the second diffraction grating.

9. The integrated circuit of claim 8, wherein, Comprising:

10. An integrated circuit, characterized by an overlay mark region comprising: a plurality of semiconductor fins; a first diffraction grating of a plurality of first conductive structures over the plurality of semiconductor fins; and a second diffraction grating of a plurality of second conductive structures over and offset from the plurality of first conductive structures, wherein the second diffraction grating is laterally between each pair of adjacent ones of the plurality of second conductive structures corresponding to the plurality of first conductive structures; and a device region comprising: a plurality of first metal connection structures; and a plurality of second metal connection structures in contact with the plurality of first metal connection structures. ​

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