Interconnection layer structure

Abstract

The disclosure relates to an interconnect layer structure. The interconnection layer includes a first region and a second region. The first region includes a first dielectric layer and a first interconnect structure. The second region includes a second dielectric layer and a second interconnect structure. The first region has a first ratio of a metallic surface area to a non-metallic surface area in the first region. The second region has a second ratio of a metallic surface area to a non-metallic surface area in the second region. The first ratio is different from the second ratio. The first dielectric layer and the second dielectric layer include dielectric materials selected and / or processed differently according to the first ratio and the second ratio, substantially corresponding to the polishing rates of the first region and the second region in the planarization process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an interconnect layer structure. BACKGROUND

[0002] In semiconductor manufacturing, some processes such as chemical mechanical polishing (CMP) process are performed to planarize an interconnect layer including metal structures and dielectric materials. Variations in metal density of the interconnect layer in different regions can cause uneven polishing rate, which in turn causes uneven surface of the interconnect layer and affects structures subsequently formed above the interconnect layer. SUMMARY

[0003] Some embodiments of the present disclosure provide an interconnect layer structure including a first dielectric region and a second dielectric region on a substrate. The first dielectric region includes a first dielectric material and a first metal structure. The second dielectric region includes a second dielectric material and a second metal structure. The second dielectric material is different from the first dielectric material. A top surface of the first dielectric region is coplanar with a top surface of the second dielectric region. The first metal structure has a first density, and the second metal structure has a second density different from the first density.

[0004] Some embodiments of the present disclosure provide an interconnect layer structure including a substrate and an interconnect layer on the substrate. The interconnect layer includes a first region and a second region. The first region includes a first metal structure embedded in a first dielectric layer, and the first dielectric layer includes a first dielectric material. The second region includes a second metal structure embedded in a second dielectric layer, the second dielectric layer includes a second dielectric material different from the first dielectric material, and a thickness of the first dielectric layer is different from a thickness of the second dielectric layer. A first ratio of a first metal surface area to a first non-metal surface area in the first region is less than a reference value. A second ratio of a second metal surface area to a second non-metal surface area in the second region is greater than the reference value.

[0005] Some embodiments of the present disclosure provide an interconnect layer structure including a substrate, a first region on the substrate, and a second region on the substrate and adjacent to the first region, wherein a top surface of the first region is coplanar with a top surface of the second region. The first region includes a first portion of a first dielectric layer in the first region and a first metal structure embedded in the first portion of the first dielectric layer. The second region includes a second portion of the first dielectric layer in the second region, a second dielectric layer on the second portion of the first dielectric layer, and a second metal structure embedded in the second portion of the first dielectric layer and the second dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various embodiments of the present disclosure can be better understood when read from the following detailed description with appropriate Figs. 1-4.

[0007] Figures 1A-1E is a cross-sectional view of a structure including an interconnect layer according to some embodiments;

[0008] Figure 2 is a flowchart of a method configured to analyze an interconnect layer to determine regions of the interconnect layer having different metal densities according to some embodiments;

[0009] Figure 3 and Figure 4 is a cross-sectional view of a structure including an interconnect layer according to some embodiments;

[0010] Figure 5 is a flowchart of a manufacturing method configured to form an interconnect layer according to some embodiments; and

[0011] Figures 6-12 is a cross-sectional view of an intermediate structure during manufacturing of an interconnect layer according to some embodiments.

[0012] [SYMBOL DESCRIPTION]

[0013] 100: semiconductor structure

[0014] 102, 302: substrate

[0015] 110, 111, 112, 114, 119: dielectric layer

[0016] 112, 114, 122, 124: sublayer

[0017] 116, 118, 126, 127, 128: interconnect structure / metal structure

[0018] 120, 121, 122, 123, 124: dielectric layer

[0019] 200, 500: method

[0020] 205, 210, 215, 505, 510, 515, 520, 525, 530: step 300: structure

[0021] 310: interconnect layer

[0022] 330, 416, 418: metal structure

[0023] 330a, 330b: metal line

[0024] 720: opening

[0025] 1015: first opening / opening

[0026] 1017: second opening / opening

[0027] 1119: metal layer

[0028] D1, D2, D3: Thickness

[0029] L11, L12: Width

[0030] M1, M2: Interconnection layer

[0031] R11, R12, R21, R22, R23: Regions

[0032] S11, S12: Spacing

[0033] T11, T12, T21, T21: Thickness

[0034] W11, W12, W21, W22: Width

[0035] x, y, z: axes Detailed Implementation

[0036] The following disclosure provides many different embodiments or examples of configurations to achieve different features of the subject matter of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely exemplary and are not intended to limit this disclosure. For example, as described later, forming a first feature over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact.

[0037] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe an element or feature relative to another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptions used in this disclosure may be interpreted similarly and accordingly.

[0038] In some embodiments, the terms “about” and “substantially” may indicate a given value varying within 5% of that value (e.g., values ​​of ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely exemplary and are not intended to limit this disclosure. It should be understood that the terms “about” and “substantially” may refer to a percentage of a value that can be interpreted by a person of ordinary skill in the art based on the teachings of this disclosure.

[0039] A process flow of semiconductor fabrication can include planarizing a surface of a structure to configure for a subsequent process flow. For example, a process of forming an interconnect layer on a substrate can include forming an opening in a dielectric material layer on the substrate, and subsequently blanket depositing a metal material layer (e.g., copper) in the opening. Further, a planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed to remove excess metal material outside the opening and to planarize a top surface of the interconnect layer, which includes a metal surface of the metal material and a non-metal surface of the dielectric material.

[0040] A CMP process includes applying an abrasive and / or corrosive chemical solution (also referred to as a polishing agent) to a polishing pad, and pressing the surface to be planarized against the polishing pad. In this way, planarization is facilitated by a chemical reaction between the polishing agent and the surface, in combination with relative mechanical motion between the surface and the polishing pad. However, different portions of a surface of different materials can have different polishing rates due to different chemical and mechanical properties. In particular, a metal surface and a non-metal surface can have different polishing rates. Thus, the overall polishing rate of a surface region can depend on the ratio of the metal surface area to the non-metal surface area in the region. Surface regions having a higher polishing rate can experience more material loss and over-polishing than surrounding regions having a lower polishing rate and less polishing. As a result, the surface can become non-uniform after the CMP process, sometimes referred to as "dishing." For example, a surface of a first region having a lower ratio of metal surface area to non-metal surface area can be polished more effectively than a surface of a second region having a higher ratio of metal surface area to non-metal surface area, and vice versa. In an example, a surface having different dielectric regions (e.g., oxide regions and nitride regions) can also have different polishing rates. After a CMP process, a non-uniform surface can adversely affect the quality of structures formed on the surface in subsequent processes.

[0041] Embodiments described herein are directed to overcoming the above problems. In some embodiments, an interconnect layer on a substrate can include a first region having a first metal density and a second region having a second metal density, and the second metal density is different from the first metal density. The first region and the second region can also include a first dielectric material and a second dielectric material, respectively. The first dielectric material and the second dielectric material can be different, and can be selected according to different polishing rates of the first dielectric material and the second dielectric material to compensate for polishing differences between the first region and the second region due to different metal densities of the first region and the second region, thereby reducing (or even preventing) dishing.

[0042] According to some embodiments, asFigure 1A A semiconductor structure 100 is shown having multiple interconnect layers Ml and M2 formed over a substrate 102. Figure 1A A cross-sectional view of a semiconductor structure 100 is shown, according to some embodiments, and x, y, z axes are shown for reference. The semiconductor structure 100 can be included in a microprocessor, memory unit, or other integrated circuit (IC).

[0043] Referring to Figure 1AIn some embodiments, substrate 102 can include a semiconductor material, such as silicon. In some embodiments, substrate 102 can include a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 102 can include (i) elemental semiconductors, such as silicon (Si) or germanium (Ge); (ii) compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) alloy semiconductors, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) combinations thereof. In some embodiments, substrate 102 can be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, substrate 102 can be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the lattice direction of substrate 102 can be (100), (110), or (111). In some embodiments, substrate 102 can include a semiconductor structure. For example, substrate 102 can include one or more layers of semiconductor devices and one or more layers of interconnect layers. In some embodiments, substrate 102 can include one or more layers of semiconductor elements, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), gate-all-around FETs (GAA FETs), complementary FETs (CFETs), and / or vertical FETs (VFETs). In some embodiments, substrate 102 can further include one or more layers of interconnect layers, and the one or more layers of interconnect layers connect the semiconductor devices between the one or more layers of semiconductor devices. In some embodiments, the interconnect layers in substrate 102 can be the same as or similar to interconnect layers Ml and M2.

[0044] Interconnect layer Ml can include a plurality of regions, such as regions Rl l and R12. Each region can include one or more dielectric layers and interconnect structures located in the dielectric layers. For example, region Rl l can include dielectric layer 111 and interconnect structures 116. Dielectric layer 111 can further include one or more sub-dielectric layers, such as sub-layers 112 and 114. Similarly, region R12 can include dielectric layer 110 and interconnect structures 118. Although not shown, in some embodiments, region Rl l can include one or more sub-dielectric layers, such as sub-layers 112 and 114, and region R12 can include one or more sub-dielectric layers, such as sub-layers 112 and 114. Figure 1AThe illustrated dielectric layer 110 does not include multiple sublayers, while dielectric layer 111 includes two sublayers 112 and 114, but both dielectric layers 110 and 111 may include any number of sublayers. In some embodiments, the top surfaces of regions R11 and R12 may be coplanar. Specifically, the top surfaces of dielectric layers 110 and 111 and the top surfaces of interconnect structures 116 and 118 may be coplanar. In some embodiments, the thickness of interconnect layer M1 may be between about 20 nm and about 300 nm. This thickness range is not limiting, and the thickness of interconnect layer M1 may be thicker or thinner than the provided range.

[0045] Dielectric layers 110 and 111 may each comprise one or more dielectric materials, such as silicon oxide (SiO2) or silicon oxycarbide (SiO2). x C) Silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbide (SiC), silicon carbonitride (SiOCN), silicon germanium oxide (SiGeO) x) or combinations thereof. Dielectric layers 110 and 111 can include different dielectric materials having different properties, such as different dielectric constants, different carbon concentrations, different porosities, different breakdown voltages, and different hardnesses. In some embodiments, the dielectric constant of dielectric layers 110 and 111 can be between about 1 and about 3.9. For example, the dielectric constant of dielectric layers 110 and 111 can be between about 3.7 and about 3.9, between about 3.5 and about 3.7, between about 3.2 and about 3.5, between about 2.7 and about 3.2, or between about 2.4 and about 2.7. In some embodiments, the carbon concentration of dielectric layers 110 and 111 can be between about 0% and about 30%. For example, the carbon concentration of dielectric layers 110 and 111 can be between about 0% and about 5%, between about 5% and about 10%, between about 10% and about 15%, between about 15% and about 20%, between about 20% and about 25%, or between about 25% and about 30%. In some embodiments, the porosity of dielectric layers 110 and 111 can be between about 0% and about 10%. For example, the porosity of dielectric layers 110 and 111 can be between about 0% and about 2%, between about 2% and about 5%, between about 5% and about 8%, or between about 8% and about 10%. In some embodiments, the average size of the pores in dielectric layers 110 and 111 can be between about 3 angstroms and about 15 angstroms. For example, the average size of the pores in dielectric layers 110 and 111 can be between about 3 angstroms and about 5 angstroms, between about 5 angstroms and about 8 angstroms, between about 8 angstroms and about 12 angstroms, or between about 12 angstroms and about 15 angstroms. In some embodiments, the breakdown voltage of dielectric layers 110 and 111 can be between about 5 MV / cm and about 10 MV / cm. For example, the breakdown voltage of dielectric layers 110 and 111 can be between about 5 MV / cm and about 6 MV / cm, between about 6 MV / cm and about 8 MV / cm, or between about 8 MV / cm and about 10 MV / cm.

[0046] Interconnect structures 116 and 118 can be embedded in the main dielectric layers of interconnect structures 116 and 118, respectively. For example, as shown, interconnect structure 116 is embedded in dielectric layer 111, and interconnect structure 118 is embedded in dielectric layer 110. In some embodiments, interconnect structures 116 and 118 can include interconnect lines extending along a horizontal direction (e.g., along the y-axis) and provide electrical connections in interconnect layer Ml. In some embodiments, interconnect structures 116 and 118 can include interconnect vias extending through interconnect layer Ml (e.g., along the z-axis) and provide electrical connections for layers above and below interconnect layer Ml. Figure 1A

[0047] ​The interconnect structures 116 and 118 can each include one or more suitable metallic materials, such as copper (Cu), tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys, and combinations thereof. Thus, the interconnect structures 116 and 118 can also be referred to as metallic structures 116 and 118. In some embodiments, the interconnect structures 116 and 118 can include the same metallic material. For example, the interconnect structures 116 and 118 can include Cu. In some embodiments, the interconnect structures 116 and 118 can include different metallic materials. In some embodiments, the interconnect structures 116 and 118 can each include a seed layer disposed on an interface of a host dielectric layer in which the interconnect structures 116 and 118 are disposed. The seed layer can have a thickness of a few nanometers and can be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The seed layer can serve as an electrode configured to form the interconnect structures 116 and 118 in an electroplating process.

[0048] In some embodiments, the top surfaces of the regions R11 and R12 in the interconnect layer M1 can have different metal densities. The metal density of a region referred to herein refers to the percentage of the metal surface area on the top surface of the region and is configured to quantify how much amount of metal the top surface has. For example, referring to Figure 1A , the top surface of the region R11 includes a metal surface corresponding to the top surface of the interconnect structure 116 and a non-metal surface corresponding to the top surface of the dielectric layer 111. Similarly, the top surface of the region R12 includes a metal surface corresponding to the top surface of the interconnect structure 118 and a non-metal surface corresponding to the top surface of the dielectric layer 110. Denoting the metal surface area in a region as Am and the non-metal surface area in the region as An, the metal density can be expressed as Am / (Am+An). Another ratio Am / An can be configured to quantify the ratio of the metal surface area to the non-metal surface area on the surface to quantify how much proportion of metal the surface has. As shown in the example of Figure 1A , the metal density of the region R11 is greater than the metal density of the region R12.

[0049] In some embodiments, the difference in polishing rate between the metal- rich region Rl l and the metal-poor region Rl 2 during a CMP process can be compensated by selecting the dielectric material of the dielectric layers 110 and 111 such that the overall polishing rate of the regions Rl l and Rl 2 is substantially equivalent, and further, the generation of dishing can be reduced (or even prevented). The dielectric material of the dielectric layers 110 and 111 can be selected according to factors and parameters in the CMP process, such as the type of abrasive, the condition of the polishing pad, the speed of relative motion between the surface to be planarized and the polishing pad, and the pressure applied by the polishing pad on the substrate.

[0050] In some embodiments, if the polishing rate of the metal surface is higher than the polishing rate of the non-metal surface during a CMP process, then the dielectric material of the dielectric layers 110 and 111 can be selected based on this characteristic such that the polishing rate of the dielectric layer 110 of the region Rl 2 is greater than the polishing rate of the dielectric layer 111 of the region Rl l, given that the metal density in the region Rl l is higher than the metal density in the region Rl 2. For example, the dielectric material of the dielectric layer 110 can have a higher porosity, a larger average pore size, a higher carbon concentration, a lower dielectric constant, a lower hardness, and / or a lower breakdown voltage than the dielectric material of the dielectric layer 111. On the other hand, in some embodiments, if the polishing rate of the metal surface is lower than the polishing rate of the non-metal surface during a CMP process, then the dielectric material of the dielectric layers 110 and 111 can be selected based on this characteristic such that the polishing rate of the dielectric layer 110 of the region Rl 2 is less than the polishing rate of the dielectric layer 111 of the region Rl l, given that the metal density in the region Rl l is higher than the metal density in the region Rl 2. For example, the dielectric material of the dielectric layer 110 can have a lower porosity, a smaller average pore size, a lower carbon concentration, a higher dielectric constant, a higher hardness, and / or a lower breakdown voltage than the dielectric material of the dielectric layer 111.

[0051] In some embodiments, the multi-layer structure of the dielectric layers 110 and / or 111 can provide various options for adjusting the polishing rate to compensate for the different metal densities in the regions Rl l and Rl 2. In some embodiments, as shown in FIG. 1C, the polishing rate of the dielectric layer 111 is adjusted by selecting different dielectric materials to form the sub-layers 112 and 114. For example, the sub-layers 112 and 114 can have different porosities, different average pore sizes, different carbon concentrations, different dielectric constants, and / or different breakdown voltages. Since the sub-layers 112 and 114 are both dielectrics, the sub-layers 112 and 114 can also be referred to as dielectric layers 112 and 114. In some embodiments, as shown in FIG. 1D, the polishing rate of the dielectric layer 111 is adjusted by selecting different thicknesses for the sub-layers 112 and 114. For example, the sub-layers 112 and 114 can have different thicknesses, which can result in different polishing rates. Figure 1A Figure 1A ​As shown, the geometry of sublayers 112 and 114 can also affect the polishing rate of dielectric layer 111. For example, dielectric layer 111 may have a total width W11, sublayer 114 may have a width W12, the vertical portion of sublayer 112 may have a thickness T11, and the bottom portion of sublayer 112 may have a thickness T12. In some embodiments, sublayer 112 may be configured to enhance the adhesion of dielectric layer 111 to the substrate 102 and the side surfaces of dielectric layer 110.

[0052] Interconnect layer M2 can be disposed on interconnect layer M1 and can contain multiple regions, such as regions R21, R22, and R23, each region including a dielectric layer and an interconnect structure. For example, as Figure 1A As shown, region R21 includes dielectric layer 120 and interconnect structure 126, region R22 includes dielectric layer 121 and interconnect structure 127, and region R23 includes dielectric layer 123 and interconnect structure 128. Unless otherwise stated, the description of the dielectric layer and interconnect structure of regions R11 and R12 in interconnect layer M1 applies to the dielectric layer and interconnect structure of regions R21, R22, and R23. In some embodiments, regions between different interconnect layers may have substantially the same metal density and the same dielectric layer. For example, regions R11 and R22 may have substantially the same metal density, sublayers 112 and 122 may include the same dielectric material, and sublayers 114 and 124 may include the same dielectric material. Similarly, regions R12 and R21 may have substantially the same metal density, and dielectric layers 110 and 120 may include the same dielectric material. In some embodiments, regions with different metal densities between different interconnect layers may overlap in the vertical direction (e.g., along the z-axis). For example, as Figure 1A As shown, region R22 of interconnect layer M2 may overlap with regions R11 and R12 of interconnect layer M1. In some embodiments, the interconnect structure of a region in an interconnect layer may be electrically coupled to the interconnect structure of a different region in another interconnect layer. For example, as Figure 1A As shown, interconnect structure 118 includes metal wires / vias connected to metal wires / vias in interconnect structures 127 and 128.

[0053] In some embodiments, regions R21, R22, and R23 may have different metal densities. For example, as... Figure 1AAs shown, the metal density of region R22 is greater than the metal density of regions R21 and R23. In some embodiments, the dielectric layers 120, 121, and 122 can comprise different dielectric materials to compensate for the different metal densities of regions R21, R22, and R23, such that the overall polishing rate of regions R21, R22, and R23 can be substantially comparable. When planarizing the interconnect layer M2 in a CMP process, the occurrence of dishing can be reduced (or even prevented). The selection of the dielectric materials of the dielectric layers 120, 121, and 122 according to the metal densities of regions R21, R22, and R23 can follow the same scheme as described above for the selection of the dielectric materials of the dielectric layers 110 and 111 according to the metal densities of regions R11 and R12, and will not be repeated for the sake of simplicity.

[0054] In some embodiments, each of the dielectric layers 120, 121, and 122 can comprise a multi-layer structure. For example, as shown in FIG. 1C, the dielectric layer 121 can comprise sub-layers 122 and 124. Unless otherwise specified, the description of the different dielectric materials and different geometric factors (e.g., width W11 / W21, width W12 / W22, thickness T11 / T21, and thickness T12 / T22) of sub-layers 112 and 114 apply to sub-layers 122 and 124. Figure 1A

[0055] Figure 1B A cross-sectional view of an interconnect layer M1 is shown in FIG. 1A. Figure 1A A cross-sectional view of a variation of the interconnect layer M1 is shown in FIG. 1B. Unless otherwise specified, Figures 1C-1E the description of the dielectric layers and interconnect structures of regions R11 and R12 in the interconnect layer M1 apply to the dielectric layers and interconnect structures of Figure 1A regions R21, R22, and R23 in the interconnect layer M1. Figure 1A Figures 1B-1E

[0056] Please refer to Figure 1C In some embodiments, compared to Figure 1A and Figure 1B , the dielectric layer 111 of region R11 can comprise sub-layer 114, but not sub-layer 112.

[0057] Please refer to Figure 1D In some embodiments, compared to Figure 1A and Figure 1B , the thickness of the dielectric layer 111 of region R11 can be less than the thickness D1 of the interconnect layer M1. For example, as shown in FIG. 1C, the thickness of the dielectric layer 121 of region R22 can be less than the thickness D1 of the interconnect layer M1. Figure 1D ​​​As shown, region R12 can include a first portion of dielectric layer 110 having a thickness Dl, region Rl 1 can include a second portion of dielectric layer 110 having a thickness D2, and thickness D2 is less than thickness Dl. Also, dielectric layer 111 can be disposed on the second portion of dielectric layer 110. In some embodiments, thickness D2 can be determined according to factors and parameters in a CMP process. In some embodiments, the mechanical strength of dielectric layer 111 can be optimized by determining thickness D2. In some embodiments, the ratio of thickness D2 to thickness Dl can be between about 0.1 and about 0.9. In some embodiments, the bottom surfaces of sub-layers 112 and 114 can be in contact with the top surface of the portion of dielectric layer 110. Also, the thicknesses of sub-layers 112 and 114 can be substantially the same. In some embodiments, the thicknesses of sub-layers 112 and 114 can be substantially the same as the thickness of one or more metal lines of interconnect structure 116.

[0058] Referring to Figure 1E In some embodiments, the mechanical strength of dielectric layer 119 can be different from that of dielectric layer 110. For example, the hardness of dielectric layer 119 can be higher than that of dielectric layer 110 to reduce the occurrence of dishing in region R12. Figure 1A and Figure 1B In some embodiments, region R12 further includes dielectric layer 119 disposed on dielectric layer 110 and embedded in the upper portion of interconnect structure 118. In some embodiments, dielectric layer 119 can include a different dielectric material than dielectric layers 110 and / or 111. In some embodiments, the ratio of thickness D3 of dielectric layer 119 to thickness Dl can be between about 0.1 and about 0.9. Similar to the selection of dielectric materials for dielectric layers 110 and 111, the material and geometric factors of dielectric layer 119 can be determined according to factors and parameters in a CMP process. In some embodiments, the hardness of dielectric layer 119 can be different from that of dielectric layers 110 and 111. For example, the hardness of dielectric layer 119 can be higher than that of dielectric layer 110 to reduce the occurrence of dishing in region R12.

[0059] Figure 2 is a flow chart of a method of configuring to analyze an interconnect layer to determine metal density of different regions of the interconnect layer according to some embodiments. For illustration, the steps of Figure 3 and Figure 4 will be explained with reference to Figure 2 and Figure 3 and Figure 4 are cross-sectional views of structures including an interconnect layer according to some embodiments. The steps of method 200 can be performed in different orders or not performed according to specific applications. Therefore, it should be understood that additional processes can be provided before, during, and after method 200, and only some of the other processes can be mentioned in the present disclosure.

[0060] In step 205, the metal density of metal structures in the interconnect layer is determined. For example, as shown in Figure 3As shown, structure 300 may include an interconnect layer 310 on substrate 302. Interconnect layer 310 may include a metal structure 330. Metal structure 330 may include components related to… Figure 1A The interconnect structures shown are the same or similar to multiple interconnect structures 116, 118, 126, 127 and 128. Figure 3 The diagram illustrates (i) a metal line 330a having a width L11 and a spacing S11 between the metal line 330a and adjacent metal lines, and (ii) a metal line 330b having a width L12 and a spacing S12 between the metal line 330b and adjacent metal lines. The width-to-spacing ratios L11 / S11 and L12 / S12 can be configured to determine the metal density of different portions of the metal structure 330.

[0061] For example, such as Figure 3 As shown, since the width L11 is greater than the width L12 and the spacing S11 is less than the spacing S12, the ratio of width to spacing L11 / S11 is greater than the ratio of width to spacing L12 / S12, meaning that the metal density around metal line 330a is greater than the metal density around metal line 330b. In some embodiments, sample calculations can be performed on multiple metal lines in a portion of the metal structure 330, and the metal density of that portion of the metal structure 330 can be determined by averaging the ratio of the width to spacing of the metal lines in each sample. In some embodiments, the metal density of the metal structure 330 can be determined as a function of coordinates on the top surface of the interconnect layer 310 to quantify how the metal density varies in different portions of the metal structure 330.

[0062] Please see Figure 2 In step 210, the region of the interconnect layer can be determined based on the metal density of the portion of the metal structure in the region. In this embodiment, the metal density of the portion of the metal structure in the region is also referred to as the metal density of that region. For example, such as Figure 4 As shown, regions R11 and R12 can be defined in interconnect layer 310, where the metal density of region R11 is greater than that of region R12. Once regions with different metal densities are determined, the metal structure can be divided into interconnect structures of different regions. For example, as... Figure 4 As shown, the metal structure 330 is divided into metal structures 416 and 418, respectively included in regions R11 and R12. Metal structures 416 and 418 can respectively correspond to... Figure 1A The interconnect structures 116 and 118 are shown.

[0063] In some embodiments, determining the regions of the interconnect layer may include comparing the metal density of different portions of the metal structure 330 with a reference value. For example, if the ratio of the average width of a portion of the metal structure 330 to the pitch is greater than the reference value, then that portion belongs to region R11. Similarly, if the ratio of the average width of this portion of the metal structure 330 to the pitch is less than the reference value, then that portion belongs to region R12. In some embodiments, the ratio of the average width to the pitch of the portions in region R11 or R12 is substantially equal to the ratio of the metal surface area to the non-metal surface area in region R11 or R12. In some embodiments, the reference value may be between about 1.0 and about 3.0. For example, the reference value may be between about 1.0 and about 1.4, between about 1.4 and about 2.0, between about 2.0 and about 2.5, or between about 2.5 and about 3.0. In some embodiments, the reference value may be about 1.0, about 1.14, about 1.2, about 1.5, about 2.0, about 2.5, or about 3.0. In some embodiments, determining the regions of the interconnect layer may include comparing the metal density of different portions of the metal structure 330 with a plurality of reference values v1, v2, … vn-1, vn, where 0 < v1 < v2 < … < vn-1 < vn, forming rules [0, v1], [v1, v2], … [vn-1, vn]. Portions of the metal structure 330 having the same rule of metal density may be determined to belong to the same region.

[0064] Determining the regions of the interconnect layer may further include determining the dielectric material of the regions configured to form the interconnect layer in a subsequent process according to the metal density of the regions. For example, as Figure 4 shown, since the metal density of region R11 is greater than the metal density of region R12, the first dielectric material configured to form region R11 may be different from the second dielectric material configured to form region R12. For example, when the polishing rates of both the first dielectric material and the second dielectric material are higher than the polishing rate of the metal structure 330, then the first dielectric material with a polishing rate higher than that of the second dielectric material is selected. On the other hand, when the polishing rates of both the first dielectric material and the second dielectric material are lower than the polishing rate of the metal structure 330, then the first dielectric material with a polishing rate lower than that of the second dielectric material is selected. By depending on the polishing rates of the dielectric materials of regions R11 and R12 and the different metal densities of regions R11 and R12, the overall polishing rates of regions R11 and R12 can be substantially equivalent to reduce (or prevent) the occurrence of recesses.

[0065] Please refer to Figure 2 , method 200 proceeds to step 215 to form the interconnect layer. Step 215 is described in detail in Figure 5 which Figure 5 is a flowchart of a manufacturing method configured to form an interconnect layer according to some embodiments. For illustration, reference will be made toFigures 6-12 The exemplary manufacturing process shown is used to illustrate this. Figure 5 The steps shown, Figures 6-12 This is a cross-sectional view of an intermediate structure during the fabrication of an interconnect layer according to some embodiments.

[0066] Figures 6-12 Component symbols in Figure 1A The component symbols in the document have the same annotations. The steps of method 500 may be performed in a different order or not at all, depending on the specific application. Therefore, it should be understood that additional processes may be provided before, during, and after method 500, and only a few other processes may be briefly described in this disclosure.

[0067] Please see Figure 5 In step 505, a first dielectric layer is formed over the substrate. For example, such as... Figure 6 As shown, a dielectric layer 110 is formed over a substrate 102. In some embodiments, forming the dielectric layer 110 may include overlay deposition of a dielectric material on the substrate 102, including by PVD, CVD, plasma-enhanced CVD (PECVD), ALD, sputtering, or electron-beam (e-beam) deposition. In some embodiments, the dielectric layer 110 may be formed in regions R11 and R12 already determined in step 210. In some embodiments, the dielectric material may include a second dielectric material selected to form region R12, as described in step 210. In some embodiments, forming the dielectric layer 110 may include doping the dielectric layer 110 with carbon. In some embodiments, forming the dielectric layer 110 may include increasing or decreasing the carbon concentration in the dielectric layer 110. In some embodiments, forming the dielectric layer 110 may include treating the dielectric layer 110 to increase or decrease the dielectric constant of the dielectric layer 110. In some embodiments, forming the dielectric layer 110 may include treating the dielectric layer 110 to increase or decrease its hardness. For example, the dielectric layer 110 may be adjusted for carbon concentration, dielectric constant, and / or hardness by heat treatment, ultraviolet (UV) treatment, plasma treatment, electron beam treatment, or a combination thereof. In some embodiments, forming the dielectric layer 110 may include introducing a pore-forming agent into the dielectric layer 110 by using a pore-forming agent precursor in the dielectric layer 110 to form pores in the dielectric layer 110. The pore-forming agent precursor may include propane (C3H8), benzene (C6H6), and / or α-terpinene (ATRP) (C 10 H 16). In some embodiments, forming the dielectric layer 110 can also include processing the porogen in the dielectric layer 110 to increase or decrease the porosity of the dielectric layer 110. For example, the porogen in the dielectric layer 110 can be adjusted by a thermal treatment, a UV process, a plasma process, an e-beam process, or a combination thereof, to adjust the porosity density or size in the dielectric layer 110.

[0068] Referring to Figure 5 In step 510, a portion of the first dielectric layer in the first region is removed, where the first region is determined in step 210 based on the metal density of the metal structure to be formed in the interconnect layer. For example, as shown in Figure 7 , a portion of the dielectric layer 110 is removed to form an opening 720 in the region Rl l. Removing the portion of the dielectric layer 110 can include a lithography process including (i) spin-coating a photoresist on the dielectric layer 110, (ii) patterning the photoresist to expose the portion of the dielectric layer 110 in the region Rl l, and (iii) etching the exposed portion of the dielectric layer 110 to form the opening 720. In some embodiments, after the portion of the dielectric layer 110 is removed, a side surface of the dielectric layer 110 is exposed. In some embodiments, after the portion of the dielectric layer 110 is removed, a portion of the substrate 102 can be exposed in the opening 720.

[0069] Referring to Figure 5 In step 515, a second dielectric layer is formed in the first region. For example, as shown in Figure 8 , a sub-layer 112 can be formed on the bottom and side surfaces of the opening 720, and as shown in Figure 9 , a sub-layer 114 can be formed on the sub-layer 112 to fill the opening 720 to form a dielectric layer 111. In some embodiments, the dielectric material configured to form the dielectric layer 111 can be determined based on the metal density of the region Rl l determined in step 210. In some embodiments, the description of forming the dielectric layer 110 in step 505 applies to the formation of the sub-layers 112 and 114, unless otherwise specified.

[0070] In some embodiments, the dielectric material configured to form sub-layers 112 and 114 can be different from the dielectric material configured to form dielectric layer 110, such that the polishing rate of dielectric layer 111 is different from the polishing rate of dielectric layer 110. In some embodiments, the dielectric material configured to form sub-layers 112 and 114 can be the same as the dielectric material configured to form dielectric layer 110, but sub-layers 112 and 114 can be treated differently from dielectric layer 110, such that the polishing rate of polishing dielectric layer 111 can be different from the polishing rate of dielectric layer 110. In some embodiments, sub-layers 112 and 114 can be doped with different carbon concentrations than dielectric layer 110. In some embodiments, sub-layers 112 and 114 can include different porogen precursors than dielectric layer 110.

[0071] In some embodiments, sub-layers 112 and 114 can be treated by different processes. In some embodiments, sub-layers 112 and 114 can be treated by different temperature profiles of thermal treatment than dielectric layer 110. In some embodiments, sub-layers 112 and 114 can be treated in a UV process by different UV intensity or duration than dielectric layer 110. In some embodiments, sub-layers 112 and 114 can be treated in a plasma process by different plasma power, pressure, and / or duration than dielectric layer 110. In some embodiments, sub-layers 112 and 114 can be treated in an e-beam process by different e-beam power and / or duration than dielectric layer 110.

[0072] In some embodiments, forming dielectric layer 111 can also include controlling parameters to control the dimensions of sub-layers 112 and 114 when depositing sub-layers 112 and 114. For example, by controlling temperature, pressure, deposition time, and / or combinations, to adjust the thickness T12 of the bottom portion of sub-layer 112 and / or the thickness T11 of the vertical portion of sub-layer 112, as shown in Figure 8 .

[0073] Referring to Figure 5 , in step 520, a first opening and a second opening are formed in the first region and the second region, respectively. For example, as shown in Figure 10As shown, the first openings 1015 can be formed in the region Rl l, and the second openings 1017 can be formed in the region R12. Forming the openings 1015 and 1017 can include a lithography process, which can include (i) spin-coating a photoresist on the dielectric layers 110, 112, and 114, (ii) patterning the photoresist by a mask to expose portions of the dielectric layers 110, 112, and 114, and (iii) etching the exposed portions of the dielectric layers 110, 112, and 114. In some embodiments, multiple lithography processes can be performed, each using a different patterned mask, to obtain openings of different depths according to the needs of forming metal lines / vias in the interconnect structure.

[0074] Referring to Figure 5 In step 525, a metal layer is formed on the first dielectric layer and the second dielectric layer. For example, as shown in Figure 11 , the metal layer 1119 is formed on the dielectric layers 110 and 111 to fill the openings 1015 and 1017. In some embodiments, forming the metal layer 1119 can include (i) forming a seed layer by deposition, including forming a layer of conductive material on the exposed surfaces of the dielectric layers 110 and 111 by a CVD process, a PVD process, or an ALD process, and (ii) electroplating a metal material with the seed layer as an electrode to form the metal layer 1119. In some embodiments, electroplating the metal material can include electroplating Cu and / or other metal materials with low resistivity.

[0075] Referring to Figure 5 In step 530, portions of the metal layer outside the first openings and the second openings can be removed by a planarization process. For example, as shown in Figure 12 , a CMP process can be performed to (i) remove portions of the metal layer 1119 above the dielectric layers 110 and 111 to form the interconnect structures 116 and 118, and (ii) the top surfaces of the dielectric layers 110 and 111 and the interconnect structures 116 and 118. In some embodiments, an abrasive can be added in the CMP process. In some embodiments, parameters of the CMP process can be controlled such that the polishing rates of the regions Rl l and R12 can be comparable. The parameters can include the type of abrasive, the condition of the polishing pad, the speed of the relative motion between the substrate and the polishing pad, the pressure applied by the polishing pad on the substrate, or a combination thereof.

[0076] Although the method 500 includes a process of forming only one layer of interconnect layers, in some embodiments, after step 530, the process can continue to form a second interconnect layer (e.g., the interconnect layer M2 as shown in Figure 1A , for example, as shown in Figure 1AAs shown, the process can continue with method 200 to analyze interconnect layer M2 and determine different regions R21, R22, and R23 according to the metal density of interconnect layer M2, and further continue with method 500 to form interconnect layer M2 in a similar manner as interconnect layer Ml. In some embodiments, after step 530, other structures can be formed on interconnect layer Ml, such as one or more layers of semiconductor devices.

[0077] Embodiments described in the present disclosure relate to an interconnect layer structure and a method of forming the same. In some embodiments, an interconnect layer can include a first region and a second region. In some embodiments, the first region can include a first dielectric layer and a first interconnect structure, and the second region can include a second dielectric layer and a second interconnect structure. In some embodiments, the first region can have a first ratio of metal surface area to non-metal surface area, and the second region can have a second ratio of metal surface area to non-metal surface area. In some embodiments, the first ratio and the second ratio can be different. In some embodiments, according to the first ratio and the second ratio, the first dielectric layer and the second dielectric layer can be selected to be different dielectric materials and / or processed differently to make the polishing rate of the first region and the second region comparable in a planarization process.

[0078] In some embodiments, an interconnect layer structure includes a first dielectric region and a second dielectric region on a substrate. The first dielectric region includes a first dielectric material and a first metal structure. The second dielectric region includes a second dielectric material and a second metal structure. The second dielectric material is different from the first dielectric material. A top surface of the first dielectric region is coplanar with a top surface of the second dielectric region. The first metal structure has a first density, and the second metal structure has a second density different from the first density. In some embodiments, the first density is less than the second density, and a first porosity of the first dielectric material is less than a second porosity of the second dielectric material. In some embodiments, the first density is less than the second density, and a first carbon concentration of the first dielectric material is less than a second carbon concentration of the second dielectric material. In some embodiments, the first density is less than the second density, and a first dielectric constant of the first dielectric material is greater than a second dielectric constant of the second dielectric material. In some embodiments, the first density is less than the second density, and a first breakdown voltage of the first dielectric material is greater than a second breakdown voltage of the second dielectric material. In some embodiments, a top surface of the first metal structure is coplanar with a top surface of the second metal structure. In some embodiments, the first metal structure and the second metal structure include copper.

[0079] In some embodiments, an interconnect layer structure includes a substrate and an interconnect layer on the substrate. The interconnect layer includes a first region and a second region. The first region includes a first metal structure and a first dielectric material. The second region includes a second metal structure and a second dielectric material. A first ratio of a first metal surface area to a first non-metal surface area in the first region is less than a reference value. A second ratio of a second metal surface area to a second non-metal surface area in the second region is greater than the reference value.

[0080] In some embodiments, an interconnect layer structure includes a substrate and an interconnect layer on the substrate. The interconnect layer includes a first region and a second region. The first region includes a first metal structure embedded in a first dielectric layer, and the first dielectric layer includes a first dielectric material. The second region includes a second metal structure embedded in a second dielectric layer, the second dielectric layer includes a second dielectric material different from the first dielectric material, and a thickness of the first dielectric layer is different from a thickness of the second dielectric layer. A first ratio of a first metal surface area to a first non-metal surface area in the first region is less than a reference value. A second ratio of a second metal surface area to a second non-metal surface area in the second region is greater than the reference value. In some embodiments, the reference value is between about 1.0 and about 1.4. In some embodiments, a top surface of the first region is coplanar with a top surface of the second region. In some embodiments, the second region further includes a third dielectric material on a bottom surface and side surfaces of the second region, and the third dielectric material is different from the second dielectric material. In some embodiments, the second region further includes a third dielectric layer on the second dielectric layer, and the third dielectric layer is embedded in an upper portion of the second metal structure. In some embodiments, the interconnect layer structure further includes another interconnect layer on the interconnect layer, and the another interconnect layer includes a third region and a fourth region. The third region includes a third metal structure and the first dielectric material. The fourth region includes a fourth metal structure and the second dielectric material. A third ratio of a third metal surface area to a third non-metal surface area in the third region is substantially equal to the first ratio. A fourth ratio of a fourth metal surface area to a fourth non-metal surface area in the fourth region is substantially equal to the second ratio. In some embodiments, the third region overlaps with the first region and the second region.

[0081] In some embodiments, a method of forming an interconnect layer structure includes forming a first dielectric region including a first dielectric material on a substrate. A second dielectric region including a second dielectric material is formed on the substrate, and the second dielectric material is different from the first dielectric material. Also, a first metal structure and a second metal structure are formed in the first dielectric region and the second dielectric region, respectively. A first density of the first metal structure is different from a second density of the second metal structure, and a top surface of the first metal structure is coplanar with a top surface of the second metal structure. In some embodiments, forming the second dielectric region includes removing a portion of the first dielectric material to form an opening, and depositing the second dielectric material in the opening. In some embodiments, forming the second dielectric region includes increasing a porosity of the second dielectric region. In some embodiments, forming the second dielectric region includes decreasing a dielectric constant of the second dielectric region. In some embodiments, forming the second dielectric region includes removing a portion of the first dielectric material to expose a side surface of the first dielectric region; forming a layer of a third dielectric material on the substrate and the side surface of the first dielectric region; and depositing the second dielectric material on the layer of the third dielectric material. In some embodiments, forming the first metal structure and the second metal structure includes: forming a plurality of openings in the first dielectric region and the second dielectric region; forming a metal layer in the openings; and planarizing the metal layer, the first dielectric region, and the second dielectric region.

[0082] In some embodiments, an interconnect layer structure includes a substrate, a first region on the substrate, and a second region on the substrate and adjacent to the first region, wherein a top surface of the first region is coplanar with a top surface of the second region. The first region includes a first portion of a first dielectric layer in the first region and a first metal structure embedded in the first portion of the first dielectric layer. The second region includes a second portion of the first dielectric layer in the second region, a second dielectric layer on the second portion of the first dielectric layer, and a second metal structure embedded in the second portion of the first dielectric layer and the second dielectric layer. In some embodiments, the first portion of the first dielectric layer has a first thickness, the second portion of the first dielectric layer has a second thickness, and the second thickness is less than the first thickness. In some embodiments, the second dielectric layer includes at least one first sub-layer and at least one second sub-layer spaced apart from the at least one first sub-layer, wherein bottom surfaces of the at least one first sub-layer and the at least one second sub-layer are in contact with a top surface of the second portion of the first dielectric layer in the second region.

[0083] It is to be understood that the contents of the detailed description, rather than the abstract, primarily are configured to explain the claimed subject matter. The abstract portion of the disclosure can set forth one or more, but not all possible embodiments of the disclosure as envisioned by the inventor(s) and, as such, is not intended to limit the scope of the appended claims in any way.

[0084] The foregoing disclosure summarizes features of several embodiments so that those of ordinary skill in the art can better understand the various embodiments of the present disclosure. Those of ordinary skill in the art will understand that the present disclosure can serve as a basis for designing or modifying other processes and structures to achieve the same purposes and / or to achieve the same benefits with other embodiments of the present disclosure. Those of ordinary skill in the art will also understand that such equivalent constructions / etc. do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An interconnect layer structure, characterized by comprising: a first dielectric region and a second dielectric region on a substrate, wherein: a top surface of the first dielectric region is coplanar with a top surface of the second dielectric region; a first metal structure is in the first dielectric region and has a first density; and a second metal structure is in the second dielectric region and has a second density different from the first density.

2. The interconnect layer structure of claim 1, wherein: the first density is less than the second density; and a first porosity of the first dielectric region is less than a second porosity of the second dielectric region.

3. The interconnect layer structure of claim 1, wherein, wherein: the first density is less than the second density; and a first breakdown voltage of the first dielectric region is greater than a second breakdown voltage of the second dielectric region.

4. The interconnect layer structure of claim 1, wherein, a top surface of the first metal structure is coplanar with a top surface of the second metal structure.

5. An interconnect layer structure, characterized by comprising: a substrate; and an interconnect layer on the substrate and comprising a first region and a second region, wherein: the first region comprises a first metal structure embedded in a first dielectric layer; the second region comprises a second metal structure embedded in a second dielectric layer, wherein a thickness of the first dielectric layer is different from a thickness of the second dielectric layer; a first ratio of a first metal surface area to a first non-metal surface area in the first region is less than a reference value; and a second ratio of a second metal surface area to a second non-metal surface area in the second region is greater than the reference value.

6. The interconnect layer structure of claim 5, wherein, the second region further comprises: a third dielectric layer on the second dielectric layer and embedding an upper portion of the second metal structure.

7. The interconnect layer structure of claim 5, wherein, further comprising: a further interconnect layer on the interconnect layer and comprising a third region and a fourth region, wherein: the third region comprises a third metal structure and a third dielectric layer; the fourth region comprises a fourth metal structure and a fourth dielectric layer; a third ratio of a third metal surface area to a third non-metal surface area in the third region is equal to the first ratio; and a fourth ratio of a fourth metal surface area to a fourth non-metal surface area in the fourth region is equal to the second ratio.

8. An interconnect layer structure, characterized by comprising: a substrate; a first region on the substrate and comprising: a first portion of a first dielectric layer in the first region; and a first metal structure embedded in the first portion of the first dielectric layer; and a second region on the substrate and adjacent to the first region, wherein a top surface of the first region is coplanar with a top surface of the second region, and comprising: a second portion of the first dielectric layer in the second region; a second dielectric layer on the second portion of the first dielectric layer; and a second metal structure embedded in the second portion of the first dielectric layer and the second dielectric layer.

9. The interconnect layer structure of claim 8, wherein, the first portion of the first dielectric layer has a first thickness, the second portion of the first dielectric layer has a second thickness, and the second thickness is less than the first thickness.

10. The interconnect layer structure of claim 8, wherein, The second dielectric layer includes at least one first sub-layer and at least one second sub-layer disposed apart from the at least one first sub-layer, wherein bottom surfaces of the at least one first sub-layer and the at least one second sub-layer are in contact with a top surface of the second portion of the first dielectric layer located in the second region.

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