Solid state disk test system

Abstract

The utility model discloses a solid state disk testing system which is used for testing a solid state disk and comprises a HOST, a back plate and a bridging plate. The bridging board is electrically connected with the HOST and the backboards at the same time, a first-stage first expansion chip and a plurality of second-stage first expansion chips connected with the first-stage first expansion chip are integrated on the bridging board, and the second-stage first expansion chips are electrically connected with the backboards in a one-to-one correspondence mode. The first-stage first expansion chip is used for analyzing the master control signal, expanding a test signal in the master control signal into a plurality of first-stage test signals and respectively issuing the first-stage test signals to the plurality of second-stage first expansion chips; and the second-stage first expansion chip is used for expanding the first-stage test signal into a plurality of second-stage test signals and respectively issuing the second-stage test signals to the plurality of backboards, and the backboards transmit the second-stage test signals to the plurality of test interfaces. According to the utility model, the host can directly control and test a plurality of solid state disks, and the cost is low.

Description

Technical Field

[0001] This utility model relates to the field of hard disk testing technology, and in particular to a solid-state hard disk testing system. Background Technology

[0002] Solid-state drives (SSDs) are hard drives made using arrays of solid-state electronic storage chips. An SSD consists of a control unit and storage units (FLASH chips and DRAM chips). Currently, SSDs are widely used in many fields, including military, automotive, industrial control, video surveillance, network monitoring, network terminals, power, medical, aerospace, and navigation equipment. To ensure the proper functioning of SSDs during use, testing them is particularly important.

[0003] However, current typical SSD testing system architecture consists of a host, a switch, a cell unit, a backplane, and SSDs. The cell unit is centered around a CPU motherboard, paired with a backplane primarily controlled by a microcontroller. The two communicate via serial ports, and a single cell unit can support 4 to 16 SSDs for testing. To improve testing efficiency, multiple cell units are typically configured to communicate with their corresponding backplanes, and each cell unit needs to communicate with the host. This necessitates adding a switch between the two to facilitate communication between multiple cell units and the host, increasing costs. Utility Model Content

[0004] To address the shortcomings of existing technologies, this invention provides a solid-state drive (SSD) testing system that allows the host computer to directly control and test multiple SSDs at a lower cost.

[0005] This utility model is achieved through the following technical solution:

[0006] A solid-state drive (SSD) testing system for testing SSDs, comprising:

[0007] HOST is used to send the main control signal corresponding to the function under test;

[0008] Multiple backplanes, each backplane integrating multiple test interfaces for connecting multiple solid-state drives;

[0009] The bridge board is electrically connected to the HOST and multiple backplanes. The bridge board integrates a primary first expansion chip and multiple secondary first expansion chips connected to the primary first expansion chip. Each secondary first expansion chip is electrically connected to one of the multiple backplanes. The primary first expansion chip parses the total control signal and expands the test signals within the total control signal into multiple primary test signals, which are then sent to the multiple secondary first expansion chips. The secondary first expansion chips expand the primary test signals into multiple secondary test signals and send them to the multiple backplanes. The backplanes then transmit the secondary test signals to the multiple test interfaces.

[0010] Furthermore, the bridge board also integrates a primary second expansion chip and multiple secondary second expansion chips electrically connected to the primary second expansion chip. The multiple secondary second expansion chips are electrically connected to multiple backplanes one by one. The primary second expansion chip is used to parse the total control signal and expand the control signal in the total control signal into multiple primary control signals, which are then sent to the multiple secondary second expansion chips respectively. The secondary second expansion chips are used to expand the primary control signal into multiple secondary control signals and send them to the multiple backplanes respectively.

[0011] Furthermore, the bridge board also integrates a first IO expansion chip, which is electrically connected to the first-level first expansion chip, the second-level first expansion chip, the first-level second expansion chip, and the second-level second expansion chip. It is used to parse the total control signal and expand the reset signal in the total control signal into multiple first-level reset signals, which are then sent to the first-level first expansion chip, the second-level first expansion chip, the first-level second expansion chip, and the second-level second expansion chip, respectively.

[0012] Furthermore, the bridge board also integrates a first I 2 C isolator, the HOST, the first I 2 The C-isolator is sequentially connected to the first-stage expansion chip, and the first I... 2 C-type isolators are used to improve the stability of signal transmission.

[0013] Furthermore, the backplane integrates a connector, a third-level first expansion chip electrically connected to the connector, and multiple test interfaces electrically connected to the third-level first expansion chip. The connector is also electrically connected to the second-level first expansion chip and the second-level second expansion chip. The third-level first expansion chip is used to receive the second-level test signal and expand it into multiple third-level test signals to be sent to the multiple test interfaces respectively.

[0014] Furthermore, the backplane integrates a second IO expansion chip, which is electrically connected to the connector and multiple test interfaces. The second IO expansion chip is used to parse the secondary control signal and expand it into multiple P3 power-off control signals, which are then sent to the multiple test interfaces respectively.

[0015] Furthermore, the backplane integrates a third I / O expansion chip, which is electrically connected to the connector and multiple test interfaces. The third I / O expansion chip is used to parse the secondary control signal and expand it into multiple plug-in detection signals, which are then sent to the multiple test interfaces respectively.

[0016] Furthermore, the backplane also integrates multiple LEDs that correspond one-to-one with the multiple test interfaces. The backplane also integrates a fourth IO expansion chip, which is electrically connected to the connector and the multiple LEDs. It is used to parse the secondary control signal and expand it into multiple LED signals, which are then sent to the multiple LEDs respectively.

[0017] Furthermore, the backplate also integrates two second I's that are electrically connected to the connector. 2 C isolator, one of the second I 2 The C-isolator is electrically connected to the third-level first expansion chip, and the other second I... 2 The C-isolator is simultaneously connected to the second, third, and fourth IO expansion chips.

[0018] Furthermore, the test interface includes at least one of a U.2 interface, an M.2 interface, and a SATA interface.

[0019] Compared with existing technologies, the advantages of this utility model are:

[0020] 1. This utility model, through a test architecture of HOST-bridge board-backplane-solid-state drive, realizes the expansion of the total control signal of HOST through the bridge board, and allows HOST to directly control the solid-state drive on the backplane for testing. This eliminates the need for switches and multiple CELL systems in general test systems, greatly reducing product costs.

[0021] 2. What components are used, and what effect is achieved? Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall architecture of a solid-state drive testing system according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of a bridge plate according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of the back plate according to an embodiment of the present utility model;

[0025] Figure 4 This is a schematic diagram of the specific structure of the back plate according to an embodiment of the present utility model;

[0026] Figure 5 This is a schematic diagram of the specific structure of the back plate according to another embodiment of the present invention.

[0027] Labeling Explanation: 1. HOST; 2. Bridge Board; 211. First Expansion Chip of Level 1; 212. First Expansion Chip of Level 2; 213. First Expansion Chip of Level 3; 221. Second Expansion Chip of Level 1; 222. Second Expansion Chip of Level 2; 231. First I / O Expansion Chip; 232. Second I / O Expansion Chip; 233. Third I / O Expansion Chip; 234. Fourth I / O Expansion Chip; 3. Backplane; 31. Connector; 4. Solid State Drive; 51. First I / O... 2 C isolator; 52, Second I 2 C-isolator. Detailed Implementation

[0028] The following detailed, non-limiting description of the utility model's technical solution, in conjunction with preferred embodiments and accompanying drawings, is provided. In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0029] like Figure 1As shown, an embodiment of this utility model discloses a solid-state drive (SSD) testing system for testing SSDs 4. The system includes a host (HOST1), multiple backplanes 3, and a bridge board 2 electrically connected to both the host (HOST1) and the backplanes 3. The host (HOST1) sends a master control signal corresponding to the function under test. The bridge board 2 parses the master control signal and expands the test signals within it into multiple secondary test signals, which are then sent to the multiple backplanes 3. Each backplane 3 integrates multiple test interfaces 30 for connecting multiple SSDs 4. This utility model, through its host (HOST1)-bridge board 2-backplane 3-SSD 4 testing architecture, enables the bridge board 2 to expand the master control signal of the host (HOST1), allowing the host (HOST1) to directly control the SSDs 4 on the backplanes 3 for testing, significantly reducing product costs.

[0030] Specifically, the function of HOST1 is to send the master control signal corresponding to the function under test. HOST1 can be a PC host or other devices, including but not limited to these, and those skilled in the art can choose according to the actual situation. HOST1 can send the master control signal by receiving test operation instructions issued by the user. In this embodiment, HOST1 is connected to the bridge board 2 via a serial port connection to the SMbus bus, that is, the master control signal in this embodiment is an SMbus signal.

[0031] Further reference Figure 2 The bridge board 2 integrates a primary first expansion chip 211 and multiple secondary first expansion chips 212 connected to the primary first expansion chip 211. The secondary first expansion chips 212 are electrically connected to multiple backplanes 3 one-to-one. The primary first expansion chip 211 parses the overall control signal and expands the test signal within it into multiple primary test signals, which are then sent to the multiple secondary first expansion chips 212. The secondary first expansion chips 212 expand the primary test signals into multiple secondary test signals and send them to the multiple backplanes 3, which then transmit the secondary test signals to multiple test interfaces 30. In this embodiment, the test signal, primary test signal, secondary test signal, and the tertiary test signal (described below) are all SMbus1 signals. This invention, by setting two levels of expansion chips on the bridge board 2, allows the test signal of HOST1 to be expanded into multiple paths, thereby connecting to multiple backplanes 3 and improving testing efficiency.

[0032] Specifically, in this embodiment, the bridge board 2 is provided with one primary first expansion chip 211 and eight secondary first expansion chips 212. The primary first expansion chip 211 expands the test signal into eight primary test signals and transmits them to the corresponding secondary first expansion chips 212. Each secondary first expansion chip 212 expands the received primary test signal into eight secondary test signals and sends them down to the corresponding backplane 3. That is, HOST1 can connect to a total of 64 backplanes 3 through the bridge board 2, which greatly improves the testing efficiency and reduces the testing cost.

[0033] Furthermore, the bridge board 2 also integrates a primary second expansion chip 221 and multiple secondary second expansion chips 222 electrically connected to the primary second expansion chip 221. The multiple secondary second expansion chips 222 are electrically connected to multiple backplanes 3 one-to-one. The primary second expansion chip 221 is used to parse the total control signal and expand the control signals in the total control signal into multiple primary control signals, which are then sent to the multiple secondary second expansion chips 222. The secondary second expansion chips 222 are used to expand the primary control signals into multiple secondary control signals and send them to the multiple backplanes 3. In this embodiment, the control signal, primary control signal, secondary control signal, and the tertiary control signal (described below) are all SMbus2 signals. In this embodiment, the number of primary second expansion chips 221 and secondary second expansion chips 222 corresponds to the number of primary first expansion chips 211 and secondary first expansion chips 212, respectively, so that each backplane 3 can receive the control signal from HOST1 and complete some extended functions other than testing.

[0034] Optionally, the bridge board 2 also integrates a first I / O expansion chip 231. The first I / O expansion chip 231 is electrically connected to a first-level first expansion chip 211, a second-level first expansion chip 212, a first-level second expansion chip 221, and a second-level second expansion chip 222. It is used to parse the overall control signal and expand the reset signal in the overall control signal into multiple first-level reset signals, which are then sent to the first-level first expansion chip 211, the second-level first expansion chip 212, the first-level second expansion chip 221, and the second-level second expansion chip 222 respectively. By setting the first I / O expansion chip 231, this invention can realize the reset of the first-level first expansion chip 211, the second-level first expansion chip 212, the first-level second expansion chip 221, and the second-level second expansion chip 222.

[0035] In addition, two first I's are also integrated on the bridge board 2. 2 C-isolation unit 51 is used to improve the stability of signal transmission. One of the first I... 2 The connection method for isolator C51 is HOST1, first I 2 C-isolator 51 is sequentially connected to the first-level expansion chip 211, and another first I...2 The connection method for isolator C51 is HOST1, first I 2 Isolator 51 is connected in sequence to the first-level second expansion chip 221. This utility model, by setting I... 2 C-type isolators, through electrical isolation, can effectively reduce electrical interference between different circuits, reduce noise and electromagnetic compatibility (EMC) issues, and improve the stability of signal transmission.

[0036] Key reference Figure 3 The backplane 3 integrates a connector 31, a third-level first expansion chip 213 electrically connected to the connector 31, and multiple test interfaces 30 electrically connected to the third-level first expansion chip 213. The connector 31 is also electrically connected to a second-level first expansion chip 212 and a second-level second expansion chip 222. The third-level first expansion chip 213 receives second-level test signals and expands them into multiple third-level test signals to be sent to the multiple test interfaces 30 respectively. By setting the third-level first expansion chip 213 on the backplane 3, this utility model enables multiple solid-state drives 4 to be connected to a single backplane 3 simultaneously, further improving testing efficiency.

[0037] In addition, the backplane 3 also integrates multiple LEDs corresponding to multiple test interfaces 30, a second IO expansion chip 232, a third IO expansion chip 233, and a fourth IO expansion chip 234.

[0038] The second IO expansion chip 232 is electrically connected to both connector 31 and multiple test interfaces 30. It parses the secondary control signals and expands them into multiple P3 power-off control signals, which are then sent to the multiple test interfaces 30. The third IO expansion chip 233 is also electrically connected to both connector 31 and multiple test interfaces 30. It parses the secondary control signals and expands them into multiple disk insertion detection signals, which are then sent to the multiple test interfaces 30. The fourth IO expansion chip 234 is electrically connected to both connector 31 and multiple LEDs. It parses the secondary control signals and expands them into multiple LED signals, which are then sent to the multiple LEDs. Furthermore, each test interface 30 is connected to a MOS switch 32 to complete power-off control. Since the P3 power-off control signals, disk insertion detection signals, and LED signals are all IO signals, the entire test system can not only test the solid-state drive 4 but also perform functions such as LED signal monitoring, disk insertion detection, and LED change monitoring, further improving the versatility of the test system and making it more user-friendly.

[0039] In addition, the backplate 3 also integrates two second I-type connectors that are electrically connected to the connector 31. 2 C isolator 52, one of the second I 2 C-isolator 52 is electrically connected to the third-level first expansion chip 213, and another second I... 2Isolator 52 is simultaneously connected to the second IO expansion chip 232, the third IO expansion chip 233, and the fourth IO expansion chip 234, thereby improving the stability of signal transmission.

[0040] refer to Figure 4 This is one embodiment of the backplate 3 in this utility model, where the test interface 30 is a U.2 interface. The backplate 3 has a total of eight U.2 interfaces, maximizing the expansion of interfaces and the number of connectable solid-state drives 4, thus effectively improving testing efficiency.

[0041] refer to Figure 5 In another embodiment of the backplate 3 of this utility model, the test interface 30 is an M.2 interface or a SATA interface. The backplate 3 has two sets of M.2 or SATA interfaces, each set containing eight interfaces, and correspondingly, two sets of LEDs, a second IO expansion chip 232, a third IO expansion chip 233, and a fourth IO expansion chip 234 are also provided. In use, the user can choose to use either of the two backplates 3, thereby enabling testing of different types of solid-state drives and improving system compatibility.

[0042] This invention utilizes a test architecture consisting of HOST1, bridge board 2, backplane 3, and solid-state drive 4. This architecture expands the overall control signal of HOST1 via bridge board 2, allowing HOST1 to directly control the solid-state drive 4 on backplane 3 for testing, significantly reducing product costs. Furthermore, bridge board 2 has two levels of expansion, and backplane 3 has one level of expansion, for a total of three levels. This enables a single HOST1 to control and test multiple solid-state drives, improving testing efficiency and reducing costs. Moreover, it eliminates the need for the original microcontroller on backplane 3, the switch between HOST1 and the backplane, and multiple cell boards, further reducing costs to approximately one-tenth of the original amount.

[0043] The above embodiments only illustrate several implementation methods of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A solid state drive testing system for testing a solid state drive (4), characterized by, include: HOST(1) is used to send the total control signal corresponding to the function under test; Multiple backplanes (3), the backplanes (3) are integrated with multiple test interfaces (30) for connecting multiple solid-state drives (4); The bridge board (2) is electrically connected to the HOST (1) and multiple backplanes (3). The bridge board (2) integrates a first-level first expansion chip (211) and multiple second-level first expansion chips (212) connected to the first-level first expansion chip (211). The second-level first expansion chips (212) are electrically connected to multiple backplanes (3) one by one. The first-level first expansion chip (211) is used to parse the total control signal and expand the test signal in the total control signal into multiple first-level test signals and send them to multiple second-level first expansion chips (212) respectively. The second-level first expansion chips (212) are used to expand the first-level test signals into multiple second-level test signals and send them to multiple backplanes (3) respectively. The backplanes (3) then transmit the second-level test signals to multiple test interfaces (30).

2. The solid state drive testing system of claim 1, wherein, The bridge board (2) also integrates a first-level second expansion chip (221) and a plurality of second-level second expansion chips (222) electrically connected to the first-level second expansion chip (221). The plurality of second-level second expansion chips (222) are electrically connected to the plurality of backplanes (3) one by one. The first-level second expansion chip (221) is used to parse the total control signal and expand the control signal in the total control signal into a plurality of first-level control signals and send them to the plurality of second-level second expansion chips (222) respectively. The second-level second expansion chip (222) is used to expand the first-level control signal into a plurality of second-level control signals and send them to the plurality of backplanes (3) respectively.

3. The solid state drive testing system of claim 2, wherein, The bridge board (2) also integrates a first IO expansion chip (231), which is electrically connected to the first-level first expansion chip (211), the second-level first expansion chip (212), the first-level second expansion chip (221), and the second-level second expansion chip (222). It is used to parse the total control signal and expand the reset signal in the total control signal into multiple first-level reset signals and send them to the first-level first expansion chip (211), the second-level first expansion chip (212), the first-level second expansion chip (221), and the second-level second expansion chip (222), respectively.

4. The solid state drive testing system of claim 2, wherein, The bridge plate (2) is also integrated with a first I 2 C isolator (51), the HOST (1), a first I 2 C isolator (51) and a first expansion chip (211) are connected in sequence, and the first I 2 C isolator (51) is used to improve the stability of signal transmission.

5. The solid state drive testing system of claim 3, wherein, The backplane (3) integrates a connector (31), a third-level first expansion chip (213) electrically connected to the connector (31), and a plurality of test interfaces (30) electrically connected to the third-level first expansion chip (213). The connector (31) is also electrically connected to the second-level first expansion chip (212) and the second-level second expansion chip (222). The third-level first expansion chip (213) is used to receive the second-level test signal and expand it into multiple third-level test signals to be sent to the multiple test interfaces (30) respectively.

6. The solid state drive testing system of claim 5, wherein, The backboard (3) is integrated with a second IO expansion chip (232) which is electrically connected with the connector (31) and the test interfaces (30) at the same time, and is used for analyzing the secondary control signals and expanding into multiple P3 power-off control signals which are respectively sent to the test interfaces (30).

7. The solid state drive testing system of claim 6, wherein, The backboard (3) is integrated with a third IO expansion chip (233) which is electrically connected with the connector (31) and the test interfaces (30) at the same time, and is used for analyzing the secondary control signals and expanding into multiple socket detection signals which are respectively sent to the test interfaces (30).

8. The solid state drive testing system of claim 7, wherein, The backboard (3) is further integrated with multiple lamp beads which are one-to-one corresponding to the test interfaces (30), and the backboard (3) is integrated with a fourth IO expansion chip (234) which is electrically connected with the connector (31) and the lamp beads at the same time, and is used for analyzing the secondary control signals and expanding into multiple lamp bead signals which are respectively sent to the lamp beads.

9. The solid state drive testing system of claim 8, wherein, The back plate (3) also integrates two second I-type connectors that are electrically connected to the connector (31). 2 C isolator (52), one of which is the second I 2 The C-isolator (52) is electrically connected to the third-level first expansion chip (213), and another second I... 2 The C isolator (52) is simultaneously connected to the second IO expansion chip (232), the third IO expansion chip (233), and the fourth IO expansion chip (234).

10. The solid state drive testing system of claim 1, wherein, The test interface (30) comprises at least one of a U.2 interface, an M.2 interface and a SATA interface.

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