Antenna control system
By integrating power management, control, and RF switch modules, the automation and integration of the controlled antenna control system are achieved, solving the problems of large system size and high failure rate in existing technologies, and improving the system's portability and communication efficiency.
Patent Information
- Application Number
- CN202423317400.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing controlled antenna control modules have a large system size due to their complex circuit layout and numerous components, which is not conducive to miniaturization and integration, increases the failure rate and maintenance difficulty, and makes it difficult to achieve fast and accurate identification and response to external signals.
The power management module, control module, and RF switch module are integrated into one system. The power management module provides a stable voltage, the control module collects and converts external signals into TTL signals, and the RF switch module switches the controlled antenna according to the TTL signal to achieve automated control.
This achievement enables the overall miniaturization and integration of the antenna control system, improving the system's portability and installation flexibility, simplifying operation procedures, and enhancing communication efficiency and system reliability.
Smart Images
Figure CN223829314U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of controlled antenna control, and more particularly, to an antenna control system. BACKGROUND
[0002] With the vigorous development of commercial aerospace, especially the rapid advancement of low-orbit satellite internet projects, more stringent and diversified requirements are put forward for satellite measurement and control technologies. As a key link in satellite measurement and control systems, the performance and reliability of controlled antenna switching technology are directly related to the stability and efficiency of the entire communication system. As a core component for realizing controlled antenna switching, the design and optimization of the controlled antenna control module have become a hot spot of current research.
[0003] Currently, most controlled antenna control modules adopt traditional circuit design schemes to realize the switching control of controlled antennas through complex circuit layout and component combination. These modules usually include power management, signal acquisition and processing, control logic execution, and radio frequency switches. Among them, the power management module is responsible for providing stable power supply for the entire system; the signal acquisition and processing module is responsible for receiving external signals and converting them into a signal form recognizable by the system; the control logic execution module generates control instructions for switching the radio frequency switch according to the processed signals through a series of logical operations and judgments; and the radio frequency switch realizes the switching between different controlled antennas according to the received instructions.
[0004] However, this traditional circuit design scheme has many shortcomings. First, due to the complex circuit layout and large number of components, the entire system is bulky, which is not conducive to the development needs of miniaturization and integration. At the same time, the complex circuit structure also increases the failure rate and maintenance difficulty of the system, reduces the stability and reliability of the system, and makes it difficult to realize fast and accurate identification and response to external signals. CONTENT OF THE INVENTION
[0005] In view of at least one defect or improvement demand of the prior art, the present application provides an antenna control system to solve the problem that the antenna control system is bulky due to the complex circuit layout and large number of components, which is not conducive to the development needs of miniaturization and integration, and at the same time, increases the failure rate and maintenance difficulty of the system, reduces the stability and reliability of the system, and makes it difficult to realize fast and accurate identification and response to external signals.
[0006] To achieve the above object, according to the first aspect of the utility model, provide a kind of antenna control system, comprising: power management module, control module and radio frequency switch module;Power management module, control module and radio frequency switch module are sequentially connected;Power management module is further connected with radio frequency switch module;
[0007] Wherein, power management module is used to convert the input voltage from outside into multiple power supply voltages for control module and radio frequency switch module power supply;
[0008] Control module is used to collect outside separated signal, and outside separated signal is converted into TTL signal and sent to radio frequency switch module;
[0009] Radio frequency switch module is used to switch working controlled antenna according to TTL signal.
[0010] In some possible implementation ways, power management module further includes: surge protection circuit, voltage stabilizing circuit, first voltage conversion circuit, second voltage conversion circuit and third voltage conversion circuit;Surge protection circuit is connected with voltage stabilizing circuit;Voltage stabilizing circuit is connected with first voltage conversion circuit, second voltage conversion circuit respectively;First voltage conversion circuit is connected with third voltage conversion circuit;
[0011] Wherein, surge protection circuit is used to limit and absorb surge voltage in input voltage from outside, and obtain the input voltage from outside after surge protection processing;
[0012] Voltage stabilizing circuit is used to stabilize voltage and obtain preset initial voltage after surge protection processing of input voltage from outside;
[0013] First voltage conversion circuit is used to convert preset initial voltage into first preset voltage;
[0014] Second voltage conversion circuit is used to convert preset initial voltage into second preset voltage;
[0015] Third voltage conversion circuit is used to convert first preset voltage into third preset voltage.
[0016] In some possible implementation ways, surge protection circuit further includes: chip U1, surge protection chip E1, chip EMI1;Resistance R1, R2, R3, R4, R5, R6, R8, R9, R12;Capacitor C1, C13, C14, C15, C16, C17;Zener diode Q1, Q2;
[0017] The fifth pin, the sixth pin, the seventh pin and the eighth pin of the chip U1 are connected with the positive pole of the external input voltage and one end of the resistors R2 and R5, the other end of the resistor R2 is connected with the fifth pin of the anti-surge chip E1, the other end of the resistor R5 is connected with the eighth pin of the anti-surge chip E1; the third pin of the voltage stabilizing diode Q1 is connected with the fifth pin of the anti-surge chip E1, the first pin of the voltage stabilizing diode Q1 is connected with the sixth pin of the anti-surge chip E1; the third pin of the voltage stabilizing diode Q2 is connected with the sixth pin of the anti-surge chip E1, the first pin of the voltage stabilizing diode Q2 is connected with the negative pole of the external input voltage; one end of the resistor R9 is connected with the eighth pin of the anti-surge chip E1, the other end of the resistor R9 is connected with the seventh pin of the anti-surge chip E1; one end of the resistor R12 is connected with the seventh pin of the anti-surge chip E1, the other end of the resistor R12 is connected with the negative pole of the external input voltage; one end of the resistor R3 is connected with the fourth pin of the chip U1, the other end of the resistor R3 is connected with the fourth pin of the anti-surge chip E1; the resistor R4 is connected in parallel with the resistor R3; the capacitor C1 is connected in parallel with the fourth pin and the fifth pin of the anti-surge chip E1; the first pin, the second pin and the third pin of the chip U1 are connected in parallel with the third pin of the anti-surge chip E1; one end of the resistor R1 is connected with the third pin of the anti-surge chip E1, the other end of the resistor R1 is connected with the second pin of the anti-surge chip E1; one end of the resistor R6 is connected with the second pin of the anti-surge chip E1, the other end of the resistor R6 is connected with the first pin of the anti-surge chip E1; one end of the resistor R8 is connected with the first pin of the anti-surge chip E1, the other end of the resistor R8 is connected with the negative pole of the external input voltage; one end of the capacitor C17 is connected with the negative pole of the external input voltage, the other end of the capacitor C17 is connected with the twelfth pin of the anti-surge chip E1; one end of the capacitor C13 is connected with the second pin of the anti-surge chip E1, the other end of the capacitor C13 is connected with the negative pole of the external input voltage; one end of the capacitor C14 is connected with the second pin of the anti-surge chip E1, the other end of the capacitor C14 is connected with the negative pole of the external input voltage; one end of the capacitor C15 is connected with the second pin of the anti-surge chip E1, the other end of the capacitor C15 is connected with the negative pole of the external input voltage; one end of the capacitor C16 is connected with the second pin of the anti-surge chip E1, the other end of the capacitor C16 is connected with the negative pole of the external input voltage; the first pin of the chip EMI1 is connected with the second pin of the anti-surge chip E1, the second pin of the chip EMI1 is connected with the negative pole of the external input voltage, the third pin and the fourth pin of the chip EMI1 are connected with the voltage stabilizing circuit.
[0018] In some possible implementation manners, the voltage stabilizing circuit further comprises: capacitors C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C18, C19, C20, C21, C22, C23, resistors R7, R10, R11, RH1, RL1, a chip U2, L1;
[0019] The first pin and the third pin of the chip U2 are connected with the third pin and the fourth pin of the chip EMI1, one end of the resistor R11 is connected with the second pin of the chip U2, and the other end of the resistor R11 is connected with the third pin of the chip U2; the resistor R7 is connected between the seventh pin and the eighth pin of the chip U2; the resistor R10 is connected between the fourth pin and the fifth pin of the chip U2; the resistor RH1 is connected between the sixth pin and the eighth pin of the chip U2; the resistor RL1 is connected between the fourth pin and the sixth pin of the chip U2; one end of the capacitor C7 is connected with the eighth pin of the chip U2, the other end of the capacitor C7 is connected with one end of the capacitor C18, and the other end of the capacitor C18 is connected with the fourth pin of the chip U2; one end of the capacitor C8 is connected with the eighth pin of the chip U2, the other end of the capacitor C8 is connected with one end of the capacitor C19, and the other end of the capacitor C19 is connected with the fourth pin of the chip U2; the first pin of the chip L1 is connected with the fourth pin of the chip U2, and the second pin of the chip L1 is connected with the eighth pin of the chip U2; one end of the capacitor C9 is connected with the third pin of the chip L1, the other end of the capacitor C9 is connected with one end of the capacitor C20, and the other end of the capacitor C20 is connected with the fourth pin of the chip L1; one end of the capacitor C10 is connected with the third pin of the chip L1, the other end of the capacitor C10 is connected with one end of the capacitor C21, and the other end of the capacitor C21 is connected with the fourth pin of the chip L1; one end of the capacitor C11 is connected with the third pin of the chip L1, the other end of the capacitor C11 is connected with one end of the capacitor C22, and the other end of the capacitor C22 is connected with the fourth pin of the chip L1; one end of the capacitor C12 is connected with the third pin of the chip L1, the other end of the capacitor C12 is connected with one end of the capacitor C23, and the other end of the capacitor C23 is connected with the fourth pin of the chip L1.
[0020] In some possible implementation manners, the first voltage conversion circuit further comprises: a chip U3, capacitors C24, C25, C29, C30, C31, C32, resistors R13, R14, R16, R17;
[0021] The twelfth pin of the chip U3 is connected with a voltage stabilizing circuit, and the eleventh pin of the chip U3 is connected with the twelfth pin of the chip U3; one end of the capacitor C31 is connected with the twelfth pin of the chip U3, and the other end of the capacitor C31 is connected with the ground; one end of the capacitor C30 is connected with the eighth pin of the chip U3, and the other end of the capacitor C31 is connected with the ground; one end of the resistor R16 is connected with the seventh pin of the chip U3, and the other end of the resistor R16 is connected with the ground; one end of the capacitor C32 is connected with the ninth pin of the chip U3, and the other end of the capacitor C32 is connected with the ground; the capacitor C24 is connected in parallel between the second pin and the third pin of the chip U3; the resistor R13 is connected in parallel between the fourth pin and the fifth pin of the chip U3; one end of the capacitor C29 is connected with the fourth pin of the chip U3, and the other end of the capacitor C29 is connected with the ground; one end of the capacitor C25 is connected with the fifth pin of the chip U3, and the other end of the capacitor C25 is connected with the ground; one end of the resistor R14 is connected with the fifth pin of the chip U3, and the other end of the resistor R14 is connected with the sixth pin of the chip U3; one end of the resistor R17 is connected with the sixth pin of the chip U3, and the other end of the resistor R17 is connected with the ground.
[0022] In some possible implementation manners, the second voltage conversion circuit further comprises: a chip U5, capacitors C34, C35, C36, C37, C38, C39, resistors R19, R20, R21, R22;
[0023] The twelfth pin of the chip U3 is connected with a voltage stabilizing circuit, and the eleventh pin of the chip U3 is connected with the twelfth pin of the chip U3; one end of the capacitor C31 is connected with the twelfth pin of the chip U3, and the other end of the capacitor C31 is connected with the ground; one end of the capacitor C30 is connected with the eighth pin of the chip U3, and the other end of the capacitor C31 is connected with the ground; one end of the resistor R16 is connected with the seventh pin of the chip U3, and the other end of the resistor R16 is connected with the ground; one end of the capacitor C32 is connected with the ninth pin of the chip U3, and the other end of the capacitor C32 is connected with the ground; the capacitor C24 is connected in parallel between the second pin and the third pin of the chip U3; the resistor R13 is connected in parallel between the fourth pin and the fifth pin of the chip U3; one end of the capacitor C29 is connected with the fourth pin of the chip U3, and the other end of the capacitor C29 is connected with the ground; one end of the capacitor C25 is connected with the fifth pin of the chip U3, and the other end of the capacitor C25 is connected with the ground; one end of the resistor R14 is connected with the fifth pin of the chip U3, and the other end of the resistor R14 is connected with the sixth pin of the chip U3; one end of the resistor R17 is connected with the sixth pin of the chip U3, and the other end of the resistor R17 is connected with the ground.
[0024] In some possible implementation manners, the third voltage conversion circuit further comprises: capacitors C26, C27, C28, C33, resistors R15, R18, RX1, RX2, RY1, RY2, a chip U4;
[0025] Specifically, pin 5 of chip U4 is connected to the first voltage conversion circuit; pins 5, 6, 7, 8, and 10 of chip U4 are connected in parallel; pins 1, 18, 19, and 20 of chip U4 are connected in parallel; one end of capacitor C26 is connected to pin 5 of chip U4, and the other end of capacitor C26 is grounded; resistor R18 is connected in parallel between pins 5 and 11 of chip U4; resistor R15 is connected in parallel between pins 5 and 9 of chip U4; and one end of capacitor C27 is connected to pin 5 of chip U4. One end of capacitor C27 is grounded; one end of capacitor C3 is connected to pin 15 of chip U4, and the other end of capacitor C33 is grounded; one end of resistor RX1 is connected to pin 16 of chip U4, and the other end of resistor RX1 is connected to one end of resistor RX2, and the other end of resistor RX2 is connected to pin 1 of chip U4; one end of resistor RY1 is connected to pin 16 of chip U4, and the other end of resistor RY1 is connected to one end of resistor RY2, and the other end of resistor RY2 is grounded; one end of capacitor C28 is connected to pin 1 of chip U4, and the other end of capacitor C28 is grounded.
[0026] In some possible implementations, the control module further includes: a separate pulse capture circuit, an FPGA circuit, and a communication circuit; the separate pulse capture circuit, the FPGA circuit, and the communication circuit are connected in sequence.
[0027] Among them, the separation pulse capture circuit is used to acquire external separation signals and convert the external separation signals into preset separation signals adapted to the FPGA circuit;
[0028] The communication circuit is used to establish a data exchange path between the FPGA circuit and the external data interface;
[0029] The FPGA circuit is used to convert the preset separation signal into a TTL signal based on external data and send it to the RF switch module.
[0030] In some possible implementations, the RF switch module further includes: a switch driver circuit and an RF switch circuit; the switch driver circuit and the RF switch circuit are connected.
[0031] Among them, the switch drive circuit is used to generate a variety of different drive levels according to the TTL signal;
[0032] The radio frequency switch circuit is used to control the corresponding controlled antenna to receive / transmit signals according to the drive level.
[0033] In some possible implementations, the RF switch circuit also includes: inductors L2, L3, L4, L5, L6, L7; capacitors C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50; resistors R23, R24, R25, R26; chip RFSW1; and chip U6.
[0034] One end of capacitor C45 is grounded, and the other end is connected to one end of inductor L4. One end of resistor R23 is connected to the power management module, and the other end is connected to one end of inductor L4. The other end of inductor L4 is connected to pin 11 of chip RFSW1. One end of capacitor C47 is connected to the switch driver circuit, and the other end is connected to pin 11 of chip RFSW1. One end of capacitor C40 is connected to the switch driver circuit, and the other end is connected to pin 3 of chip RFSW1. One end of inductor L3 is connected to the core... Pin 3 of RFSW1 is connected to one end of inductor L3, which in turn connects to one end of resistor R26. The other end of resistor R26 is connected to one end of inductor L6, and the other end of inductor L6 is connected to pin 6 of RFSW1. One end of capacitor C42 is connected to the other end of inductor L3, and the other end of capacitor C42 is grounded. One end of inductor L5 is connected to pin 4 of RFSW1, and the other end of inductor L5 is connected to one end of resistor R25. The other end of resistor R25 is connected to one end of inductor L7, and the other end of inductor L7 is connected to pin 7 of RFSW1. Pins; one end of capacitor C46 is connected to the other end of inductor L5, and the other end of capacitor C46 is grounded; one end of capacitor C48 is connected to the other end of inductor L6, and the other end of capacitor C48 is grounded; one end of capacitor C49 is connected to the other end of inductor L7, and the other end of capacitor C49 is grounded; one end of capacitor C50 is connected to the seventh pin of chip RFSW1, and the other end of capacitor C50 is connected to the switch drive circuit; the fifth pin of chip U6 is connected to the other end of resistor R25, the seventh pin of chip U6 is connected to one end of resistor R26, and the sixth pin of chip U6... One pin is connected to one end of inductor L2, and the other end of inductor L2 is connected to the power management module; one end of capacitor C41 is connected to one end of inductor L2, and the other end of capacitor C41 is grounded; one end of capacitor C43 is connected to one end of inductor L2, and the other end of capacitor C43 is grounded; one end of capacitor C44 is connected to the other end of inductor L2, and the other end of capacitor C44 is grounded; the second and fourth pins of chip U6 are connected in parallel; one end of resistor R24 is grounded, and the other end of resistor R24 is connected to the second pin of chip U6, which receives the control antenna.
[0035] In summary, compared with the prior art, the above-described technical solution conceived by this utility model can achieve the following beneficial effects:
[0036] This invention provides an antenna control system that integrates a power management module, a control module, and an RF switch module into a single system. This achieves overall miniaturization and integration of the antenna control system, reducing its footprint and improving its portability and installation flexibility. By acquiring external discrete signals and converting them into TTL signals for transmission to the RF switch module, automated control of controlled antenna switching is achieved. This eliminates the need for manual operation of complex switches or parameter adjustments; simply providing an external signal triggers the switching of the controlled antenna, simplifying operation, reducing operational difficulty, and improving work efficiency. The system can output multiple power supply voltages to meet the needs of different modules, allowing it to flexibly adapt to various working environments and voltage conditions. Controlling the RF switch module to switch the operating controlled antennas enables effective management of multiple controlled antennas, improving communication efficiency and enhancing system reliability and flexibility. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 A schematic diagram of a module of an embodiment of the antenna control system provided by this utility model;
[0039] Figure 2 A schematic diagram of an embodiment of the power management module provided by this utility model;
[0040] Figure 3 A schematic diagram of the circuit structure of an embodiment of the surge protection circuit provided by this utility model;
[0041] Figure 4 A schematic diagram of the circuit structure of an embodiment of the voltage regulator circuit provided by this utility model;
[0042] Figure 5 A schematic diagram of the circuit structure of an embodiment of the first voltage conversion circuit, the second voltage conversion circuit, and the third voltage conversion circuit provided by this utility model;
[0043] Figure 6 A schematic diagram of a module of an embodiment of the control module provided by this utility model;
[0044] Figure 7 A schematic diagram of an embodiment of the radio frequency switch module provided by this utility model;
[0045] Figure 8A schematic diagram of the circuit structure of an embodiment of the radio frequency switch circuit provided by this utility model. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model. Furthermore, the technical features involved in the various embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.
[0047] The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of a module of an embodiment of the antenna control system provided by the present invention. In a specific embodiment of the present invention, an antenna control system 100 is disclosed, including: a power management module 110, a control module 120 and a radio frequency switch module 130; the power management module 110, the control module 120 and the radio frequency switch module 130 are connected in sequence; the power management module 110 is also connected to the radio frequency switch module 130.
[0049] Among them, the power management module 110 is used to convert the external input voltage into various power supply voltages to power the control module 120 and the radio frequency switch module 130;
[0050] The control module 120 is used to acquire external separation signals and convert them into TTL signals to send to the radio frequency switch module 130;
[0051] The radio frequency switch module 130 is used to switch the operating controlled antenna 200 according to the TTL signal.
[0052] In the above embodiment, the power management module 110 is responsible for receiving external input voltage, which can come from the power grid, battery, or other power supply devices. The power management module 110 is internally equipped with various voltage conversion circuits, including a surge protection circuit 111, a voltage regulator circuit 112, a first voltage conversion circuit 113, a second voltage conversion circuit 114, and a third voltage conversion circuit 115. The surge protection circuit 111 first limits and absorbs surge voltages in the external input voltage to protect subsequent circuits from damage. The voltage after surge protection enters the voltage regulator circuit 112, which stabilizes it at a preset initial voltage level to ensure the stable operation of the entire system. Then, the preset initial voltage is converted into various different voltages to power different parts of the system. Through such voltage conversion and management, the power management module 110 can stably and reliably provide various different power supply voltages to the entire antenna control system 100, ensuring the normal operation and high efficiency of the system.
[0053] The control module 120 is highly intelligent and automated, capable of acquiring various discrete signals from the external environment in real time. These signals can originate from different communication devices, sensors, or other signal sources, carrying information about the switching requirements of the controlled antenna 200, communication status, or other important data. The control module 120 uses internal signal processing circuits and algorithms to analyze and process these complex discrete signals, then converts them into standard TTL (Transistor-to-Transistor Logic) signals. TTL signals are commonly used digital signals with both high and low levels, facilitating transmission and processing in circuits. The control module 120 sends the converted TTL signals to the RF switch module 130 to achieve precise control of the switching of the controlled antenna 200.
[0054] The RF switch module 130 quickly and accurately switches the operating controlled antenna 200 according to the TTL signal sent by the control module 120. The RF switch module 130 employs internal switching circuitry and RF isolation technology to ensure signal integrity and stability during the switching process of the controlled antenna 200. Simultaneously, the RF switch module 130 also possesses excellent performance characteristics such as low loss and high isolation, effectively improving the overall performance of the communication system. Upon receiving the TTL signal, the internal switching circuitry of the RF switch module 130 responds rapidly, switching the currently operating controlled antenna 200 to the designated controlled antenna 200, thereby enabling the reception and transmission of communication signals.
[0055] It is worth noting that, in addition to providing power to the control module 120 and the RF switch module 130, the power management module 110 is also directly connected to the RF switch module 130. This design allows the power management module 110 to monitor the operating status of the RF switch module 130 in real time and adjust the supply voltage or take other protective measures as needed, thereby further improving the stability and reliability of the system.
[0056] Compared with existing technologies, the antenna control system 100 provided in this embodiment integrates the power management module 110, the control module 120, and the RF switch module 130 into a single system, achieving overall miniaturization and integration of the antenna control system 100. This not only reduces the system's footprint but also improves its portability and installation flexibility. By acquiring external discrete signals and converting them into TTL signals, the switching of the controlled antenna 200 is automatically controlled. There is no need for manual operation of complex switches or parameter adjustments; simply providing an external signal triggers the switching of the controlled antenna 200, simplifying the operation steps, reducing operational difficulty, and improving work efficiency. It can output multiple power supply voltages to meet the needs of different modules, allowing the system to flexibly adapt to different working environments and voltage conditions. Controlling the RF switch module 130 to switch the operating controlled antennas 200 enables effective management of multiple controlled antennas 200, improving communication efficiency and enhancing system reliability and flexibility.
[0057] Please see Figure 2 , Figure 2 This is a schematic diagram of a power management module according to an embodiment of the present invention. In some embodiments of the present invention, the power management module 110 further includes: a surge protection circuit 111, a voltage regulator circuit 112, a first voltage conversion circuit 113, a second voltage conversion circuit 114, and a third voltage conversion circuit 115; the surge protection circuit 111 is connected to the voltage regulator circuit 112; the voltage regulator circuit 112 is connected to the first voltage conversion circuit 113 and the second voltage conversion circuit 114 respectively; the first voltage conversion circuit 113 is connected to the third voltage conversion circuit 115.
[0058] Among them, the surge protection circuit 111 is used to limit and absorb the surge voltage in the external input voltage to obtain the surge-protected external input voltage;
[0059] The voltage regulator circuit 112 is used to regulate the external input voltage for surge protection to obtain a preset initial voltage;
[0060] The first voltage conversion circuit 113 is used to convert a preset initial voltage into a first preset voltage;
[0061] The second voltage conversion circuit 114 is used to convert the preset initial voltage into a second preset voltage;
[0062] The third voltage conversion circuit 115 is used to convert the first preset voltage into the third preset voltage.
[0063] In the above embodiment, the surge protection circuit 111 is used to limit and absorb surge voltages in the external input voltage. Surge voltages are usually generated by instantaneous high voltages in the power grid or lightning strikes, and if they are not limited and absorbed, they may damage subsequent circuits. The surge protection circuit 111 absorbs surge energy through internal nonlinear components (such as varistors, gas discharge tubes, etc.), thereby protecting the safety of subsequent circuits.
[0064] The voltage regulator circuit 112 stabilizes the external input voltage after surge protection at a preset initial voltage level. The voltage regulator circuit 112 usually adopts the form of a linear regulator or a switching regulator, and achieves precise control of the output voltage through internal feedback mechanism and adjustment element.
[0065] The first voltage conversion circuit 113 and the second voltage conversion circuit 114 start from the preset initial voltage output by the voltage regulator circuit 112 and perform different voltage conversions. The first voltage conversion circuit 113 converts the preset initial voltage into a first preset voltage, while the second voltage conversion circuit 114 converts the preset initial voltage into a second preset voltage. Through precise voltage conversion, these two circuits ensure that different components inside the system can obtain appropriate power supply voltages.
[0066] The third voltage conversion circuit 115 is connected to the first voltage conversion circuit 113. It further converts the first preset voltage into the third preset voltage, enabling the power management module 110 to provide a wider range of voltage output options and meet the more diverse power supply needs within the system.
[0067] It is understood that the preset initial voltage, first preset voltage, second preset voltage, and third preset voltage can all be adjusted according to actual needs, and this utility model does not impose further restrictions in this regard.
[0068] Please see Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of one embodiment of the surge protection circuit provided by this utility model. In some embodiments of this utility model, the surge protection circuit 111 further includes: chip U1, surge protection chip E1, chip EMI1; resistors R1, R2, R3, R4, R5, R6, R8, R9, R12; capacitors C1, C13, C14, C15, C16, C17; and Zener diodes Q1 and Q2.
[0069] Specifically, pins 5, 6, 7, and 8 of chip U1 are connected to the positive terminal of the external input voltage and one end of resistors R2 and R5. The other end of resistor R2 is connected to pin 5 of surge protection chip E1, and the other end of resistor R5 is connected to pin 8 of surge protection chip E1. Pin 3 of Zener diode Q1 is connected to pin 5 of surge protection chip E1, and pin 1 of Zener diode Q1 is connected to pin 6 of surge protection chip E1. Pin 3 of Zener diode Q2 is connected to pin 6 of surge protection chip E1, and pin 1 of Zener diode Q2 is connected to the negative terminal of the external input voltage. One end of resistor R9... One end of resistor R9 is connected to pin 8 of surge protector chip E1; the other end of resistor R9 is connected to pin 7 of surge protector chip E1; one end of resistor R12 is connected to pin 7 of surge protector chip E1, and the other end of resistor R12 is connected to the negative terminal of the external input voltage; one end of resistor R3 is connected to pin 4 of chip U1, and the other end of resistor R3 is connected to pin 4 of surge protector chip E1; resistor R4 is connected in parallel across resistor R3; capacitor C1 is connected in parallel with pins 4 and 5 of surge protector chip E1; pins 1, 2, and 3 of chip U1 are connected in parallel with pin 3 of surge protector chip E1; one end of resistor R1... Connect one end of resistor R1 to pin 3 of surge protector chip E1; connect the other end of resistor R1 to pin 2 of surge protector chip E1; connect one end of resistor R6 to pin 2 of surge protector chip E1, and connect the other end of resistor R6 to pin 1 of surge protector chip E1; connect one end of resistor R8 to pin 1 of surge protector chip E1, and connect the other end of resistor R8 to the negative terminal of the external input voltage; connect one end of capacitor C17 to the negative terminal of the external input voltage, and connect the other end of capacitor C17 to pin 12 of surge protector chip E1; connect one end of capacitor C13 to pin 2 of surge protector chip E1, and connect the other end of capacitor C13 to the external input voltage. Negative terminal; one end of capacitor C14 is connected to the second pin of surge protector chip E1, and the other end of capacitor C14 is connected to the negative terminal of the external input voltage; one end of capacitor C15 is connected to the second pin of surge protector chip E1, and the other end of capacitor C15 is connected to the negative terminal of the external input voltage; one end of capacitor C16 is connected to the second pin of surge protector chip E1, and the other end of capacitor C16 is connected to the negative terminal of the external input voltage; the first pin of chip EMI1 is connected to the second pin of surge protector chip E1, the second pin of chip EMI1 is connected to the negative terminal of the external input voltage, and the third and fourth pins of chip EMI1 are connected to voltage regulator circuit 112.
[0070] In the above embodiment, when the external 28V voltage enters the circuit, it first passes through the surge protection circuit 111, which is based on a high voltage surge suppressor with current limiting function, model LT4363MPMS-2#PBF. This circuit can withstand a transient voltage of 40V, not exceeding 1s. The EMI filter is used to shield the circuit from electromagnetic interference.
[0071] Please see Figure 4 , Figure 4The schematic diagram of the circuit structure of one embodiment of the voltage regulator circuit provided by this utility model is shown. In some embodiments of this utility model, the voltage regulator circuit 112 further includes: capacitors C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C18, C19, C20, C21, C22, and C23; resistors R7, R10, R11, RH1, and RL1; and chips U2 and L1.
[0072] Specifically, capacitors C3, C4, C5, and C6 are connected in parallel between pins 1 and 3 of chip U2, which in turn are connected to pins 3 and 4 of chip EMI1. One end of resistor R11 is connected to pin 2 of chip U2, and the other end is connected to pin 3 of chip U2. Resistor R7 is connected in parallel between pins 7 and 8 of chip U2. Resistor R10 is connected in parallel between pins 4 and 5 of chip U2. Resistor RH1 is connected in parallel between pins 6 and 8 of chip U2. Resistor RL1 is connected in parallel between pins 4 and 6 of chip U2. One end of capacitor C7 is connected to pin 8 of chip U2, and the other end is connected to one end of capacitor C18, which in turn is connected to pin 4 of chip U2. One end of capacitor C8 is connected to pin 8 of chip U2, and the other end is connected to capacitor C19. One end of capacitor C19 is connected to the fourth pin of chip U2; the first pin of chip L1 is connected to the fourth pin of chip U2, and the second pin of chip L1 is connected to the eighth pin of chip U2; one end of capacitor C9 is connected to the third pin of chip L1, and the other end of capacitor C9 is connected to one end of capacitor C20, and the other end of capacitor C20 is connected to the fourth pin of chip L1; one end of capacitor C10 is connected to the third pin of chip L1, and the other end of capacitor C10 is connected to one end of capacitor C21, and the other end of capacitor C21 is connected to the fourth pin of chip L1; one end of capacitor C11 is connected to the third pin of chip L1, and the other end of capacitor C11 is connected to one end of capacitor C22, and the other end of capacitor C22 is connected to the fourth pin of chip L1; one end of capacitor C12 is connected to the third pin of chip L1, and the other end of capacitor C12 is connected to one end of capacitor C23, and the other end of capacitor C23 is connected to the fourth pin of chip L1.
[0073] In the above embodiments, the voltage regulator circuit 112, combined with the surge protection circuit 111, can first absorb and limit overvoltage and overcurrent in the circuit, providing a more stable and safer input voltage, ensuring the normal operation of the system. This dual protection mechanism significantly improves the reliability and safety of the system. When the mains voltage fluctuates significantly, the voltage regulator circuit 112 can adjust the output voltage to maintain it within a set range. This allows the system to better adapt to different power grid environments, helping to reduce system errors and improve system accuracy and stability.
[0074] Please see Figure 5, Figure 5 The circuit structure diagram of one embodiment of the first voltage conversion circuit, the second voltage conversion circuit, and the third voltage conversion circuit provided by this utility model is shown. In some embodiments of this utility model, the first voltage conversion circuit 113 further includes: chip U3, capacitors C24, C25, C29, C30, C31, and C32, and resistors R13, R14, R16, and R17.
[0075] Among them, pin 12 of chip U3 is connected to voltage regulator circuit 112, and pin 11 of chip U3 is connected to pin 12 of chip U3; one end of capacitor C31 is connected to pin 12 of chip U3, and the other end of capacitor C31 is grounded; one end of capacitor C30 is connected to pin 8 of chip U3, and the other end of capacitor C31 is grounded; one end of resistor R16 is connected to pin 7 of chip U3, and the other end of resistor R16 is grounded; one end of capacitor C32 is connected to pin 9 of chip U3, and the other end of capacitor C32 is grounded; capacitor C24 is connected in parallel. Connect the resistor R13 between the second and third pins of chip U3; connect the resistor R14 in parallel between the fourth and fifth pins of chip U3; connect one end of capacitor C29 to the fourth pin of chip U3 and the other end of capacitor C29 to ground; connect one end of capacitor C25 to the fifth pin of chip U3 and the other end of capacitor C25 to ground; connect one end of resistor R14 to the fifth pin of chip U3 and the other end of resistor R14 to the sixth pin of chip U3; connect one end of resistor R17 to the sixth pin of chip U3 and the other end of resistor R17 to ground.
[0076] In some embodiments of this utility model, the second voltage conversion circuit 114 further includes: chip U5, capacitors C34, C35, C36, C37, C38, and C39, and resistors R19, R20, R21, and R22.
[0077] In this circuit, pin 12 of chip U5 is connected to voltage regulator circuit 112, and pin 11 of chip U5 is connected to pin 12 of chip U5; one end of capacitor C36 is connected to pin 12 of chip U5, and the other end of capacitor C36 is grounded; one end of capacitor C38 is connected to pin 8 of chip U5, and the other end of capacitor C36 is grounded; one end of resistor R21 is connected to pin 7 of chip U5, and the other end of resistor R21 is grounded; one end of capacitor C39 is connected to pin 9 of chip U5, and the other end of capacitor C39 is grounded; capacitor C34 is connected in parallel... Connect the resistor R19 between the second and third pins of chip U5; connect the resistor R19 in parallel between the fourth and fifth pins of chip U5; connect one end of capacitor C37 to the fourth pin of chip U5 and the other end of capacitor C37 to ground; connect one end of capacitor C35 to the fifth pin of chip U5 and the other end of capacitor C35 to ground; connect one end of resistor R20 to the fifth pin of chip U5 and the other end of resistor R20 to the sixth pin of chip U5; connect one end of resistor R22 to the sixth pin of chip U5 and the other end of resistor R22 to ground.
[0078] In some embodiments of this utility model, the third voltage conversion circuit 115 further includes: capacitors C26, C27, C28, and C33; resistors R15, R18, RX1, RX2, RY1, and RY2; and chip U4.
[0079] Specifically, pin 5 of chip U4 is connected to the first voltage conversion circuit 113; pins 5, 6, 7, 8, and 10 of chip U4 are connected in parallel; pins 1, 18, 19, and 20 of chip U4 are connected in parallel; one end of capacitor C26 is connected to pin 5 of chip U4, and the other end of capacitor C26 is grounded; resistor R18 is connected in parallel between pins 5 and 11 of chip U4; resistor R15 is connected in parallel between pins 5 and 9 of chip U4; and one end of capacitor C27 is connected to pin 5 of chip U4. One end of capacitor C27 is grounded; one end of capacitor C3 is connected to pin 15 of chip U4, and the other end of capacitor C33 is grounded; one end of resistor RX1 is connected to pin 16 of chip U4, and the other end of resistor RX1 is connected to one end of resistor RX2, and the other end of resistor RX2 is connected to pin 1 of chip U4; one end of resistor RY1 is connected to pin 16 of chip U4, and the other end of resistor RY1 is connected to one end of resistor RY2, and the other end of resistor RY2 is grounded; one end of capacitor C28 is connected to pin 1 of chip U4, and the other end of capacitor C28 is grounded.
[0080] In the above embodiments, such as Figure 5 As shown, both +28V voltages enter the MAXM17572 power supply chip. Due to the voltage division by the resistors, the two MAXM17572 power supply chips produce different output voltages. One outputs +5V to power the next stage power supply chip, while the other outputs +1.2V as the core voltage for the FPGA. The output voltage formula for the MAXM17572 power supply chip is: Vout = 0.9 * (Rb + Ru) / Rb. The generated +5V voltage, after being supplied to the TPS74401 power supply chip, produces +3.3V to power the FPGA.
[0081] Furthermore, the +3.3V and +1.2V voltages output by the power management module 110 power the control module 120. A high-speed optocoupler acquires external discrete signals, converting the 28V high-voltage pulse signal into a 3.3V low-voltage pulse signal. After hysteresis filtering by a Schmitt trigger, the signal enters the FPGA. The FPGA performs double-edge capture on this signal, determines the pulse width, and if the conditions are met, inverts the 3.3VTTL signal output to the RF switch module 130. The FPGA starts counting when it detects the rising edge of the input signal and ends counting when it detects the falling edge. It then determines the count length; if the requirements are met, it inverts the output pin. Because the input signal and the FPGA clock are in different clock domains, two-stage synchronization processing is required during detection. Additionally, the FPGA periodically uploads its current operating status via serial port.
[0082] Please see Figure 6 , Figure 6 This is a schematic diagram of a control module according to an embodiment of the present invention. In some embodiments of the present invention, the control module 120 further includes: a separate pulse capture circuit 121, an FPGA circuit 122, and a communication circuit 123; the separate pulse capture circuit 121, the FPGA circuit 122, and the communication circuit 123 are connected in sequence.
[0083] Among them, the separation pulse capture circuit 121 is used to acquire external separation signals and convert the external separation signals into preset separation signals that are compatible with the FPGA circuit 122;
[0084] Communication circuit 123 is used to establish a data exchange path between FPGA circuit 122 and external data interface;
[0085] The FPGA circuit 122 is used to convert the preset separation signal into a TTL signal based on external data and send it to the RF switch module 130.
[0086] In the above embodiments, the main function of the separation pulse capture circuit 121 is to acquire external separation signals, which may come from various sensors, triggers, or other signal sources, carrying key information that the device or system needs to process. This circuit uses precise time measurement and signal processing techniques to convert these external signals into preset separation signals compatible with the FPGA circuit 122, ensuring the accuracy and reliability of the signals and providing a solid foundation for subsequent signal processing.
[0087] The FPGA circuit 122 is highly flexible and programmable, capable of processing preset separation signals in real time based on external data. Through its internal logic units and interconnection network, the FPGA circuit 122 implements complex signal processing algorithms and control logic, enabling it to convert preset separation signals into TTL (transistor-to-transistor logic) signals and send them to the RF switch module 130 or other target components. This not only ensures signal compatibility and stability but also improves the system's response speed and reliability.
[0088] The communication circuit 123 establishes a data exchange path between the FPGA circuit 122 and the external data interface, realizing real-time data transmission and sharing. The communication circuit 123 supports multiple communication protocols and data formats, which can meet the needs of different application scenarios. Through the communication circuit 123, the FPGA circuit 122 can receive external data input and output the processed data to the external data interface, thereby realizing seamless connection between internal and external information of the system.
[0089] In the control module 120, the discrete pulse capture circuit 121, the FPGA circuit 122, and the communication circuit 123 are connected in sequence to form a complete signal processing and control link, which can accurately acquire and process external signals to realize complex control logic and algorithms. At the same time, through the connection of the communication circuit 123 with the external data interface, the control module 120 can receive and send data in real time, ensuring the real-time performance and reliability of the system.
[0090] Please see Figure 7 , Figure 7 This is a schematic diagram of an embodiment of the radio frequency switch module provided by the present invention. In some embodiments of the present invention, the radio frequency switch module 130 further includes: a switch driving circuit 131 and a radio frequency switch circuit 132; the switch driving circuit 131 and the radio frequency switch circuit 132 are connected.
[0091] Among them, the switch drive circuit 131 is used to generate a variety of different drive levels according to the TTL signal;
[0092] The radio frequency switch circuit 132 is used to control the corresponding controlled antenna 200 to receive / transmit signals according to the drive level.
[0093] In the above embodiments, the switch driving circuit 131 generates various different driving levels based on the TTL signal from the control module 120, determining the on and off states of the RF switch circuit 132 under different conditions. The switch driving circuit 131 converts the TTL signal into a level signal suitable for the operation of the RF switch circuit 132 through internal logic circuits and driving elements, thereby achieving precise control of the RF switch circuit 132.
[0094] The RF switch circuit 132 is responsible for controlling the corresponding controlled antenna 200 to receive or transmit signals according to the drive level generated by the switch drive circuit 131. The RF switch circuit 132 is typically composed of multiple RF switch units, each of which can be turned on or off under different drive levels. When the switch drive circuit 131 generates a specific drive level, the corresponding switch unit in the RF switch circuit 132 will switch to the corresponding state, thereby realizing the switching and routing of RF signals.
[0095] In the RF switch module 130, the switch drive circuit 131 and the RF switch circuit 132 are closely connected, jointly realizing the precise control and switching of the RF signal. The switch drive circuit 131 generates a variety of different drive levels based on the TTL signal from the control module 120. These drive levels realize the switching and routing of the RF signal through the switching unit in the RF switch circuit 132, which not only improves the flexibility and reliability of the system, but also ensures the precise switching and transmission of the RF signal between multiple controlled antennas 200 or signal paths.
[0096] Please see Figure 8 , Figure 8 This is a schematic diagram of the circuit structure of an embodiment of the radio frequency switch circuit provided by this utility model. In some embodiments of this utility model, the radio frequency switch circuit 132 further includes: inductors L2, L3, L4, L5, L6, L7; capacitors C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50; resistors R23, R24, R25, R26; chip RFSW1; and chip U6.
[0097] Among them, one end of capacitor C45 is grounded, and the other end of capacitor C45 is connected to one end of inductor L4; one end of resistor R23 is connected to power management module 110, and the other end of resistor R23 is connected to one end of inductor L4; the other end of inductor L4 is connected to pin 11 of chip RFSW1; one end of capacitor C47 is connected to switch drive circuit 131, and the other end of capacitor C47 is connected to pin 11 of chip RFSW1; one end of capacitor C40 is connected to switch drive circuit 131, and the other end of capacitor C40 is connected to pin 3 of chip RFSW1; inductor L3... One end of inductor L3 is connected to pin 3 of chip RFSW1; the other end of inductor L3 is connected to one end of resistor R26; the other end of resistor R26 is connected to one end of inductor L6; the other end of inductor L6 is connected to pin 6 of chip RFSW1; one end of capacitor C42 is connected to the other end of inductor L3, and the other end of capacitor C42 is grounded; one end of inductor L5 is connected to pin 4 of chip RFSW1; the other end of inductor L5 is connected to one end of resistor R25; the other end of resistor R25 is connected to one end of inductor L7; the other end of inductor L7 is connected to pin 7 of chip RFSW1. Pin connections: One end of capacitor C46 is connected to the other end of inductor L5, and the other end of capacitor C46 is grounded; one end of capacitor C48 is connected to the other end of inductor L6, and the other end of capacitor C48 is grounded; one end of capacitor C49 is connected to the other end of inductor L7, and the other end of capacitor C49 is grounded; one end of capacitor C50 is connected to the seventh pin of chip RFSW1, and the other end of capacitor C50 is connected to switch driver circuit 131; the fifth pin of chip U6 is connected to the other end of resistor R25, the seventh pin of chip U6 is connected to one end of resistor R26, and the sixth pin of chip U6... One pin is connected to one end of inductor L2, and the other end of inductor L2 is connected to the power management module; one end of capacitor C41 is connected to one end of inductor L2, and the other end of capacitor C41 is grounded; one end of capacitor C43 is connected to one end of inductor L2, and the other end of capacitor C43 is grounded; one end of capacitor C44 is connected to the other end of inductor L2, and the other end of capacitor C44 is grounded; the second and fourth pins of chip U6 are connected in parallel; one end of resistor R24 is grounded, and the other end of resistor R24 is connected to the second pin of chip U6; the second pin of chip U6 receives the control antenna 200.
[0098] In the above embodiment, the 5VTTL signal, after passing through a dual inverting driver, is converted into different high and low levels and enters the RF switch MASW-011055. According to the set truth table (Table 1), different high and low levels can drive the RF switch MASW-011055 to open different channels, as detailed in Table 1 below:
[0099] Table 1
[0100]
[0101] In summary, the antenna control system 100 provided by this utility model integrates the power management module 110, the control module 120, and the RF switch module 130 into a single system, achieving overall miniaturization and integration of the antenna control system 100. This not only reduces the system's footprint but also improves its portability and installation flexibility. By acquiring external discrete signals and converting them into TTL signals, the switching of the controlled antenna 200 is automatically controlled. There is no need for manual operation of complex switches or parameter adjustments; simply providing an external signal triggers the switching of the controlled antenna 200, simplifying the operation steps, reducing operational difficulty, and improving work efficiency. It can output multiple power supply voltages to meet the needs of different modules, allowing the system to flexibly adapt to different working environments and voltage conditions. Controlling the RF switch module 130 to switch the operating controlled antennas 200 enables effective management of multiple controlled antennas 200, improving communication efficiency and enhancing system reliability and flexibility.
[0102] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.
[0103] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0104] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between devices or units may be electrical or other forms.
[0105] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0106] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0107] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.
[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0109] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. An antenna control system, characterized in that, include: The system includes a power management module, a control module, and an RF switch module; the power management module, the control module, and the RF switch module are connected in sequence; the power management module is also connected to the RF switch module. The power management module is used to convert the external input voltage into various supply voltages to power the control module and the radio frequency switch module. The control module is used to acquire external separation signals and convert the external separation signals into TTL signals and send them to the radio frequency switch module; The radio frequency switch module is used to switch the operating controlled antenna according to the TTL signal.
2. The antenna control system as described in claim 1, characterized in that, The power management module further includes: a surge protection circuit, a voltage regulator circuit, a first voltage conversion circuit, a second voltage conversion circuit, and a third voltage conversion circuit; the surge protection circuit is connected to the voltage regulator circuit; the voltage regulator circuit is connected to the first voltage conversion circuit and the second voltage conversion circuit respectively; the first voltage conversion circuit is connected to the third voltage conversion circuit. The surge protection circuit is used to limit and absorb surge voltage in the external input voltage to obtain a surge-protected external input voltage. The voltage regulator circuit is used to regulate the external input voltage for surge protection to obtain a preset initial voltage. The first voltage conversion circuit is used to convert the preset initial voltage into a first preset voltage; The second voltage conversion circuit is used to convert the preset initial voltage into a second preset voltage; The third voltage conversion circuit is used to convert the first preset voltage into a third preset voltage.
3. The antenna control system as described in claim 2, characterized in that, The surge protection circuit also includes: chip U1, surge protection chip E1, chip EMI1; resistors R1, R2, R3, R4, R5, R6, R8, R9, R12; capacitors C1, C13, C14, C15, C16, C17; and Zener diodes Q1 and Q2. Specifically, the fifth, sixth, seventh, and eighth pins of chip U1 are connected to the positive terminal of the external input voltage and one end of resistors R2 and R5. The other end of resistor R2 is connected to the fifth pin of surge protection chip E1, and the other end of resistor R5 is connected to the eighth pin of surge protection chip E1. The third pin of Zener diode Q1 is connected to the fifth pin of surge protection chip E1, and the first pin of Zener diode Q1 is connected to the sixth pin of surge protection chip E1. The third pin of Zener diode Q2 is connected to the sixth pin of surge protection chip E1, and the first pin of Zener diode Q2 is connected to the negative terminal of the external input voltage. One end of resistor R9 is connected to... The surge protection chip E1's eighth pin is connected to the surge protection chip E1's seventh pin; one end of resistor R9 is connected to the surge protection chip E1's seventh pin, and the other end of resistor R12 is connected to the negative terminal of the external input voltage; one end of resistor R3 is connected to the chip U1's fourth pin, and the other end of resistor R3 is connected to the surge protection chip E1's fourth pin; resistor R4 is connected in parallel across resistor R3; capacitor C1 is connected in parallel with the surge protection chip E1's fourth and fifth pins; the first, second, and third pins of chip U1 are connected in parallel with the surge protection chip E1's third pin; one end of resistor R1 is connected to... The surge protection chip E1 has its third pin connected to the surge protection chip E1. The other end of resistor R1 is connected to the second pin of the surge protection chip E1. One end of resistor R6 is connected to the second pin of the surge protection chip E1, and the other end is connected to the first pin of the surge protection chip E1. One end of resistor R8 is connected to the first pin of the surge protection chip E1, and the other end is connected to the negative terminal of the external input voltage. One end of capacitor C17 is connected to the negative terminal of the external input voltage, and the other end is connected to the twelfth pin of the surge protection chip E1. One end of capacitor C13 is connected to the second pin of the surge protection chip E1, and the other end is connected to the external input voltage. The capacitor C14 is connected to the negative terminal of the external input voltage; one end of the capacitor C14 is connected to the second pin of the surge protection chip E1, and the other end of the capacitor C14 is connected to the negative terminal of the external input voltage; one end of the capacitor C15 is connected to the second pin of the surge protection chip E1, and the other end of the capacitor C15 is connected to the negative terminal of the external input voltage; one end of the capacitor C16 is connected to the second pin of the surge protection chip E1, and the other end of the capacitor C16 is connected to the negative terminal of the external input voltage; the first pin of the EMI1 chip is connected to the second pin of the surge protection chip E1, the second pin of the EMI1 chip is connected to the negative terminal of the external input voltage, and the third and fourth pins of the EMI1 chip are connected to the voltage regulator circuit.
4. The antenna control system as described in claim 3, characterized in that, The voltage regulator circuit also includes: capacitors C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C18, C19, C20, C21, C22, and C23; resistors R7, R10, R11, RH1, and RL1; and chips U2 and L1. Specifically, capacitors C3, C4, C5, and C6 are connected in parallel between the first and third pins of chip U2, and the first and third pins of chip U2 are connected to the third and fourth pins of chip EMI1; one end of resistor R11 is connected to the second pin of chip U2, and the other end of resistor R11 is connected to the third pin of chip U2; resistor R7 is connected in parallel between the seventh and eighth pins of chip U2; resistor R10 is connected in parallel between the fourth and fifth pins of chip U2; resistor RH1 is connected in parallel between the sixth and eighth pins of chip U2; resistor RL1 is connected in parallel between the fourth and sixth pins of chip U2; one end of capacitor C7 is connected to the eighth pin of chip U2, and the other end of capacitor C7 is connected to one end of capacitor C18, and the other end of capacitor C18 is connected to the fourth pin of chip U2; one end of capacitor C8 is connected to the eighth pin of chip U2, and the other end of capacitor C8 is connected to one end of capacitor C19. The other end of capacitor C19 is connected to the fourth pin of chip U2; the first pin of chip L1 is connected to the fourth pin of chip U2, and the second pin of chip L1 is connected to the eighth pin of chip U2; one end of capacitor C9 is connected to the third pin of chip L1, and the other end of capacitor C9 is connected to one end of capacitor C20, and the other end of capacitor C20 is connected to the fourth pin of chip L1; one end of capacitor C10 is connected to the third pin of chip L1, and the other end of capacitor C10 is connected to one end of capacitor C21, and the other end of capacitor C21 is connected to the fourth pin of chip L1; one end of capacitor C11 is connected to the third pin of chip L1, and the other end of capacitor C11 is connected to one end of capacitor C22, and the other end of capacitor C22 is connected to the fourth pin of chip L1; one end of capacitor C12 is connected to the third pin of chip L1, and the other end of capacitor C12 is connected to one end of capacitor C23, and the other end of capacitor C23 is connected to the fourth pin of chip L1.
5. The antenna control system as described in claim 2, characterized in that, The first voltage conversion circuit also includes: chip U3, capacitors C24, C25, C29, C30, C31, and C32, and resistors R13, R14, R16, and R17; In this circuit, pin 12 of chip U3 is connected to the voltage regulator circuit, and pin 11 of chip U3 is connected to pin 12 of chip U3; one end of capacitor C31 is connected to pin 12 of chip U3, and the other end of capacitor C31 is grounded; one end of capacitor C30 is connected to pin 8 of chip U3, and the other end of capacitor C31 is grounded; one end of resistor R16 is connected to pin 7 of chip U3, and the other end of resistor R16 is grounded; one end of capacitor C32 is connected to pin 9 of chip U3, and the other end of capacitor C32 is grounded; capacitor C24 is connected in parallel... Between the second and third pins of chip U3; resistor R13 is connected in parallel between the fourth and fifth pins of chip U3; one end of capacitor C29 is connected to the fourth pin of chip U3, and the other end of capacitor C29 is grounded; one end of capacitor C25 is connected to the fifth pin of chip U3, and the other end of capacitor C25 is grounded; one end of resistor R14 is connected to the fifth pin of chip U3, and the other end of resistor R14 is connected to the sixth pin of chip U3; one end of resistor R17 is connected to the sixth pin of chip U3, and the other end of resistor R17 is grounded.
6. The antenna control system as described in claim 2, characterized in that, The second voltage conversion circuit also includes: chip U5, capacitors C34, C35, C36, C37, C38, and C39, and resistors R19, R20, R21, and R22; Specifically, pin 12 of chip U5 is connected to the voltage regulator circuit, and pin 11 of chip U5 is connected to pin 12 of chip U5; one end of capacitor C36 is connected to pin 12 of chip U5, and the other end of capacitor C36 is grounded; one end of capacitor C38 is connected to pin 8 of chip U5, and the other end of capacitor C36 is grounded; one end of resistor R21 is connected to pin 7 of chip U5, and the other end of resistor R21 is grounded; one end of capacitor C39 is connected to pin 9 of chip U5, and the other end of capacitor C39 is grounded; capacitor C34 is connected in parallel... Between the second and third pins of chip U5; resistor R19 is connected in parallel between the fourth and fifth pins of chip U5; one end of capacitor C37 is connected to the fourth pin of chip U5, and the other end of capacitor C37 is grounded; one end of capacitor C35 is connected to the fifth pin of chip U5, and the other end of capacitor C35 is grounded; one end of resistor R20 is connected to the fifth pin of chip U5, and the other end of resistor R20 is connected to the sixth pin of chip U5; one end of resistor R22 is connected to the sixth pin of chip U5, and the other end of resistor R22 is grounded.
7. The antenna control system as described in claim 2, characterized in that, The third voltage conversion circuit also includes: capacitors C26, C27, C28, and C33; resistors R15, R18, RX1, RX2, RY1, and RY2; and chip U4. Specifically, the fifth pin of chip U4 is connected to the first voltage conversion circuit; the fifth, sixth, seventh, eighth, and tenth pins of chip U4 are connected in parallel; the first, eighteenth, nineteenth, and twentieth pins of chip U4 are connected in parallel; one end of capacitor C26 is connected to the fifth pin of chip U4, and the other end of capacitor C26 is grounded; resistor R18 is connected in parallel between the fifth and eleventh pins of chip U4; resistor R15 is connected in parallel between the fifth and ninth pins of chip U4; one end of capacitor C27 is connected to the fifth pin of chip U4; and capacitor C... The other end of capacitor C3 is grounded; one end of capacitor C3 is connected to the fifteenth pin of chip U4, and the other end of capacitor C3 is grounded; one end of resistor RX1 is connected to the sixteenth pin of chip U4, the other end of resistor RX1 is connected to one end of resistor RX2, and the other end of resistor RX2 is connected to the first pin of chip U4; one end of resistor RY1 is connected to the sixteenth pin of chip U4, the other end of resistor RY1 is connected to one end of resistor RY2, and the other end of resistor RY2 is grounded; one end of capacitor C28 is connected to the first pin of chip U4, and the other end of capacitor C28 is grounded.
8. The antenna control system as described in claim 1, characterized in that, The control module further includes: a separate pulse capture circuit, an FPGA circuit, and a communication circuit; the separate pulse capture circuit, the FPGA circuit, and the communication circuit are connected in sequence. The separation pulse capture circuit is used to acquire the external separation signal and convert the external separation signal into a preset separation signal adapted to the FPGA circuit. The communication circuit is used to establish a data exchange path between the FPGA circuit and the external data interface. The FPGA circuit is used to convert the preset separation signal into a TTL signal based on external data and send it to the radio frequency switch module.
9. The antenna control system as described in claim 1, characterized in that, The radio frequency switch module further includes: a switch driving circuit and a radio frequency switch circuit; the switch driving circuit and the radio frequency switch circuit are connected. The switch driving circuit is used to generate various different driving levels based on the TTL signal; The radio frequency switch circuit is used to control the corresponding controlled antenna to receive / transmit signals according to the drive level.
10. The antenna control system as described in claim 9, characterized in that, The radio frequency switch circuit also includes: inductors L2, L3, L4, L5, L6, L7; capacitors C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50; resistors R23, R24, R25, R26; chip RFSW1; and chip U6. In this configuration, one end of capacitor C45 is grounded, and the other end of capacitor C45 is connected to one end of inductor L4. One end of resistor R23 is connected to the power management module, and the other end of resistor R23 is connected to one end of inductor L4. The other end of inductor L4 is connected to pin 11 of chip RFSW1. One end of capacitor C47 is connected to the switch drive circuit, and the other end of capacitor C47 is connected to pin 11 of chip RFSW1. One end of capacitor C40 is connected to the switch drive circuit, and the other end of capacitor C40 is connected to pin 3 of chip RFSW1. One end of inductor L3 is connected to... The third pin of the RFSW1 chip is connected to the third pin of the RFSW1 chip. One end of the inductor L3 is connected to one end of the resistor R26, the other end of the resistor R26 is connected to one end of the inductor L6, and the other end of the inductor L6 is connected to the sixth pin of the RFSW1 chip. One end of the capacitor C42 is connected to the other end of the inductor L3, and the other end of the capacitor C42 is grounded. One end of the inductor L5 is connected to the fourth pin of the RFSW1 chip, and the other end of the inductor L5 is connected to one end of the resistor R25, the other end of the resistor R25 is connected to one end of the inductor L7, and the other end of the inductor L7 is connected to the seventh pin of the RFSW1 chip. Pins; one end of capacitor C46 is connected to the other end of inductor L5, and the other end of capacitor C46 is grounded; one end of capacitor C48 is connected to the other end of inductor L6, and the other end of capacitor C48 is grounded; one end of capacitor C49 is connected to the other end of inductor L7, and the other end of capacitor C49 is grounded; one end of capacitor C50 is connected to the seventh pin of chip RFSW1, and the other end of capacitor C50 is connected to the switch drive circuit; the fifth pin of chip U6 is connected to the other end of resistor R25, the seventh pin of chip U6 is connected to one end of resistor R26, and the third pin of chip U6 is connected to the other end of resistor R25. The six pins are connected to one end of the inductor L2, and the other end of the inductor L2 is connected to the power management module; one end of the capacitor C41 is connected to one end of the inductor L2, and the other end of the capacitor C41 is grounded; one end of the capacitor C43 is connected to one end of the inductor L2, and the other end of the capacitor C43 is grounded; one end of the capacitor C44 is connected to the other end of the inductor L2, and the other end of the capacitor C44 is grounded; the second and fourth pins of the chip U6 are connected in parallel; one end of the resistor R24 is grounded, and the other end of the resistor R24 is connected to the second pin of the chip U6, which receives the control antenna.