Negative voltage shift circuit, radio frequency switch and radio frequency module

Abstract

The utility model relates to a negative voltage shift circuit, a radio frequency switch and a radio frequency module. The negative voltage shift circuit comprises a control input stage module which is configured to determine and obtain a first control signal and a second control signal which are opposite to each other based on a positive reference level and a ground level under the control of an initial signal; the negative voltage generation stage module is configured to switch a conduction branch of the cross coupling structure so as to obtain a third control signal and a fourth control signal; the intermediate isolation stage module is configured to perform isolation conversion on the second control signal and the third control signal to obtain a third group of double-state signals; and the output stage module is configured to determine to obtain a first substrate control signal and a first grid control signal under the control of the third group of dual-state signals so as to control the on-off of the first switch. The negative voltage shift circuit provided by the utility model is rapid in conversion, low in power consumption and small in area.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a negative voltage level shifting circuit, a radio frequency switch, and a radio frequency module. Background Technology

[0002] Radio frequency (RF) switches are an important component of wireless communication systems and are one of the most basic devices on the antenna port. For example, they are in high demand in mobile terminals such as mobile phones.

[0003] Currently, NMOS transistors, also known as N-type MOS transistors (metal-oxide-semiconductor field-effect transistors), are commonly used as the basic switching devices in radio frequency (RF) switches. For example, when the gate (G) is connected to 2.5V and the substrate (B) is connected to 0V, the NMOS transistor is turned on, and the RF switch can be turned on. When the gate (G) is connected to -2.5V and the substrate (B) is connected to -2.5V, the NMOS transistor is turned off, and the RF switch can be turned off.

[0004] However, external control signals are typically 0 / 2.5V levels. Directly applying these signals to the gate (G) and substrate (B) cannot achieve the on / off control of the NMOS transistor. A negative voltage-level converter (NLC) is needed to convert the 0 / 2.5V level to -2.5V / 2.5V to meet the requirements for NMOS transistor on / off control. Therefore, providing a negative voltage-level converter is crucial. Utility Model Content

[0005] In view of this, the present application provides a negative voltage level shifting circuit, a radio frequency switch, and a radio frequency module to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a negative voltage level shifting circuit, the negative voltage level shifting circuit comprising:

[0007] The control input stage module is configured to determine a first set of dual-state signals based on a positive reference level and a ground level under the control of an initial signal; wherein the first set of dual-state signals includes a first control signal and a second control signal that are inversely related to each other;

[0008] The negative pressure generating stage module is configured to switch the conducting branch of the cross-coupled structure according to the level of the first set of bi-state signals to obtain a second set of bi-state signals; wherein, the second set of bi-state signals includes a third control signal and a fourth control signal; the levels of the third control signal and the fourth control signal are determined according to the positive reference level and the negative reference level, respectively;

[0009] An intermediate isolation level module is configured to include at least one of the following: isolating and converting the second control signal and the third control signal to obtain a third set of dual-state signals; isolating and converting the first control signal and the fourth control signal to obtain a fourth set of dual-state signals; wherein the third set of dual-state signals includes a first switch control signal and a second switch control signal, the first switch control signal being determined based on a positive reference level and a ground level under the control of the second control signal, and the second switch control signal being determined based on a negative reference level and a ground level under the control of the third control signal; the fourth set of dual-state signals includes a first switch control signal and a second switch control signal, the first switch control signal being determined based on a positive reference level and a ground level under the control of the first control signal, and the second switch control signal being determined based on a negative reference level and a ground level under the control of the fourth control signal; and

[0010] The output stage module is configured to include at least one of the following: under the control of the third set of dual-state signals, determining a first substrate control signal based on a negative reference level and a ground level and determining a first gate control signal based on a positive reference level and a negative reference level to control the on / off state of switch number one; under the control of the fourth set of dual-state signals, determining a second substrate control signal based on a negative reference level and a ground level and determining a second gate control signal based on a positive reference level and a negative reference level to control the on / off state of switch number two.

[0011] In conjunction with the first aspect, in an alternative implementation,

[0012] The negative pressure generating stage module includes:

[0013] A control module is configured to switch the transmission of a positive reference level under the control of the first set of dual-state signals, so that one of the third control signal and the fourth control signal obtains a positive reference level; and

[0014] The cross-coupling structure module is configured to switch the transmission of the negative reference level based on the cross-coupling structure, so that when one of the third control signal and the fourth control signal obtains a positive reference level, the other obtains a negative reference level; and latches the levels of the third control signal and the fourth control signal.

[0015] In conjunction with the first aspect, in an alternative implementation,

[0016] The negative pressure generating stage module also includes:

[0017] A protection module is coupled between the generation control module and the cross-coupled structure module to reduce the voltage between the control terminal and the output terminal of the transmission transistor in the generation control module to a preset threshold.

[0018] In conjunction with the first aspect, in an alternative implementation,

[0019] The negative voltage generation stage module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

[0020] The gate of the first PMOS transistor is configured to acquire a first control signal, and the gate of the second PMOS transistor is configured to acquire a second control signal.

[0021] The source, substrate, source, and substrate of the first PMOS transistor are respectively configured to obtain a positive reference level; the drain of the first PMOS transistor is connected to the source of the third PMOS transistor; and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor.

[0022] The gates of the third PMOS transistor and the fourth PMOS transistor are configured to acquire ground level; the substrates of the third PMOS transistor and the fourth PMOS transistor are configured to acquire positive reference level; the drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor and configured to output a third control signal; the drain of the fourth PMOS transistor is connected to the drain of the sixth NMOS transistor and configured to output a fourth control signal.

[0023] The gates of the fifth and sixth NMOS transistors are configured to acquire ground level; the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor; the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor and the gate of the seventh NMOS transistor; the substrates of the fifth, sixth, seventh, and eighth NMOS transistors, the source of the seventh NMOS transistor, and the source of the eighth NMOS transistor are configured to acquire negative reference level.

[0024] In conjunction with the first aspect, in an alternative implementation,

[0025] The control input stage module includes a first inverter and a second inverter;

[0026] The input terminal of the first inverter is configured to acquire an initial signal; the output terminal of the first inverter is connected to the input terminal of the second inverter and configured to output a first control signal; the output terminal of the second inverter is configured to output a second control signal.

[0027] The first power supply terminals of the first inverter and the second inverter are respectively configured to obtain a positive reference level, and the second power supply terminals of the first inverter and the second inverter are respectively configured to obtain a ground level.

[0028] In conjunction with the first aspect, in an alternative implementation,

[0029] The intermediate isolation level module includes at least one of the following: a first isolation module; a second isolation module;

[0030] The first isolation module includes a third inverter, a fourth inverter, a fifth buffer, and a sixth buffer;

[0031] The input terminal of the third inverter is configured to acquire the second control signal; the output terminal of the third inverter is connected to the input terminal of the fourth inverter; the output terminal of the fourth inverter is connected to the input terminal of the fifth buffer; the output terminal of the fifth buffer is configured to output the first switch control signal.

[0032] The input terminal of the sixth buffer is configured to acquire the third control signal, and the output terminal of the sixth buffer is configured to output the second switch control signal.

[0033] The first power supply terminals of the third inverter, the fourth inverter, and the fifth buffer are configured to acquire a positive reference level, and the second power supply terminals of the third inverter, the fourth inverter, and the fifth buffer are configured to acquire a ground level; the first power supply terminal of the sixth buffer is configured to acquire a ground level, and the second power supply terminal of the sixth buffer is configured to acquire a negative reference level.

[0034] The second isolation module includes a seventh inverter, an eighth inverter, a ninth buffer, and a tenth buffer;

[0035] The input terminal of the seventh inverter is configured to acquire the first control signal, and the output terminal of the seventh inverter is connected to the input terminal of the eighth inverter; the output terminal of the eighth inverter is connected to the input terminal of the ninth buffer; the output terminal of the ninth buffer is configured to output the first switch control signal.

[0036] The input terminal of the tenth buffer is configured to acquire the fourth control signal, and the output terminal of the tenth buffer is configured to output the second switch control signal.

[0037] The first power supply terminals of the seventh inverter, the eighth inverter, and the ninth buffer are configured to acquire a positive reference level, and the second power supply terminals of the seventh inverter, the eighth inverter, and the ninth buffer are configured to acquire a ground level; the first power supply terminal of the tenth buffer is configured to acquire a ground level, and the second power supply terminal of the tenth buffer is configured to acquire a negative reference level.

[0038] In conjunction with the first aspect, in an alternative implementation,

[0039] The output stage module includes at least one of the following: a first output module; a second output module;

[0040] The first output module includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and an eleventh inverter;

[0041] The gate of the ninth PMOS transistor is configured to acquire the first switch control signal; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor; the gate of the tenth PMOS transistor is configured to acquire the ground level; the source of the ninth PMOS transistor, the substrate of the ninth PMOS transistor, and the substrate of the tenth PMOS transistor are respectively configured to acquire the positive reference level.

[0042] The drain of the tenth PMOS transistor is connected to the drain of the eleventh NMOS transistor and configured to output the first gate control signal.

[0043] The gate of the eleventh NMOS transistor is configured to acquire the ground level; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; the gate of the twelfth NMOS transistor is configured to acquire the second switch control signal; the source of the twelfth NMOS transistor, the substrate of the twelfth NMOS transistor, and the substrate of the eleventh NMOS transistor are respectively configured to acquire the negative reference level.

[0044] The input terminal of the eleventh inverter U11 is configured to acquire the second switch control signal, the output terminal of the eleventh inverter is configured to output the first substrate control signal, the first power supply terminal of the eleventh inverter is configured to acquire the ground level, and the second power supply terminal of the eleventh inverter is configured to acquire the negative reference level.

[0045] The second output module includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a twelfth inverter;

[0046] The gate of the thirteenth PMOS transistor is configured to acquire the first switch control signal; the drain of the thirteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor; the gate of the fourteenth PMOS transistor is configured to acquire the ground level; the source of the thirteenth PMOS transistor, the substrate of the thirteenth PMOS transistor, and the substrate of the fourteenth PMOS transistor are respectively configured to acquire the positive reference level.

[0047] The drain of the fourteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor and configured to output the second gate control signal;

[0048] The gate of the fifteenth NMOS transistor is configured to acquire a ground level; the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor; the gate of the sixteenth NMOS transistor is configured to acquire the second control signal of the second switch; the source of the sixteenth NMOS transistor, the substrate of the sixteenth NMOS transistor, and the substrate of the fifteenth NMOS transistor are respectively configured to acquire a negative reference level;

[0049] The input terminal of the twelfth inverter is configured to acquire the second switch control signal, the output terminal of the twelfth inverter is configured to output the second substrate control signal, the first power supply terminal of the twelfth inverter is configured to acquire the ground level, and the second power supply terminal of the twelfth inverter is configured to acquire the negative reference level.

[0050] In a second aspect, embodiments of this application provide a radio frequency switch, the radio frequency switch including a switching transistor and a negative voltage level shifting circuit as described in the first aspect;

[0051] The first signal terminal of the switching transistor is configured as the input terminal of the radio frequency switch, and the second signal terminal of the switching transistor is configured as the output terminal of the radio frequency switch;

[0052] The negative voltage level shift circuit is configured to output a first gate control signal to the control terminal of the switching transistor and output a first substrate control signal to the substrate of the switching transistor to control the switching transistor to be turned on or off.

[0053] Thirdly, embodiments of this application provide a radio frequency switch, characterized in that the radio frequency switch includes a first switch, a second switch, and a negative voltage level shifting circuit as described in the first aspect;

[0054] The first signal terminal of switch number one is configured as the input terminal of the radio frequency switch, and the second signal terminal of switch number one is configured as the output terminal of the radio frequency switch;

[0055] The first signal terminal of switch number two is connected to the output terminal of the radio frequency switch, and the second signal terminal of switch number two is grounded.

[0056] The negative voltage level shifting circuit is configured to output a first gate control signal to the control terminal of switch one and output a first substrate control signal to the substrate of switch one to control switch one to be turned on or off; and to output a second gate control signal to the control terminal of switch two and output a second substrate control signal to the substrate of switch two to control switch two to be turned on or off, so that one of switch one and switch two is turned off during the other's conduction period.

[0057] Fourthly, embodiments of this application provide a radio frequency module, the radio frequency module including at least one of the following: a radio frequency switch as described in the second aspect; a radio frequency switch as described in the third aspect.

[0058] The beneficial effects of the technical solution provided in this application include: by using the negative voltage generation stage module, the conducting branch of the cross-coupled structure is switched according to the level of the first set of dual-state signals to obtain the second set of dual-state signals, which speeds up the switching speed and has a simple circuit structure and small area; and by using the intermediate isolation stage module and the output stage module, isolation conversion is achieved, reducing power consumption, thereby providing a negative voltage level shifting circuit that is fast in conversion, low in power consumption and small in area.

[0059] Additional aspects and advantages of the embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of this application. Attached Figure Description

[0060] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, are provided. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of those features. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0061] Figure 1 This is a schematic block diagram illustrating a specific example of a negative voltage level shifting circuit in this application.

[0062] Figure 2 This is a circuit diagram illustrating a specific example of the negative pressure generating stage module in this application.

[0063] Figure 3 This is a circuit diagram illustrating a specific example of a control input stage module in an embodiment of this application.

[0064] Figure 4 This is a circuit diagram illustrating a specific example of an intermediate isolation level module in an embodiment of this application.

[0065] Figure 5 This is a circuit diagram illustrating a specific example of the output stage module in an embodiment of this application.

[0066] Figure 6 This is a schematic block diagram illustrating the principle of a specific example of a radio frequency switch in an embodiment of this application.

[0067] Figure 7 This is a schematic block diagram illustrating another specific example of a radio frequency switch in the embodiments of this application. Detailed Implementation

[0068] To make the technical solution and beneficial effects of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0069] The embodiments described in this application are not exhaustive, but merely illustrative of some embodiments, and are not intended to limit the scope of protection of this application. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined with each other. For example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0070] In each embodiment of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0071] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application.

[0072] In the embodiments of this application, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun after the article can be understood as either a singular expression or a plural expression.

[0073] In the embodiments of this application, "multiple" refers to two or more.

[0074] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0075] The prefixes "first," "second," etc., used in the embodiments of this application are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects is based on the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, the numerical value of the descriptive object is not limited by ordinal numbers and can be one or more. Taking "first device" as an example, the numerical value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the descriptive object is "device," then "first device" and "second device" can be the same device or different devices, and their types can be the same or different.

[0076] In some embodiments, the term "connection" can refer to the transmission of electrical signals or data between the connected end and the connected end, and can be understood as "electrical connection," "communication connection," etc. A "connection" can be a direct connection between two components, an indirect connection established through other components, a connection within two components, or any other possible form of connection.

[0077] In some embodiments, the terms “greater than”, “greater than or equal to”, “not less than”, “more than”, “more than or equal to”, “not less than”, “higher than”, “higher than or equal to”, “not lower than”, “above”, “exceeding”, etc. can be used interchangeably, and the terms “less than”, “less than or equal to”, “not greater than”, “less than”, “less than or equal to”, “not more than”, “lower than”, “lower than or equal to”, “not higher than”, “below”, etc. can be used interchangeably.

[0078] In some embodiments, high voltage and low voltage, or high voltage and low voltage, or high level and low level, can be relative values, not necessarily absolute values.

[0079] In some embodiments, a transistor can be a single transistor; or it can be a series and / or parallel connection of multiple transistors, each having functional electrodes corresponding to the individual functional electrodes of a single transistor, and also having the same operating states as a single transistor, such as on and off states. For example, a single transistor may include a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), whose functional electrodes may include a gate (G), source (S), drain (D), and substrate (B). The series and / or parallel connection of multiple transistors then has gate G, source S, drain D, and substrate B corresponding to the gate G, source S, drain D, and substrate B of a single MOSFET, and the operating states corresponding to the single MOSFET. MOSFETs may include P-type MOSFETs (PMOS transistors) and N-type MOSFETs (NMOS transistors).

[0080] In some embodiments, a transistor may include a control terminal, a first signal terminal, and a second signal terminal. Its operating principle is that, under the control of a control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off, thereby connecting or blocking signal transmission between the first signal terminal and the second signal terminal. In exemplary embodiments, the transistor may include at least one of the following: a MOSFET; a BJT (bipolar junction transistor); an IGBT (insulated gate bipolar transistor); a GTO (gate turn-off thyristor); a SCR (silicon controlled rectifier); an MCT (MOS-controlled thyristor); an IGCT (integrated gate commutated thyristor); an IEGT (electron injection enhancement gate transistor); and so on.

[0081] This application provides a negative voltage level shifting circuit. Figure 1 A schematic block diagram illustrating a specific example of a negative voltage level shifting circuit according to an embodiment of this application is shown. As shown, the negative voltage level shifting circuit includes:

[0082] The control input stage module 10 is configured to determine a first set of bistate signals based on the positive reference level VDD and the ground level GND under the control of the initial signal EN; wherein the first set of bistate signals includes a first control signal Q and a second control signal QB that are inversely related to each other;

[0083] The negative pressure generating stage module 20 is configured to switch the conducting branch of the cross-coupled structure according to the level of the first set of bi-state signals to obtain a second set of bi-state signals; wherein, the second set of bi-state signals includes a third control signal V1 and a fourth control signal V1B; the level of the third control signal V1 and the level of the fourth control signal V1B are determined according to the positive reference level VDD and the negative reference level VBB, respectively.

[0084] The intermediate isolation stage module 30 is configured to include at least one of the following: isolating and converting the second control signal QB and the third control signal V1 to obtain a third set of dual-state signals; isolating and converting the first control signal Q and the fourth control signal V1B to obtain a fourth set of dual-state signals; wherein the third set of dual-state signals includes a first switch control signal B and a second switch control signal BN, the first switch control signal B being determined based on a positive reference level VDD and a ground level GND under the control of the second control signal QB, and the second switch control signal BN being determined based on a negative reference level VBB and a ground level GND under the control of the third control signal V1; the fourth set of dual-state signals includes a first switch control signal BB and a second switch control signal BBN, the first switch control signal BB being determined based on a positive reference level VDD and a ground level GND under the control of the first control signal Q, and the second switch control signal BBN being determined based on a negative reference level VBB and a ground level GND under the control of the fourth control signal V1B; and

[0085] The output stage module 40 is configured to include at least one of the following: under the control of the third set of dual-state signals, determining a first substrate control signal HVB ​​based on a negative reference level VBB and a ground level GND, and determining a first gate control signal HVG based on a positive reference level VDD and a negative reference level VBB, to control the on / off state of switch number one; under the control of the fourth set of dual-state signals, determining a second substrate control signal RVB based on a negative reference level VBB and a ground level GND, and determining a second gate control signal RVG based on a positive reference level VDD and a negative reference level VBB, to control the on / off state of switch number two.

[0086] In this embodiment, the positive reference level VDD and the negative reference level VBB can be provided by a fixed reference source. The fixed reference source can be constructed from an analog circuit. For example, the positive reference level VDD is 2.5V, and the negative reference level VBB is -2.5V. The ground level GND can be 0V, which can be obtained by directly grounding.

[0087] refer to Figure 1 The implementation process of the negative voltage level shift circuit is as follows:

[0088] The control input stage module 10 receives the initial signal EN of 0 / VDD and outputs the first set of dual-state signals (Q and QB). For example, the first control signal Q is VDD / 0, and the second control signal QB is 0 / VDD.

[0089] The first set of dual-state signals (Q and QB) are transmitted to the negative pressure generation stage module 20 and the intermediate isolation stage module 30, respectively. The negative pressure generation stage module 20 generates and outputs the second set of dual-state signals (V1 and V1B), and then transmits them to the intermediate isolation stage module 30. For example, the third control signal V1 is VBB / VDD, and the fourth control signal V1B is VDD / VBB. That is, when V1 is VDD, V1B is VBB; or when V1 is VBB, V1B is VDD.

[0090] The intermediate isolation stage module 30 can generate and output a third set of dual-state signals (B and BN), and / or a fourth set of dual-state signals (BB and BBN). For example, the first switch control signal B is 0 / VDD, and the second switch control signal BN is VBB / 0, meaning that when B is 0V, BN is VBB; or when B is VDD, BN is 0V. Simultaneously, the first switch control signal BB is VDD / 0, and the second switch control signal BBN is 0 / VBB, meaning that corresponding to B and BN, BB is VDD and BBN is 0V; or BB is 0V and BBN is VBB.

[0091] Finally, the output stage module 40 can generate and output HVB and HVG to control the on / off state of switch number one, and / or RVB and RVG to control the on / off state of switch number two. The first substrate control signal HVB ​​is 0 / VBB, and the first gate control signal HVG is VDD / VBB, that is, when HVB is 0, HVG is VDD; or when HVB is VBB, HVG is VBB. At the same time, the second substrate control signal RVB is VBB / 0, and the second gate control signal RVG is VBB / VDD, that is, corresponding to HVB and HVG, RVB is VBB, and RVG is VBB; or RVB is 0, and RVG is VDD.

[0092] In this embodiment, the cross-coupling structure can be configured according to actual needs; for example, a cross-coupling structure using NMOS transistors can be used. Switch one and switch two can both be NMOS transistors.

[0093] Thus, this embodiment of the application uses a negative voltage generation stage module to switch the conduction branch of the cross-coupled structure according to the level of the first set of dual-state signals to obtain the second set of dual-state signals, which speeds up the switching speed and has a simple circuit structure and small area; and through the intermediate isolation stage module and the output stage module, isolation conversion is achieved, reducing power consumption, thereby providing a negative voltage level shifting circuit that is fast in conversion, low in power consumption and small in area.

[0094] In this embodiment, the control input stage module 10, the negative pressure generation stage module 20, the intermediate isolation stage module 30, and the output stage module 40 can all be configured according to actual needs. The specific circuit structure of each of the above modules will be described in detail below, but it is not limited thereto.

[0095] Figure 2 A circuit diagram of a specific example of a negative pressure generating stage module according to an embodiment of this application is shown. As shown, in an optional embodiment, the negative pressure generating stage module 20 includes:

[0096] The generation control module 201 is configured to switch the transmission of the positive reference level VDD under the control of the first set of dual-state signals, so that one of the third control signal V1 and the fourth control signal V1B obtains the positive reference level VDD; and

[0097] The cross-coupling structure module 202 is configured to switch the transmission of the negative reference level VBB based on the cross-coupling structure, so that when one of the third control signal V1 and the fourth control signal V1B obtains the positive reference level VDD, the other obtains the negative reference level VBB; and latches the levels of the third control signal V1 and the fourth control signal V1B.

[0098] Thus, in this embodiment of the application, the conduction of one path through the cross-coupling structure can control the disconnection of the other path opposite to that path, thereby achieving voltage latching, generating negative voltage, and improving the stability of the third and fourth control signals.

[0099] In an optional embodiment, the negative pressure generating stage module 20 further includes:

[0100] The protection module 203 is coupled between the generation control module 201 and the cross-coupled structure module 202 to reduce the voltage between the control terminal and the output terminal of the transmission transistor in the generation control module 201 to a preset threshold.

[0101] Thus, by adding a protection module 203 between the generation control module 201 and the cross-coupling structure module 202, this embodiment of the application can significantly reduce the gate-drain voltage of the MOS transistor in the generation control module 201, reduce the drain voltage swing, reduce the voltage stress on the generation control module 201, and improve circuit safety and stability. The preset threshold can be set according to actual needs.

[0102] In an optional embodiment, the negative voltage generating stage module 20 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, and an eighth NMOS transistor M8.

[0103] The gate of the first PMOS transistor M1 is configured to acquire the first control signal Q, and the gate of the second PMOS transistor M2 is configured to acquire the second control signal QB.

[0104] The source of the first PMOS transistor M1, the substrate of the first PMOS transistor M1, the source of the second PMOS transistor M2, and the substrate of the second PMOS transistor M2 are respectively configured to obtain a positive reference level VDD; the drain of the first PMOS transistor M1 is connected to the source of the third PMOS transistor M3; the drain of the second PMOS transistor M2 is connected to the source of the fourth PMOS transistor M4.

[0105] The gates of the third PMOS transistor M3 and the fourth PMOS transistor M4 are configured to acquire the ground level GND; the substrates of the third PMOS transistor M3 and the fourth PMOS transistor M4 are configured to acquire the positive reference level VDD; the drain of the third PMOS transistor M3 is connected to the drain of the fifth NMOS transistor M5 and configured to output the third control signal V1; the drain of the fourth PMOS transistor M4 is connected to the drain of the sixth NMOS transistor M6 and configured to output the fourth control signal V1B.

[0106] The gate of the fifth NMOS transistor M5 and the gate of the sixth NMOS transistor M6 are configured to obtain the ground level GND; the source of the fifth NMOS transistor M5 is connected to the drain of the seventh NMOS transistor M7 and the gate of the eighth NMOS transistor M8, respectively; the source of the sixth NMOS transistor M6 is connected to the drain of the eighth NMOS transistor M8 and the gate of the seventh NMOS transistor M7, respectively; the substrates of the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, the eighth NMOS transistor M8, the source of the seventh NMOS transistor M7, and the source of the eighth NMOS transistor M8 are configured to obtain the negative reference level VBB, respectively.

[0107] In this embodiment, the seventh NMOS transistor M7 and the eighth NMOS transistor M8 can form a cross-coupled structure. The first PMOS transistor M1 and the second PMOS transistor M2 can be used as transmission transistors in the generation control module 201, respectively. By connecting the first PMOS transistor M1 and the fifth NMOS transistor M5 in series with the third PMOS transistor M3, and connecting the second PMOS transistor M2 and the sixth NMOS transistor M6 in series with the fourth PMOS transistor M4, the gate-drain voltage Vgd of the first PMOS transistor M1 and the second PMOS transistor M2 are reduced respectively.

[0108] In an exemplary embodiment, when the initial signal EN is 0V, the first control signal Q is at a high potential of 2.5V, and the second control signal QB is 0V; the second PMOS transistor M2 and the fourth PMOS transistor M4 are turned on, and the fourth control signal V1B is 2.5V.

[0109] When the positive reference level VDD and the negative reference level VBB are simultaneously powered on, at the instant the source voltages of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 drop, because the gates of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 are in a floating state, their gate voltages will decrease due to the parasitic capacitance Cgs, until they reach the level that turns on the fifth NMOS transistor M5 and the sixth NMOS transistor M6. Since the gate terminals of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are fixed to GND, at the instant of power-on, both the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are momentarily turned on, charging points C and D respectively; however, due to the effect of the upper structure, only one is ultimately turned on and the other is turned off.

[0110] In the upper structure, the second control signal QB is 0V, so the second PMOS transistor M2 and the fourth PMOS transistor M4 are turned on, making the fourth control signal V1B 2.5V. Meanwhile, the first control signal Q is 2.5V, the first PMOS transistor M1 is turned off, and no current charges the output point of the third control signal V1. Therefore, at this instant, the potential of the third control signal V1 is 0V. The Vds of the sixth NMOS transistor M6 is greater than that of the fifth NMOS transistor M5, so the current flowing through the sixth NMOS transistor M6 is greater than the current flowing through the fifth NMOS transistor M5. Furthermore, the charging speed at point D is greater than that at point C, causing the voltage at point D to rise faster. This causes the seventh NMOS transistor M7 to turn on first. The turning on of the seventh NMOS transistor M7 further accelerates the discharge speed at point C, causing the voltage at point C to decrease until it drops to -2.5V, causing the eighth NMOS transistor M8 to turn off, and the voltage at point D is latched. Simultaneously, the fifth NMOS transistor M5 turns on, and the potential at point C is transferred to the third control signal V1, which is -2.5V.

[0111] At this point, the third control signal V1 is output at -2.5V, and the fourth control signal V1B is output at 2.5V. The negative voltage generation stage module 20 is an NLC core structure, completing the level shift.

[0112] Similarly, when the initial signal EN is 2.5V, the first control signal Q is 0V, and the second control signal QB is 2.5V; the first PMOS transistor M1 and the third PMOS transistor M3 are turned on, and the third control signal V1 is 2.5V. The second PMOS transistor M2 is turned off, and the fourth control signal V1B is -2.5V.

[0113] Figure 3 A circuit diagram illustrating a specific example of a control input stage module according to an embodiment of this application is shown. As shown, in an optional embodiment, the control input stage module 10 includes a first inverter U1 and a second inverter U2;

[0114] The input terminal of the first inverter U1 is configured to acquire the initial signal EN; the output terminal of the first inverter U1 is connected to the input terminal of the second inverter U2 and configured to output the first control signal Q; the output terminal of the second inverter U2 is configured to output the second control signal QB.

[0115] The first power supply terminals of the first inverter U1 and the second inverter U2 are respectively configured to acquire the positive reference level VDD, and the second power supply terminals of the first inverter U1 and the second inverter U2 are respectively configured to acquire the ground level GND.

[0116] In this embodiment, the inverter can be selected according to actual needs, and its specific circuit structure can be set according to actual needs.

[0117] Figure 4 A circuit diagram illustrating a specific example of an intermediate isolation level module in an embodiment of this application is shown. As shown, in an optional embodiment, the intermediate isolation level module 30 includes at least one of the following: a first isolation module 301; a second isolation module 302;

[0118] The first isolation module 301 includes a third inverter U3, a fourth inverter U4, a fifth buffer U5, and a sixth buffer U6;

[0119] The input terminal of the third inverter U3 is configured to acquire the second control signal QB. The output terminal of the third inverter U3 is connected to the input terminal of the fourth inverter U4. The output terminal of the fourth inverter U4 is connected to the input terminal of the fifth buffer U5. The output terminal of the fifth buffer U5 is configured to output the first switch control signal B.

[0120] The input terminal of the sixth buffer U6 is configured to acquire the third control signal V1, and the output terminal of the sixth buffer U6 is configured to output the second switch control signal BN.

[0121] The first power supply terminals of the third inverter U3, the fourth inverter U4, and the fifth buffer U5 are configured to acquire a positive reference level VDD, and the second power supply terminals of the third inverter U3, the fourth inverter U4, and the fifth buffer U5 are configured to acquire a ground level GND; the first power supply terminal of the sixth buffer U6 is configured to acquire a ground level GND, and the second power supply terminal of the sixth buffer U6 is configured to acquire a negative reference level VBB.

[0122] The second isolation module 302 includes a seventh inverter U7, an eighth inverter U8, a ninth buffer U9, and a tenth buffer U10;

[0123] The input terminal of the seventh inverter U7 is configured to acquire the first control signal Q, and the output terminal of the seventh inverter U7 is connected to the input terminal of the eighth inverter U8; the output terminal of the eighth inverter U8 is connected to the input terminal of the ninth buffer U9; the output terminal of the ninth buffer U9 is configured to output the first switch control signal BB.

[0124] The input terminal of the tenth buffer U10 is configured to acquire the fourth control signal V1B, and the output terminal of the tenth buffer U10 is configured to output the second switch control signal BBN.

[0125] The first power supply terminals of the seventh inverter U7, the eighth inverter U8, and the ninth buffer U9 are configured to acquire the positive reference level VDD, and the second power supply terminals of the seventh inverter U7, the eighth inverter U8, and the ninth buffer U9 are configured to acquire the ground level GND, respectively; the first power supply terminal of the tenth buffer U10 is configured to acquire the ground level GND, and the second power supply terminal of the tenth buffer U10 is configured to acquire the negative reference level VBB.

[0126] In this embodiment, the buffer can be selected according to actual needs, and its specific circuit structure can be set according to actual needs. For example, the buffer can be obtained by connecting two inverters in series.

[0127] The first isolation module 301 and the second isolation module 302 can have the same circuit structure.

[0128] In this way, localization can be achieved through inverters, creating isolation between the input and output signals and improving the stability of the output signal.

[0129] In an exemplary embodiment, when the second control signal QB is 0V, after two stages of inversion and one stage of buffering, the output first switch control signal B is also 0V; at this time, the third control signal V1 is -2.5V, and after one stage of buffering, the output second switch control signal BN is also -2.5V.

[0130] At this time, the first control signal Q is 2.5V. After two stages of inversion and one stage of buffering, the output first switch control signal BB is also 2.5V. The fourth control signal V1B is 2.5V. After one stage of buffering, the output second switch control signal BBN is at a high potential of 0V.

[0131] Similarly, when the second control signal QB is 2.5V, after two stages of inversion and one stage of buffering, the output first switch control signal B is also 2.5V; at this time, the third control signal V1 is 2.5V, after one stage of buffering, the output second switch control signal BN is 0V.

[0132] At this time, the first control signal Q is 0V. After two stages of inversion and one stage of buffering, the output first switch control signal BB is also 0V. The fourth control signal V1B is -2.5V. After one stage of buffering, the output second switch control signal BBN is -2.5V.

[0133] Figure 5 A circuit diagram illustrating a specific example of an output stage module according to an embodiment of this application is shown. As shown, in an optional embodiment, the output stage module 40 includes at least one of the following: a first output module 401; a second output module 402;

[0134] The first output module 401 includes a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and an eleventh inverter U11;

[0135] The gate of the ninth PMOS transistor M9 is configured to acquire the first switch control signal B; the drain of the ninth PMOS transistor M9 is connected to the source of the tenth PMOS transistor M10; the gate of the tenth PMOS transistor M10 is configured to acquire the ground level GND; the source of the ninth PMOS transistor M9, the substrate of the ninth PMOS transistor M9, and the substrate of the tenth PMOS transistor M10 are respectively configured to acquire the positive reference level VDD.

[0136] The drain of the tenth PMOS transistor M10 is connected to the drain of the eleventh NMOS transistor M11 and configured to output the first gate control signal HVG.

[0137] The gate of the eleventh NMOS transistor M11 is configured to acquire the ground level GND; the source of the eleventh NMOS transistor M11 is connected to the drain of the twelfth NMOS transistor M12; the gate of the twelfth NMOS transistor M12 is configured to acquire the second switch control signal BN; the source of the twelfth NMOS transistor M12, the substrate of the twelfth NMOS transistor M12, and the substrate of the eleventh NMOS transistor M11 are respectively configured to acquire the negative reference level VBB;

[0138] The input terminal of the eleventh inverter U11 is configured to acquire the second switch control signal BN, the output terminal of the eleventh inverter U11 is configured to output the first substrate control signal HVB, the first power supply terminal of the eleventh inverter U11 is configured to acquire the ground level GND, and the second power supply terminal of the eleventh inverter U11 is configured to acquire the negative reference level VBB.

[0139] The second output module 402 includes a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth NMOS transistor M16, and a twelfth inverter U12;

[0140] The gate of the thirteenth PMOS transistor M13 is configured to acquire the first switch control signal BB; the drain of the thirteenth PMOS transistor M13 is connected to the source of the fourteenth PMOS transistor M14; the gate of the fourteenth PMOS transistor M14 is configured to acquire the ground level GND; the source of the thirteenth PMOS transistor M13, the substrate of the thirteenth PMOS transistor M13, and the substrate of the fourteenth PMOS transistor M14 are respectively configured to acquire the positive reference level VDD;

[0141] The drain of the fourteenth PMOS transistor M14 is connected to the drain of the fifteenth NMOS transistor M15 and configured to output the second gate control signal RVG.

[0142] The gate of the fifteenth NMOS transistor M15 is configured to acquire the ground level GND; the source of the fifteenth NMOS transistor M15 is connected to the drain of the sixteenth NMOS transistor M16; the gate of the sixteenth NMOS transistor M16 is configured to acquire the second switch control signal BBN; the source of the sixteenth NMOS transistor M16, the substrate of the sixteenth NMOS transistor M16, and the substrate of the fifteenth NMOS transistor M15 are respectively configured to acquire the negative reference level VBB;

[0143] The input terminal of the twelfth inverter U12 is configured to acquire the second switch control signal BBN, the output terminal of the twelfth inverter U12 is configured to output the second substrate control signal RVB, the first power supply terminal of the twelfth inverter U12 is configured to acquire the ground level GND, and the second power supply terminal of the twelfth inverter U12 is configured to acquire the negative reference level VBB.

[0144] In this embodiment of the application, the first output module 401 and the second output module 402 may have the same circuit structure.

[0145] Thus, by setting the tenth PMOS transistor M10 and the eleventh NMOS transistor M11, as well as the fourteenth PMOS transistor M14 and the fifteenth NMOS transistor M15, the embodiments of this application improve the circuit safety and stability, and realize the level conversion from 0 / VDD to 0 / VDD and VBB / VBB.

[0146] In an exemplary embodiment, the operation of the first output module 401 is as follows: when the first switch control signal B is 0V and the second switch control signal BN is -2.5V, the first substrate control signal HVB ​​is 0V; the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are turned off (disconnected), the ninth PMOS transistor M9 and the tenth PMOS transistor M10 are turned on (conducted), and the first gate control signal HVG is 2.5V. The first output module 401 can control the on / off state of switch one (NMOS transistor), the first substrate control signal HVB ​​can be supplied to the substrate of switch one, and the first gate control signal HVG can be supplied to the gate of switch one, so switch one is controlled to be turned on at this time.

[0147] Similarly, when the first switch control signal B is 2.5V and the second switch control signal BN is 0V, the first substrate control signal HVB ​​is -2.5V; the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are turned on (conducting), the ninth PMOS transistor M9 and the tenth PMOS transistor M10 are turned off (disconnected), and the first gate control signal HVG is -2.5V. Therefore, switch one is controlled to turn off at this time.

[0148] Similarly, the workflow of the second output module 402 can be referenced from that of the first output module 401, and will not be repeated here.

[0149] The level conversion relationship of a specific example of the negative voltage level shifting circuit in this application is shown in Table 1 below.

[0150] Table 1

[0151]

[0152]

[0153] This application also provides a radio frequency switch. Figure 6 A schematic block diagram of a specific example of a radio frequency switch according to an embodiment of this application is shown. As shown, the radio frequency switch includes a switching transistor 200 and a negative voltage level shifting circuit 100 as described in the above embodiment;

[0154] The first signal terminal of the switching transistor 200 is configured as the input terminal of the radio frequency switch, and the second signal terminal of the switching transistor 200 is configured as the output terminal of the radio frequency switch;

[0155] The negative voltage level shift circuit 100 is configured to output a first gate control signal HVG to the control terminal of the switching transistor 200 and output a first substrate control signal HVB ​​to the substrate of the switching transistor 200, so as to control the switching transistor 200 to be turned on or off.

[0156] In an exemplary embodiment, the switch 200 may be an NMOS transistor, and its drain (or source) may be configured as the input terminal of the RF switch, while its source (or drain) may be configured as the output terminal of the RF switch. Thus, by controlling the switching on and off of the switch 200 through the negative voltage level shifting circuit 100, the linearity and power handling capability of the RF switch are improved to meet stringent linearity requirements.

[0157] This application also provides a radio frequency switch. Figure 7 A schematic block diagram of another specific example of a radio frequency switch according to an embodiment of this application is shown. As shown, the radio frequency switch includes switch SW1, switch SW2, and a negative voltage level shifting circuit as described in the above embodiment;

[0158] The first signal terminal of switch SW1 is configured as the input terminal of the radio frequency switch, and the second signal terminal of switch SW1 is configured as the output terminal of the radio frequency switch.

[0159] The first signal terminal of switch SW2 is connected to the output terminal of the radio frequency switch, and the second signal terminal of switch SW2 is grounded.

[0160] The negative voltage level shifting circuit is configured to output a first gate control signal HVG to the control terminal of switch SW1 and a first substrate control signal HVB ​​to the substrate of switch SW1 to control switch SW1 to be turned on or off; and to output a second gate control signal RVG to the control terminal of switch SW2 and a second substrate control signal RVB to the substrate of switch SW2 to control switch SW2 to be turned on or off, so that one of switch SW1 and switch SW2 is turned off during the other's conduction period.

[0161] In an exemplary embodiment, switches SW1 and SW2 can be NMOS transistors. The drain (or source) of switch SW1 can be configured as the input terminal of the RF switch, and the source (or drain) of switch SW1 can be configured as the output terminal of the RF switch. The drain (or source) of switch SW2 can be connected to the output terminal of the RF switch, and the drain (or source) of switch SW2 can be grounded. Thus, by controlling the on / off state of switches SW1 and SW2 through a negative voltage level shifting circuit, when switch SW1 is on, the connection between the RF input ANT and the RF output TRX is conducted, and switch SW2 is off, disconnecting the connection between the RF output TRX and ground. When switch SW1 is off, the connection between the RF input ANT and the RF output TRX is disconnected, and switch SW2 is on, grounding the RF output TRX; thereby improving stability and achieving complete shutdown, meeting strict linearity requirements.

[0162] This application embodiment also provides a radio frequency module, the radio frequency module including at least one of the following: such as Figure 6 The radio frequency switch shown; such as Figure 7 The radio frequency switch shown.

[0163] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this application. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A negative voltage level shifting circuit, characterized in that, The negative voltage level shifting circuit includes: The control input stage module is configured to determine a first set of dual-state signals based on a positive reference level and a ground level under the control of an initial signal; wherein the first set of dual-state signals includes a first control signal and a second control signal that are inversely related to each other; The negative pressure generating stage module is configured to switch the conducting branch of the cross-coupled structure according to the level of the first set of bi-state signals to obtain a second set of bi-state signals; wherein, the second set of bi-state signals includes a third control signal and a fourth control signal; the levels of the third control signal and the fourth control signal are determined according to the positive reference level and the negative reference level, respectively; An intermediate isolation level module is configured to include at least one of the following: isolating and converting the second control signal and the third control signal to obtain a third set of dual-state signals; isolating and converting the first control signal and the fourth control signal to obtain a fourth set of dual-state signals; wherein the third set of dual-state signals includes a first switch control signal and a second switch control signal, the first switch control signal being determined based on a positive reference level and a ground level under the control of the second control signal, and the second switch control signal being determined based on a negative reference level and a ground level under the control of the third control signal; the fourth set of dual-state signals includes a first switch control signal and a second switch control signal, the first switch control signal being determined based on a positive reference level and a ground level under the control of the first control signal, and the second switch control signal being determined based on a negative reference level and a ground level under the control of the fourth control signal; and The output stage module is configured to include at least one of the following: under the control of the third set of dual-state signals, determining a first substrate control signal based on a negative reference level and a ground level and determining a first gate control signal based on a positive reference level and a negative reference level to control the on / off state of switch number one; under the control of the fourth set of dual-state signals, determining a second substrate control signal based on a negative reference level and a ground level and determining a second gate control signal based on a positive reference level and a negative reference level to control the on / off state of switch number two.

2. The negative voltage level shifting circuit according to claim 1, characterized in that, The negative pressure generating stage module includes: A control module is configured to switch the transmission of a positive reference level under the control of the first set of dual-state signals, so that one of the third control signal and the fourth control signal obtains a positive reference level; and The cross-coupling structure module is configured to switch the transmission of the negative reference level based on the cross-coupling structure, so that when one of the third control signal and the fourth control signal obtains a positive reference level, the other obtains a negative reference level; and latches the levels of the third control signal and the fourth control signal.

3. The negative voltage level shifting circuit according to claim 2, characterized in that, The negative pressure generating stage module also includes: A protection module is coupled between the generation control module and the cross-coupled structure module to reduce the voltage between the control terminal and the output terminal of the transmission transistor in the generation control module to a preset threshold.

4. The negative voltage level shifting circuit according to any one of claims 1-3, characterized in that, The negative voltage generation stage module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The gate of the first PMOS transistor is configured to acquire a first control signal, and the gate of the second PMOS transistor is configured to acquire a second control signal. The source, substrate, source, and substrate of the first PMOS transistor are configured to obtain a positive reference level; the drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor; The gates of the third PMOS transistor and the fourth PMOS transistor are respectively configured to obtain the ground level; The substrates of the third PMOS transistor and the fourth PMOS transistor are respectively configured to obtain a positive reference level; the drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor and configured to output a third control signal; the drain of the fourth PMOS transistor is connected to the drain of the sixth NMOS transistor and configured to output a fourth control signal. The gates of the fifth and sixth NMOS transistors are configured to acquire ground level; the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor and the gate of the eighth NMOS transistor; the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor and the gate of the seventh NMOS transistor; the substrates of the fifth, sixth, seventh, and eighth NMOS transistors, the source of the seventh NMOS transistor, and the source of the eighth NMOS transistor are configured to acquire negative reference level.

5. The negative voltage level shifting circuit according to any one of claims 1-3, characterized in that, The control input stage module includes a first inverter and a second inverter; The input terminal of the first inverter is configured to acquire an initial signal; the output terminal of the first inverter is connected to the input terminal of the second inverter and configured to output a first control signal. The output of the second inverter is configured to output a second control signal; The first power supply terminals of the first inverter and the second inverter are respectively configured to obtain a positive reference level, and the second power supply terminals of the first inverter and the second inverter are respectively configured to obtain a ground level.

6. The negative voltage level shifting circuit according to any one of claims 1-3, characterized in that, The intermediate isolation level module includes at least one of the following: a first isolation module; Second isolation module; The first isolation module includes a third inverter, a fourth inverter, a fifth buffer, and a sixth buffer; The input of the third inverter is configured to acquire the second control signal, and the output of the third inverter is connected to the input of the fourth inverter; the output of the fourth inverter is connected to the input of the fifth buffer. The output of the fifth buffer is configured to output the first switch control signal; The input terminal of the sixth buffer is configured to acquire the third control signal, and the output terminal of the sixth buffer is configured to output the second switch control signal. The first power supply terminals of the third inverter, the fourth inverter, and the fifth buffer are configured to acquire a positive reference level, and the second power supply terminals of the third inverter, the fourth inverter, and the fifth buffer are configured to acquire a ground level. The first power supply terminal of the sixth buffer is configured to acquire the ground level, and the second power supply terminal of the sixth buffer is configured to acquire the negative reference level. The second isolation module includes a seventh inverter, an eighth inverter, a ninth buffer, and a tenth buffer; The input terminal of the seventh inverter is configured to acquire the first control signal, and the output terminal of the seventh inverter is connected to the input terminal of the eighth inverter. The output of the eighth inverter is connected to the input of the ninth buffer; The output of the ninth buffer is configured to output the second control signal of the first switch; The input terminal of the tenth buffer is configured to acquire the fourth control signal, and the output terminal of the tenth buffer is configured to output the second switch control signal. The first power supply terminals of the seventh inverter, the eighth inverter, and the ninth buffer are configured to acquire a positive reference level, and the second power supply terminals of the seventh inverter, the eighth inverter, and the ninth buffer are configured to acquire a ground level. The first power supply terminal of the tenth buffer is configured to acquire the ground level, and the second power supply terminal of the tenth buffer is configured to acquire the negative reference level.

7. The negative voltage level shifting circuit according to any one of claims 1-3, characterized in that, The output stage module includes at least one of the following: a first output module; a second output module; The first output module includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and an eleventh inverter; The gate of the ninth PMOS transistor is configured to acquire the first switch control signal; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor; the gate of the tenth PMOS transistor is configured to acquire the ground level. The source of the ninth PMOS transistor, the substrate of the ninth PMOS transistor, and the substrate of the tenth PMOS transistor are respectively configured to obtain a positive reference level; The drain of the tenth PMOS transistor is connected to the drain of the eleventh NMOS transistor and configured to output the first gate control signal. The gate of the eleventh NMOS transistor is configured to acquire the ground level; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; the gate of the twelfth NMOS transistor is configured to acquire the second switch control signal; the source of the twelfth NMOS transistor, the substrate of the twelfth NMOS transistor, and the substrate of the eleventh NMOS transistor are respectively configured to acquire the negative reference level. The input terminal of the eleventh inverter U11 is configured to acquire the second switch control signal, the output terminal of the eleventh inverter is configured to output the first substrate control signal, the first power supply terminal of the eleventh inverter is configured to acquire the ground level, and the second power supply terminal of the eleventh inverter is configured to acquire the negative reference level. The second output module includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a twelfth inverter; The gate of the thirteenth PMOS transistor is configured to acquire the first switch control signal; the drain of the thirteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor; the gate of the fourteenth PMOS transistor is configured to acquire the ground level; the source of the thirteenth PMOS transistor, the substrate of the thirteenth PMOS transistor, and the substrate of the fourteenth PMOS transistor are respectively configured to acquire the positive reference level. The drain of the fourteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor and configured to output the second gate control signal; The gate of the fifteenth NMOS transistor is configured to acquire a ground level; the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor; the gate of the sixteenth NMOS transistor is configured to acquire the second control signal of the second switch; the source of the sixteenth NMOS transistor, the substrate of the sixteenth NMOS transistor, and the substrate of the fifteenth NMOS transistor are respectively configured to acquire a negative reference level; The input terminal of the twelfth inverter is configured to acquire the second switch control signal, the output terminal of the twelfth inverter is configured to output the second substrate control signal, the first power supply terminal of the twelfth inverter is configured to acquire the ground level, and the second power supply terminal of the twelfth inverter is configured to acquire the negative reference level.

8. A radio frequency switch, characterized in that, The radio frequency switch includes a switching transistor and a negative voltage level shifting circuit as described in any one of claims 1-7; The first signal terminal of the switching transistor is configured as the input terminal of the radio frequency switch, and the second signal terminal of the switching transistor is configured as the output terminal of the radio frequency switch; The negative voltage level shift circuit is configured to output a first gate control signal to the control terminal of the switching transistor and output a first substrate control signal to the substrate of the switching transistor to control the switching transistor to be turned on or off.

9. A radio frequency switch, characterized in that, The radio frequency switch includes switch number one, switch number two, and the negative voltage level shifting circuit as described in any one of claims 1-7; The first signal terminal of switch number one is configured as the input terminal of the radio frequency switch, and the second signal terminal of switch number one is configured as the output terminal of the radio frequency switch; The first signal terminal of switch number two is connected to the output terminal of the radio frequency switch, and the second signal terminal of switch number two is grounded. The negative voltage level shifting circuit is configured to output a first gate control signal to the control terminal of switch one and output a first substrate control signal to the substrate of switch one to control switch one to be turned on or off; and to output a second gate control signal to the control terminal of switch two and output a second substrate control signal to the substrate of switch two to control switch two to be turned on or off, so that one of switch one and switch two is turned off during the other's conduction period.

10. A radio frequency module, characterized in that, The radio frequency module includes at least one of the following: the radio frequency switch as described in claim 8; the radio frequency switch as described in claim 9.

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