Semiconductor package and integrated circuit wafer

Abstract

The embodiment of the utility model provides an integrated circuit wafer. The integrated circuit wafer comprises a through hole tower formed by stacking conductive layers formed during the manufacturing period of a semiconductor device and an interconnection structure of the integrated circuit wafer. The via towers may be connected to provide power to subsequently stacked integrated circuit wafers. The through-hole tower according to the present disclosure reduces manufacturing costs because the through-hole tower is manufactured without additional processing procedures. The via tower may be integrated in a circuit layout to form a low resistance power rail, thereby improving efficiency.

Description

Technical Field

[0001] This utility model relates to a semiconductor package including a via tower, an integrated circuit wafer, and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using lithography to pattern the various material layers to form circuit components and elements. Tens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer are segmented by sawing between the integrated circuits along scribe lines. Each die is typically individually packaged in, for example, a multi-chip module or other type of package.

[0003] Three-dimensional integrated circuits (3DICs) are a relatively new development in semiconductor packaging, in which multiple semiconductor dies are stacked on top of each other, such as in package-on-package (PoP) and system-in-package (SiP) technologies. 3DICs comprise semiconductor devices with two or more layers of integrated active electronic components, for example, these active electronic components are vertically stacked and interconnected to form an integrated circuit. 3DIC technologies include die-to-die stacking, die-to-wafer stacking, and wafer-to-wafer stacking. Due to, for example, reduced interconnect lengths between stacked dies, 3DIC systems can offer improved integration density and other advantages, such as faster speeds and higher bandwidth. However, compared to two-dimensional systems, 3DIC systems may exhibit higher IR drops, such as voltage drops. Increased IR drops in 3DIC systems lead to increased power consumption and decreased device performance. Utility Model Content

[0004] This disclosure provides a semiconductor package in several embodiments. The semiconductor package includes a first integrated circuit wafer layer, which includes a device layer, a first interconnect structure, a second interconnect structure, and a via tower. The device layer includes a plurality of semiconductor devices. The first interconnect structure is disposed on a first side of the device layer, and the second interconnect structure is disposed on a second side of the device layer. The via tower is configured to provide electrical connections through the first interconnect structure, the device layer, and the second interconnect structure, wherein the via tower includes a stack of conductors passing through the device layer and at least one of the first and second interconnect structures. The semiconductor package also includes a second integrated circuit wafer layer bonded to the first integrated circuit wafer layer, wherein the via tower is electrically connected to the second integrated circuit wafer layer via bonding pad features.

[0005] In some embodiments, the through-hole tower includes: a first conductor stack disposed through the first interconnect structure; and a second conductor stack disposed through the device layer, wherein the second conductor stack contacts the first conductor stack, and the bonding pad feature contacts the first conductor stack.

[0006] This disclosure provides an integrated circuit wafer in several embodiments. The integrated circuit wafer includes a device layer, a first interconnect structure, a second interconnect structure, and a via tower. The device layer includes a plurality of semiconductor devices. The first interconnect structure is disposed on a first side of the device layer, and the second interconnect structure is disposed on a second side of the device layer. The via tower is configured to provide electrical connections through the first interconnect structure, the device layer, and the second interconnect structure. The via tower includes a first conductor stack and a second conductor stack, wherein the first conductor stack passes through the first interconnect structure, the second conductor stack passes through the device layer, and the second conductor stack is in contact with the first conductor stack.

[0007] In some embodiments, the first interconnect structure includes a plurality of inter-metal dielectric layers, and the first conductor stack includes a plurality of embedded conductors in the plurality of inter-metal dielectric layers.

[0008] In some embodiments, each of the plurality of embedded conductors includes: a conductive plate; and a through-hole strip in contact with the conductive plate.

[0009] In some embodiments, each of the plurality of embedded conductors includes: a conductive plate; and an array of through holes in contact with the conductive plate.

[0010] In some embodiments, the through-hole tower further includes: a third conductor stack passing through the second interconnect structure, wherein the third conductor stack is in contact with the second conductor stack.

[0011] In some embodiments, the second interconnect structure includes a back-side power delivery network.

[0012] In some embodiments, the second conductor stack includes: a front conductor disposed on the first side of the device layer; and a back conductor disposed on the second side of the device layer.

[0013] In some embodiments, the second conductor stack further includes: an intermediate conductor disposed between the front conductor and the back conductor, wherein the front conductor and the back conductor are wires along a first direction, and the intermediate conductor is a wire along a second direction. Attached Figure Description

[0014] The concept of the embodiments of this utility model will be better understood by referring to the following detailed description and accompanying drawings. It should be noted that, according to standard industry practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0015] Figure 1 This is a schematic cross-sectional view of a three-dimensional integrated circuit (3DIC) structure according to some embodiments of the present disclosure.

[0016] Figure 2A This is a schematic cross-sectional view of a via tower in an integrated circuit chip according to some embodiments of the present disclosure.

[0017] Figure 2B yes Figure 2A A schematic top view of a through-hole tower.

[0018] Figure 2C This is a schematic partial cross-sectional view of a through-hole tower, showing... Figure 2A Details of the material layers of the through-hole tower.

[0019] Figure 3A This is a schematic cross-sectional view of a through-hole tower in an integrated circuit wafer according to some embodiments of the present disclosure.

[0020] Figure 3B yes Figure 3A A schematic top view of a through-hole tower.

[0021] Figure 4 This is a schematic cross-sectional view of a through-hole tower in an integrated circuit wafer according to some embodiments of the present disclosure.

[0022] Figure 5 This is a schematic cross-sectional view of a through-hole tower in an integrated circuit wafer according to some embodiments of the present disclosure.

[0023] Figure 6A This is a schematic cross-sectional view of a through-hole tower in an integrated circuit wafer according to some embodiments of the present disclosure.

[0024] Figure 6B yes Figure 6A A schematic top view of a through-hole tower.

[0025] Figure 6C This is a schematic partial cross-sectional view of a through-hole tower, showing... Figure 6A Details of the material layers of the through-hole tower.

[0026] Figure 7 This is a flowchart illustrating the formation process of an integrated circuit wafer according to some embodiments of the present disclosure.

[0027] Figures 8A to 8F The illustration schematically shows various processing stages during the manufacture of an integrated circuit wafer according to some embodiments of the present disclosure.

[0028] Figures 9A to 9E The illustration schematically shows various processing stages during the manufacture of an integrated circuit wafer according to some embodiments of the present disclosure.

[0029] Figure 10 This is a schematic cross-sectional view of a three-dimensional integrated circuit structure according to some embodiments of the present disclosure.

[0030] The reference numerals in the attached figures are explained as follows:

[0031] 100, 100a: Three-dimensional integrated circuit (3DIC) structure

[0032] 102: Bottom wafer layer

[0033] 102m: Intermediate wafer layer

[0034] 104: Top wafer layer

[0035] 106: Power Supply

[0036] 120: Device Layer

[0037] 122: First interconnect structure / Front interconnect structure / Interconnect structure

[0038] 124: Second interconnect structure / Backside interconnect structure / Interconnect structure

[0039] 126: Bonding membrane

[0040] 128: Features of the mating pad

[0041] 130, 130a, 130b, 130m: Through-hole tower

[0042] 132: Backside stacking

[0043] 134: Middle Stacking

[0044] 136: Front stacking

[0045] 140: Device Layer

[0046] 142: Interconnection Structure

[0047] 144: Semiconductor substrate

[0048] 146: Bonding membrane

[0049] 148: Features of the mating pad

[0050] 150: Through-hole tower

[0051] 152: Inter-chip communication path

[0052] 152a, 152b: Electrical Path

[0053] 154: Flow Path

[0054] 156: Communication Path

[0055] 156a, 156b: Electrical Path

[0056] 160: Joining pad

[0057] 200, 200a, 200b, 200c, 200d: Integrated circuit chips

[0058] 201: Semiconductor substrate

[0059] 202: Dielectric materials

[0060] 204: Semiconductor Devices

[0061] 204s / d: Source / Drain region

[0062] 204g: Gate structure

[0063] 204ILD: Interlayer Dielectric (ILD) Layer

[0064] 204md: Front-side source / drain contacts

[0065] 204vb: Gate contact

[0066] 204bmd: Backside source / drain contact

[0067] 206: Anterior contact characteristics

[0068] 208: Dorsal contact characteristics

[0069] 210, 2100, 2101, 210 m Intermetallic dielectric (IMD) layer

[0070] 212, 212 m :wire

[0071] 214, 214m Conductive via

[0072] 220: Device Layer

[0073] 222: Front-side interconnect structure / interconnect structure

[0074] 224: Backside Power Delivery Network (PDN) / Backside Interconnect Structure

[0075] 230, 230a, 230b, 230c, 230d: Through-hole towers

[0076] 231: Central axis

[0077] 232, 232a, 232c: Front-side stacking

[0078] 236, 236b, 236c: Intermediate stacking

[0079] 236d: Through-hole network

[0080] 240: Backside dielectric layer

[0081] 242: Conductive via

[0082] 244: Wire

[0083] 252, 2521, 252 m 252 c conductive plate

[0084] 254, 2541, 254 m Through-hole strip

[0085] 254c: Through-hole array

[0086] 254a, 254a m Conductive via / through hole

[0087] 256: Barrier Layer

[0088] 258: Lining

[0089] 262: Through-hole strip / conductive through-hole

[0090] 262b: Front through-hole strip

[0091] 262c: Front through hole

[0092] 262d: Front through-hole strip

[0093] 264: Conductive plate

[0094] 264b: Backside through-hole strip

[0095] 264c: Backside through-hole

[0096] 264d: Backside through-hole strip

[0097] 266d: Intermediate layer through-hole strip / intermediate layer through-hole

[0098] 268: Semiconductor fins

[0099] 300: Method

[0100] 302, 304, 306, 308, 310, 312: Operations

[0101] x, y, z: Direction

[0102] L 252 L 254 L 252a :length

[0103] P 262 P 264 P 266 Pitch

[0104] W 252 W 254 W 254a W 262 W 264 W 266 W 268 :width

[0105] R 262c R 264c :diameter

[0106] T m :thickness

[0107] 2C, 6C: Rectangular area

[0108] 2B-2B, 3B-3B, 6B-6B: Line Detailed Implementation

[0109] The following disclosure provides numerous different embodiments or examples to implement various features of the present invention. Specific examples of components and configurations are described below to simplify the description of the present invention. Of course, these specific examples are merely illustrative and not intended to limit the embodiments of the present invention. For example, in the following description, reference to a first feature being formed on or above a second feature indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself limit the relationship between the various embodiments and / or configurations described.

[0110] In addition, spatial terms such as “below,” “below,” “lower,” “above,” “higher,” and similar terms may be used herein to describe the relationship between one element or feature depicted in the diagram and another element or feature(s). These spatial terms are intended to include, in addition to the orientation shown in the diagram, the different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or otherwise), and the spatial terms used herein may be interpreted accordingly.

[0111] The embodiments described below are for a specific context (i.e., integrated circuit packaging). However, other embodiments can also be applied to other electrical connection components, including but not limited to package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, die-to-wafer assemblies, in assembling packaging, in processing substrates, interposers, etc., or for mounting input components, boards, dies, or other components, or for connection packaging or mounting combinations for any type of integrated circuit or electronic component. The various embodiments described herein allow functional components (e.g., integrated circuit dies) of different functions and sizes (e.g., height) to be packaged in the same integrated circuit package. The various embodiments described herein can be integrated into chip-on-wafer-on-substrate (CoWoS) and chip-on-chip-on-substrate (CoCoS) processes.

[0112] Integrated circuit (IC) structures can include compilations of layers with different functions, such as interconnects, power distribution networks, logic chips, memory chips, radio frequency (RF) chips, etc. As an example, and not a limitation, logic chips can include central processing units (CPUs), while memory chips can include static random-access memory (SRAM) arrays, dynamic random-access memory (DRAM) arrays, magnetic random-access memory (MRAM) arrays, other types of memory arrays, or combinations thereof. Three-dimensional integrated circuit (3DIC) structures are non-monolithic vertical structures developed based on IC structures and can include, for example, two to eight two-dimensional (2D) flip chips stacked on top of each other using various bonding techniques (e.g., hybrid bonding).

[0113] In IC and 3DIC structures, each layer can be interconnected via microbumps, through-silicon vias (TSVs), hybrid bonding, other types of interconnect structures, or combinations thereof. The IC structure is powered by power wire grids, including power lines and ground lines. These grids can be electrically connected to one end of the IC package and supply power to each layer through conductive structures (e.g., grid pillars formed by TSVs). However, as more and more layers are stacked, the increased number of TSVs and interconnect structures in the IC structure can lead to increased resistance and IR drop (e.g., a voltage drop greater than 5%). Furthermore, TSVs used to power device layers through interconnect layers consume valuable signal routing space, increase the resistance of interconnects and TSVs, degrade wafer performance, and shorten the lifespan of the IC structure.

[0114] This invention provides a novel die-to-die interconnect design with improved cost efficiency and performance. Due to the presence of a back-side (B / S) process, power delivery in a system-on-integrated-chips (SoIC) architecture can be implemented using via towers. These via towers can be formed during the same process as the back-side (B / S) interconnect and / or front-side interconnect, thus eliminating the need for additional through-silicon via (TSV) processes. The via towers according to this invention include multiple conductive plates and vias. The conductive plates and vias can have large dimensions and / or a large number, thereby forming low-resistance power rails. Therefore, integrating the fabrication of the via towers into existing processes is cost-effective. Thus, the via towers according to this invention provide low-resistance power rail connections from the back side of the bottom die through the entire wafer to the top die and other dies.

[0115] Figure 1 This is a schematic cross-sectional view of a three-dimensional integrated circuit (3DIC) structure 100 according to some embodiments of the present disclosure. The 3DIC structure 100 includes two wafer layers, namely, a bottom wafer layer 102 and a top wafer layer 104. It should be noted that the number of wafer layers is not limited. Additional wafer layers may be added depending on the system design.

[0116] The top wafer layer 104 and the bottom wafer layer 102 are vertically bonded together to form a 3DIC structure 100. Other structures may be included, such as microbumps, molding regions, dummy regions, adhesive layers, heat sinks, interconnects, ball grid array (BGA) connectors, silicon interposers, and other components or structural elements. In some embodiments, the 3DIC structure 100 may include peripheral structures (not shown) to provide mechanical support and / or thermal conduction for heat dissipation. By way of example and not limitation, the top wafer layer 104 may include one or more microprocessors or CPUs, while the bottom wafer layer 102 may include one or more memory wafers, such as SRAM wafers, DRAM wafers, MRAM wafers, other types of memory wafers, or combinations thereof.

[0117] The top wafer layer 104 may include one or more device layers 140 formed on and above the semiconductor substrate 144, and interconnect structures 142 disposed on the device layers 140. The interconnect structures 142 include wires and vias formed in a dielectric layer. The wires and vias form communication paths and power supply paths to the semiconductor devices in the device layer 140.

[0118] The bottom wafer layer 102 may include one or more device layers 120, a first interconnect structure 122 disposed on a first side of the device layer 120, and a second interconnect structure 124 disposed on a second side of the device layer 120. In some embodiments, the first interconnect structure 122 is formed on the front side of the device layer 120 and has conductive vias forming communication paths for semiconductor devices in the device layer 120. The second interconnect structure 124 is formed on the back side of the device layer 120. The second interconnect structure 124 may include a back-side power network configured to supply power to semiconductor devices in the device layer 120.

[0119] Top wafer layer 104 and bottom wafer layer 102 are vertically stacked and bonded together, with interconnect structures 142 and 122 facing each other. Top wafer layer 104 and bottom wafer layer 102 can be bonded using suitable bonding techniques, such as hybrid bonding, fusion bonding, anodic bonding, direct bonding, room temperature bonding, pressure bonding, and / or combinations thereof. Figure 1 In the illustrated example, the top wafer layer 104 and the bottom wafer layer 102 are bonded together via a bonding film 126 and a bonding film 146. In some embodiments, bonding pad features 128 are formed in the bonding film 126, and at least a portion of the bonding pad features 128 are connected to conductive features in the interconnect structure 122 of the bottom wafer layer 102. Bonding pad features 148 are disposed in the bonding film 146, and at least a portion of the bonding pad features 148 are connected to conductive features in the interconnect structure 142 of the top wafer layer 104. In some embodiments, some or all of the bonding pad features 128 and 148 are aligned and bonded together to establish communication between the top wafer layer 104 and the bottom wafer layer 102. Each pair of bonding pad features 128, 148 forms an inter-chip communication path 152. As described below, the inter-chip communication path 152 formed by the bonding pad features 128, 148 can create inter-chip communication for signal or power supply.

[0120] According to some embodiments of this disclosure, one or more through-hole towers can be formed through a wafer layer to provide power to other wafer layers in a vertical wafer stack or 3DIC. Figure 1 In one example, one or more via towers 130 are formed in the bottom wafer layer 102, operable to connect power to the top wafer layer 104. In some embodiments, power supply 106 is configured to be electrically connected to the top wafer layer 104 via the via towers 130 in the bottom wafer layer 102.

[0121] The number and distribution of via towers 130 can be varied depending on the circuit design. In some embodiments, via towers 130 may be located in the sealing ring region of a die in the bottom wafer layer 102. In other embodiments, via towers 130 may be distributed between semiconductor devices in the bottom wafer layer 102. In some embodiments, the bottom wafer layer 102 may include one via tower 130 leading to a power source 106 and to a top wafer layer 104. The conductive plates and vias in the via tower 130 may have a relatively large cross-sectional area in the xy plane, thereby achieving low resistance. In other embodiments, the bottom wafer layer 102 may include two or more via towers 130. In some embodiments, because two or more via towers 130 cumulatively form a large cross-sectional area for current flow, two or more via towers 130 may be connected in parallel between the same power source and wafer layer, thereby reducing IR drop.

[0122] The through-hole tower 130 is formed of vertically stacked conductive plates and vias formed in the dielectric layers of the device layer 120 and interconnect structures 122, 124. Each through-hole tower 130 includes alternating layers of conductive plates and vias stacked together. The fabrication of the conductive plates and vias is integrated with the fabrication of the device layer 120 and interconnect structures 122, 124. The materials of the conductive plates and vias of the through-hole tower 130 can be Cu, Ru, W, Ti, Al, Co, Mo, Ir, Rh, C, Ni, Sc, Nb, Ta, Si, or combinations thereof. The materials of the conductive plates and vias can vary in different layers depending on the process flow. For example, some portions of the through-hole tower 130 can be formed of copper plates and vias, while other portions of the through-hole tower can include tungsten or aluminum.

[0123] like Figure 1 As shown, the via 130 includes a back-side stack 132 disposed in the back-side interconnect structure 124, an intermediate stack 134 disposed in the device layer 120, and a front-side stack 136 disposed in the front-side interconnect structure 122. The back-side stack 132, the intermediate stack 134, and the front-side stack 136 are vertically stacked to form a conductive pillar through the bottom wafer layer 102, thereby allowing electrical connectivity.

[0124] The back-side stack 132 includes conductive plates and vias formed in the dielectric material layer of the back-side interconnect structure 124. The front-side stack 136 includes conductive plates and vias formed in the dielectric material layer of the front-side interconnect structure 122. In some embodiments, the materials of the front-side stack 136 and the back-side stack 132 include the same materials as those in the interconnect structure, such as copper.

[0125] Intermediate stack 134 may include one or more conductive plates and / or vias formed through device layer 120. In some embodiments, intermediate stack 134 includes conductive plates and vias formed during the formation of source / drain contacts and gate contacts. The conductive material used for intermediate stack 134 may be the same as that used for source / drain contacts and gate contacts, such as tungsten. In other embodiments, intermediate stack 134 may include conductive features formed during back-side processing. The conductive material used for intermediate stack 134 may be the same as that used for back-side interconnect structures, such as copper.

[0126] In some embodiments, the through-hole tower 130 includes both a front-side stack 136 and a back-side stack 132. In other embodiments, one of the back-side stack 132 and the front-side stack 136 may be omitted, and the through-hole tower 130 may be connected to a power supply via a power delivering network (PDN) formed on the front or back side. For example, the through-hole tower 130 may include a front-side stack 136 and a middle stack 134, and the back-side stack 132 may be omitted, and the through-hole tower 130 may be connected to a power supply via a back-side PDN or a back-side power rail.

[0127] During operation, power supply 106 is connected to the bottom wafer layer 102 via bonding pads 160. Bonding pads 160 are electrically connected to via towers 130 and back-side interconnect structure 124. In some embodiments, power supply 106 is connected to the device layer 120 of the bottom wafer layer 102 via a flow path 154, which may include one or more bonding pads 160 and conductive features in the back-side interconnect structure 124. Power supply 106 is connected to the device layer 140 of the top wafer layer 104 via a communication path 156, which may include bonding pads 160, via towers 130 through the bottom wafer layer 102, bonding pad features 128, bonding pad features 148, and conductive features in the interconnect structure 142 of the top wafer layer 104. In some embodiments, interconnect structure 142 may include via towers 150 formed in interconnect structure 142, similar to the front stack 136 of via towers 130.

[0128] Figure 2A This is a schematic cross-sectional view of an integrated circuit wafer 200 according to some embodiments of the present disclosure. The integrated circuit wafer 200 can be used in a 3DIC package. The integrated circuit wafer 200 includes one or more through-hole towers 230 configured to provide power to one or more wafers stacked perpendicularly to the integrated circuit wafer 200. For example, the integrated circuit wafer 200 can be used as... Figure 1 The bottom wafer layer 102 in the 3DIC structure 100.

[0129] The integrated circuit wafer 200 includes a device layer 220, a front-side interconnect structure 222 disposed on the front side of the device layer 220, and a back-side power delivery network (PDN) 224 disposed on the back side of the device layer 220. The device layer 220 may include a plurality of semiconductor devices 204 formed on and from a semiconductor substrate. The semiconductor devices 204 may be fabricated on and from the semiconductor substrate using various semiconductor processes, such as deposition, patterning, etching, and doping of various thin films on the semiconductor substrate. Front-side contact features 206 and back-side contact features 208 are formed above and below the semiconductor devices 204, respectively, to enable signal communication with and provide signal communication and / or power to the semiconductor devices 204. The front-side contact features 206 and back-side contact features 208 are disposed in a dielectric material 202. The dielectric material 202 may include one or more layers deposited during manufacturing.

[0130] Semiconductor device 204 may be a transistor, diode, imaging sensor, resistor, capacitor, inductor, memory cell, combination thereof, and / or other suitable device. In some embodiments, semiconductor device 204 may be a transistor, such as a FinFET (Fin Field-Effect Transistor) and a nanostructure FET having one or more channels covered by a gate electrode layer. Front contact feature 206 may include source / drain contact features and gate contact features. Back contact feature 208 may include source / drain contact features and / or gate contact features.

[0131] A front-side interconnect structure 222 is formed on the device layer 220. The interconnect structure 222 includes an intermetal dielectric (IMD) layer 210, which may be multiple interlayer dielectric (ILD) layers or intermetal dielectric (IMD) layers 210. m Conductors 212 and conductive vias 214 are embedded in the IMD layer 210. Conductors 212 and conductive vias 214 form electrical paths connected to the semiconductor device 204. Interconnect structures 222 can be formed layer-by-layer using a metallization process, such as a damascene process, to embed conductors 212. m and conductive via 214 m The corresponding IMD layer 210 is embedded in the layer. m In the middle. For example Figure 2A As shown, the interconnect structure 222 may include IMD layers 2100, 2101, ..., 210 having wires 212 and conductive vias 214. mIn some embodiments, as the dimensions of the wire 212 and the conductive via 214 increase, the IMD layers 2100, 2101, ..., 210... m It can have an increased thickness T m For example, the wires 212 and conductive vias 214 are denser and smaller in layers closer to device layer 220, and sparser and larger in layers farther from device layer 220. In some embodiments, each IMD layer 2100, 2101, ..., 210 m The thickness along the z-axis ranges from approximately 50 angstroms to approximately 500 angstroms.

[0132] The IMD layer 210 may include an insulating material, including oxygen-containing materials such as silicon oxide or fluorine-doped silicate glass (FSG); nitrogen-containing materials such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; low-k dielectric materials, such as materials with a k-value lower than that of silicon oxide; or any suitable dielectric material. In some embodiments, the IMD layer 210 includes silicon oxide. The IMD layer 210 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, or other suitable processes. The conductive wires 212 and the conductive vias 214 may each include a conductive material, such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, alloys thereof, or other suitable materials. The conductive wires 212 and the conductive vias 214 may be formed by physical vapor deposition (PVD), CVD, ALD, or other suitable processes.

[0133] The back-side power delivery network (PDN) 224 includes one or more layers of conductors 244 and conductive vias 242 formed in one or more back-side dielectric layers 240. The conductors 244 form a power grid configured to provide an electrical connection between a power source and a semiconductor device 204. In some embodiments, the power grid may be electrically connected to the same voltage level as the integrated circuit power supply lines, such as V0. ss (e.g., ground voltage reference), or V DD (e.g., power supply voltage reference). The grid lines may be formed of conductive materials, such as copper, aluminum, cobalt, tungsten, metal silicides, highly conductive tantalum nitride, any suitable conductive material, and / or combinations thereof.

[0134] The integrated circuit wafer 200 also includes one or more through-hole towers 230 configured to provide electrical connections for power lines. The number and distribution of the through-hole towers 230 may vary depending on the circuit design. In some embodiments, the through-hole towers 230 may be disposed in a sealing ring region surrounding the semiconductor device 204. In other embodiments, the through-hole towers 230 may be distributed between the semiconductor devices 204.

[0135] In some embodiments, each through-hole tower 230 includes a front stack 232 formed in the front interconnect structure 222 and an intermediate stack 236 formed in the device layer 220. In some embodiments, the through-hole tower 230 includes conductive features formed and stacked along a central axis 231. During operation, the through-hole tower 230 is connected to a power source via a back-side power delivery network (PDN) 224 to provide an electrical communication path along the central axis 231.

[0136] like Figure 2A As shown, the front stack 232 includes conductive plates 252 and via bars 254 alternately formed in the IMD layer 210. Specifically, the front stack 232 includes components formed in the IMD layer 210. m Multiple pairs of conductive plates 2521, ..., 252 in m and through-hole strips 2541, ..., 254 m Conductive plate 252 m and through hole strip 254 m With the corresponding IMD layer 210 m wire 212 m and conductive via 214 m Simultaneous manufacturing. Specifically, conductive plate 252 m and wire 212 m Aligned on the same vertical plane along the z-direction, and through-hole strip 254 m and conductive via 214 m Aligned on the same vertical plane along the z-direction. In some embodiments, conductive plate 252 m Larger than 254 through-hole strip m To be suitable for manufacturing the corresponding wire 212 m and conductive via 214 m The inlay process.

[0137] Figure 2B It is along Figure 2A A partial cross-sectional plan view of the integrated circuit wafer 200 of line 2B-2B. (See attached image.) Figure 2B As shown, conductive plate 252 m It has a rectangular shape. Conductive plate 252 m It has a width W along the x-direction. 252 and the length L along the y direction 252In some embodiments, the width W 252 Within the range of approximately 0.1 micrometers to approximately 500 micrometers, and with a length L 252 The range is between approximately 0.1 micrometers and approximately 500 micrometers. Through-hole strip 254 m It has a rectangular shape. Through-hole strip 254 m It has a width W along the x-direction. 254 and the length L along the y direction 254 In some embodiments, the width W 254 Within the range of approximately 0.008 micrometers and approximately 3 micrometers, and with a length L 254 The range is between approximately 0.1 micrometers and approximately 500 micrometers.

[0138] although Figure 2B Only one via strip 254 is shown, but two or more via strips 254 may be included to connect conductive plates 252 between adjacent layers. For example, depending on the location of the IMD layers and the lithography technique used in manufacturing, two or more via strips 254 may be arranged along the y-direction between conductive plates 252.

[0139] Despite conductive plate 252 m It is shown as having a rectangular shape, but according to the circuit layout, conductive plate 252 m It can be any suitable shape or combination of shapes. For example, conductive plate 252 m It can be a circle, triangle, oval, hexagon, or any suitable shape.

[0140] like Figure 2A As shown, each pair of conductive plates has 252 m and through hole strip 254 m It has a T-shaped cross-section. The height of the T-shaped cross-section corresponds to the corresponding IMD layer 210. m Thickness T m In some embodiments, each pair of conductive plates 252 m and through hole strip 254 m The height ranges from approximately 0.01 μm to approximately 6 μm. The height of the conductive plate 252 and the through-hole strip 254 extends from the bottom IMD layer 2101 to the top IMD layer 210. m Increase.

[0141] The conductive plate 252 and the via strip 254 are formed simultaneously with the conductive wires 212 and conductive vias 214 in the corresponding IMD layer 210 and are made of the same material. For example, the conductive plate 252 and the via strip 254 may each comprise a conductive material, such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al and their alloys, or other suitable materials. The conductive plate 252 and the via strip 254 may be formed by physical vapor deposition (PVD), CVD, ALD or other suitable processes.

[0142] The intermediate stack 236 may include one or more conductive plates and / or via strips formed through the device layer 220. In some embodiments, the intermediate stack 236 includes a via strip 262 and a conductive plate 264. The via strip 262 may be formed through the device layer 220 and contact the bottommost conductive plate 252 of the front stack 232. The conductive plate 264 is disposed below the device layer 220 and connected to the via strip 262. In some embodiments, the conductive plate 264 and the via strip 262 may be formed together during a back-side process. In some embodiments, the via strip 262 may have a rectangular shape similar to the via strip 254. The conductive plate 264 may have a rectangular shape similar to the conductive plate 252. In some embodiments, the via strip 262 and the conductive plate 264 may be formed of a conductive material, such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, alloys thereof, or other suitable materials. The through-hole strip 262 and the conductive plate 264 can be formed by physical vapor deposition (PVD), CVD, ALD or other suitable processes.

[0143] In some embodiments, the through-hole tower 230 may include a barrier layer and / or lining surrounding the conductive features of the through-hole tower 230 (e.g., through-hole strips 262, 254 and conductive plates 252, 264). Figure 2C yes Figure 2A A schematic enlarged view of the through-hole tower 230 in the rectangular region 2C. Figure 2C A barrier layer 256 and a liner 258 are shown disposed between the conductive feature and the surrounding dielectric layer.

[0144] The barrier layer 256 may be formed of Ta, TaN, Ti, Co, Ru, Nb, W, Al, Mo, Ir, and combinations thereof. The barrier layer 256 may be formed using suitable fabrication techniques, such as ALD, plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), and / or similar techniques. In some embodiments, the barrier layer 256 may be formed with a thickness ranging from about 10 angstroms to about 100 angstroms.

[0145] The substrate 258 can be formed of a suitable dielectric material, such as tetraethoxysilane (TEOS), silicon nitride, oxides, silicon oxynitride, low dielectric constant (K) dielectric materials, high dielectric constant (K) dielectric materials, and / or the like. The substrate 258 can be formed using a suitable manufacturing process (e.g., PECVD), but other suitable processes (e.g., PVD, heat treatment, etc.) can also be used alternatively. In some embodiments, the substrate 258 can be formed to a thickness ranging from about 10 angstroms to about 100 angstroms.

[0146] Figure 3A This is a schematic cross-sectional view of an integrated circuit wafer 200a according to some embodiments of the present disclosure. The integrated circuit wafer 200a is similar to the integrated circuit wafer 200, except that the integrated circuit wafer 200a includes conductive plates 252 composed of multiple layers. m Outside of the through-hole tower 230a stacked with the conductive through-hole 254a array. Figure 3B It is along Figure 3A A schematic top view of the integrated circuit chip 200a with line 3B-3B in the figure. Figure 3B Details of an array of through-hole 254a according to some embodiments of the present disclosure are schematically shown.

[0147] like Figures 3A to 3B As shown, conductive via 254a m The array is formed on the conductive plate 252 m Connected IMD layer 210 m According to design rules, conductive vias 254a can be arranged in an array having dimensions and spacing suitable for conductive vias 214 in interconnect structure 222. Conductive vias 254a m It can have a width W along the x-direction. 254a and the length L along the y direction 254 a (or diameter). Depends on IMD layer 210 m Conductive via 254a mPosition, width W 254a、 Length L 254 a (or diameter) is in the range of approximately 0.008 micrometers to approximately 3 micrometers.

[0148] According to IMD layer 210 m The location, number, and size of conductive vias 254a in each array can vary. In some embodiments, different IMD layers 210 m Conductive via 254a m The arrays can have different diameters and numbers, but have essentially the same cumulative cross-sectional area. For example, IMD layer 210 located in the lower layers... m The conductive vias 254a (i.e., those in the layer closest to device layer 220) can have smaller diameters but are more numerous, while those in the higher IMD layer 210... m The conductive vias 254a (i.e., the layers away from device layer 220) can have a large diameter but are arranged in small numbers.

[0149] Figure 4 This is a schematic cross-sectional view of an integrated circuit wafer 200b according to some embodiments of the present disclosure. The integrated circuit wafer 200b is similar to the integrated circuit wafer 200, except that the integrated circuit wafer 200b includes a via tower 230b, which has an intermediate stack 236 formed during the front-end-of-line (FEOL) and middle-end-of-line (MEOL) processes, instead of conductive vias formed during the back-end-of-line (BEOL) processes as in the integrated circuit wafer 200.

[0150] In some embodiments, the intermediate stack 236b of the through-hole tower 230b includes a front through-hole strip 262b and a back through-hole strip 264b formed along a central axis 231. The front through-hole strip 262b is formed during a FEOL / MEOL process performed on the front side, for example, simultaneously with the front contact feature 206 in the device layer 220. The front through-hole strip 262b may be formed of the same material as the front contact feature 206. In some embodiments, the front through-hole strip 262b may be formed of one or more conductive materials, such as tungsten, cobalt, or other materials suitable for use with the front contact feature 206. After the front through-hole strip 262b is formed, a front stack 232 in contact with the front through-hole strip 262b is formed thereon.

[0151] The back-side via strip 264b is formed during the FEOL / MEOL process performed on the back side, for example, simultaneously with the back-side contact feature 208 in device layer 220. The back-side via strip 264b may be formed of the same material as the back-side contact feature 208. In some embodiments, the back-side via strip 264b may be formed of one or more conductive materials, such as tungsten, cobalt, or other materials suitable for the back-side contact feature 208. The back-side via strip 264b contacts the front-side via strip 262b, forming an electrical connection through device layer 220. After the back-side via strip 264b is formed, a back-side power delivery network (PDN) 224 is then formed in contact with the back-side via strip 264b to connect the via tower 230b to a power source.

[0152] Figure 5 This is a schematic cross-sectional view of an integrated circuit wafer 200c according to some embodiments of the present disclosure. The integrated circuit wafer 200c is similar to integrated circuit wafers 200a and 200b, except that the integrated circuit wafer 200c includes a via tower 230c, which has an array of vias passing through the front interconnect structure 222 and the device layer 220.

[0153] The through-hole tower 230c includes a front stack 232c and an intermediate stack 236c. The front stack 232c includes multiple layers of conductive plates 252. c and via array 254c. In some embodiments, front stack 232c is substantially similar to front stack 232a shown in figures 3A to 3C above.

[0154] In some embodiments, the intermediate stack 236c of the through-hole tower 230c includes a front-side through-hole array 262c and a back-side through-hole array 264c. The front-side through-hole array 262c is formed during a FEOL / MEOL process performed on the front side, for example, simultaneously with the front-side contact feature 206 of the device layer 220. The front-side through-hole array 262c may be formed of the same material as the front-side contact feature 206.

[0155] The size and number of front-side vias 262c can be selected based on the size and density of the front-side contact features 206. According to design rules, the array of front-side vias 262c can be arranged with a spacing suitable for the size and arrangement of the front-side contact features 206. The front-side vias 262c can have a diameter R in the range of approximately 0.005 micrometers to approximately 0.05 micrometers. 262c In some embodiments, the front via array 262c may be formed of one or more conductive materials, such as tungsten, cobalt, or other materials suitable for use as the front contact feature 206. After forming the front via array 262c, a front stack 232 in contact with the front via array 262c is formed thereon.

[0156] The back-side via array 264c is formed during the FEOL / MEOL process performed on the back side, for example, simultaneously with the back-side contact feature 208 in device layer 220. The back-side via array 264c may be formed of the same material as the back-side contact feature 208. In some embodiments, the back-side via array 264c may be formed of one or more conductive materials, such as tungsten, cobalt, or other materials suitable for the back-side contact feature 208.

[0157] The size and number of back-side vias 264c can be selected based on the size and density of the back-side contact features 208. According to design rules, the array of back-side vias 264c can be arranged with a spacing suitable for the size and arrangement of the back-side contact features 208. The back-side vias 264c can have a diameter R in the range of approximately 0.005 micrometers to approximately 0.05 micrometers. 264c The array of back vias 264c is aligned with the array of front vias 262c to form an array of parallel electrical connections passing through device layer 220. After the array of back vias 264c is formed, a back power transmission network (PDN) 224 is formed in contact with the array of back vias 264c to connect the via tower 230c to the power supply.

[0158] Figure 6A This is a schematic cross-sectional view of an integrated circuit wafer 200d according to some embodiments of the present disclosure. The integrated circuit wafer 200d is similar to the integrated circuit wafer 200c, except that the integrated circuit wafer 200d includes a via tower 230d, which has a via network 236d formed through the device layer 220. Figure 6B It is along Figure 6A A schematic partial top view of the integrated circuit chip 200d of line 6B-6B. Figure 6B A top view of the via network 236d is shown. Figure 6C yes Figure 6A A partially enlarged cross-sectional view of the integrated circuit wafer 200d in the rectangular region 6C. Figure 6C The vertical arrangement of the via network 236d is shown.

[0159] The via network 236d may include a front via strip 262d, a back via strip 264d, and an intermediate via strip 266d. In some embodiments, the via network 236d includes multilayer via strips integrated with the layout of the semiconductor device 204. For example, the front via strip 262d may be formed on the same layer as the gate contact of the transistor in the semiconductor device 204, the intermediate via strip 266d may be formed on the same layer as the front source / drain contact of the transistor in the semiconductor device 204, and the back via strip 264d may be formed on the same layer as the back source / drain contact of the transistor in the semiconductor device 204.

[0160] The front through-hole strip 262d contacts the front stack 232 of the through-hole tower 230d. The back through-hole strip 264d contacts the back power transmission network 224. In some embodiments, the front through-hole strip 262d and the back through-hole strip 264d may include one or more conductors along a first direction (e.g., the x-direction), while the intermediate through-hole strip 266d may include one or more conductors along a second direction perpendicular to the first direction (e.g., the y-direction).

[0161] In some embodiments, the pitch of the via network 236d can be selected based on the pitch of the semiconductor device 204 in the device layer 220, thus conforming to design rules and also allowing via towers 230d to be formed in the device region of the integrated circuit wafer 200d.

[0162] In some embodiments, such as Figure 6B As shown, the front through-hole strip 262d and the back through-hole strip 264d have the same pitch P along the y-direction. 264 / P 262 This aligns the front through-hole strip 262d and the back through-hole strip 264d with each other in the y-direction. In some embodiments, the front through-hole strip 262d and the back through-hole strip 264d may be arranged parallel to the semiconductor fin 268, wherein the semiconductor device 204 is formed along the semiconductor fin 268. In some embodiments, the pitch P 264 / P 262 The pitch can be the same as that of the semiconductor fin 268 along the y-direction. In some embodiments, the pitch P 264 / P 262 The width can be in the range of approximately 50 nm to approximately 300 nm. In some embodiments, the front via strip 262d and the back via strip 264d can have a width W along the y-direction in the range of approximately 10 nm to approximately 250 nm. 264 / W 262 In some embodiments, the semiconductor fin 268 may be selectively disposed between the front via strip 262d and the back via strip 264d. In some embodiments, the semiconductor fin 268 may have a width W along the y-direction in the range of about 2 nm and about 100 nm. 268 .

[0163] The intermediate layer through-hole 266d is formed perpendicular to the front through-hole strip 262d and the back through-hole strip 264d. The intermediate layer through-hole 266d is formed along the x-direction at a pitch P. 266 Arrangement. In some embodiments, the pitch P 266 The pitch can be similar to the gate pitch of semiconductor device 204. In some embodiments, the pitch P... 266It can be in the range of approximately 20 nm to approximately 300 nm. In some embodiments, the intermediate layer via 266d can have a width W along the x-direction in the range of approximately 10 nm to approximately 250 nm. 266 .

[0164] The via network 236d can be manufactured during existing manufacturing processes without adding any additional steps. In some embodiments, the front-side via strip 262d and the intermediate-layer via 266d are formed during a FEOL / MEOL process performed on the front side, for example, simultaneously with the front-side contact feature 206 in device layer 220. The front-side via strip 262d and the intermediate-layer via 266d can be formed of the same material as the front-side contact feature 206. The back-side via strip 264d is formed during a FEOL / MEOL process performed on the back side, for example, simultaneously with the back-side contact feature 208 in device layer 220. The back-side via strip 264d can be formed of the same material as the back-side contact feature 208 in device layer 200.

[0165] Figure 7 This is a flowchart of a method 300 for forming an integrated circuit wafer with through-hole towers according to some embodiments of the present disclosure. Specifically, method 300 forms an integrated circuit wafer having through-hole towers used in 3DIC packages. Method 300 can be used to manufacture integrated circuit wafers 200, 200a, 200b, 200c, 200d and bottom wafer layer 102 as described above. Figures 8A to 8F The illustration schematically shows various processing stages during the manufacture of an integrated circuit wafer according to some embodiments of the present disclosure.

[0166] In operation 302 of method 300, a front-end (FEOL) process sequence is executed to fabricate a plurality of semiconductor devices 204 on the front side of semiconductor substrate 201, such as... Figure 8A As shown. Figure 8A This is a schematic perspective view of the integrated circuit chip 200d after operation 302.

[0167] A semiconductor substrate 201 is provided for forming an integrated circuit wafer 200d thereon. The semiconductor substrate 201 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Depending on the circuit design, the semiconductor substrate 201 may include various doping configurations.

[0168] In some embodiments, a plurality of semiconductor devices 204 are formed on and by a semiconductor substrate 201. The semiconductor devices 204 may be transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices. In some embodiments, the semiconductor devices 204 may be transistors, such as fin field-effect transistors (FinFETs) and nanostructure FETs having one or more channels covered by a gate electrode layer.

[0169] In some embodiments, the semiconductor device 204 may include a transistor having source / drain regions 204s / d and a gate structure 204g formed over a channel region between the source / drain regions 204s / d. In some embodiments, the interlayer dielectric (ILD) layer 204 ILD It is formed on top of a transistor.

[0170] In operation 304, a mid-stage (MEOL) process is performed to form the contact features of the transistor, and layers of the through-hole tower according to embodiments of the present invention are selectively formed, such as... Figure 8B As shown.

[0171] According to the circuit design, a structure is formed that passes through the ILD layer 204. ILD The contact features (e.g., conductive vias) are used to provide electrical communication to the transistor. For example, the front source / drain contact 204md and the gate contact 204vb can be formed during operation 304. Alternatively, the layer of the via tower according to embodiments of the present invention can be formed simultaneously with the front source / drain contact 204md and the gate contact 204vb.

[0172] In some embodiments, one or more intermediate layer via strips 266d may be patterned and formed together with front-side source / drain contacts 204md, and one or more front-side via strips 262d may be patterned and formed together with gate contacts 204vb. Alternatively, it may be manufactured in operation 304. Figure 4 The front through-hole strip 262b or Figure 5 The front through hole 262c.

[0173] In operation 306, a back-end (BEOL) process is performed to fabricate a front-side interconnect structure 222 on top of the semiconductor device 204, and to form layers of via towers in each IMD layer 210, such as... Figure 8C As shown.

[0174] The front interconnect structure 222 includes multiple IMD layers 210 with embedded conductors 212 and conductive vias 214. The IMD layers 210 are formed layer by layer using a suitable process. Conductive plates 252 and via strips 254 (or vias 254a) can be formed together with the conductors 212 and conductive vias 214 in each IMD layer 210. The conductive layers 252 and via strips 254 can be integrated with the patterned layout of the IMD layers without additional cost. After operation 306, the front stack 232 and the intermediate stack 236 of the via tower 230 are formed.

[0175] In operation 308 of method 300, the semiconductor substrate 201 is flipped and a back-side thinning process is performed, such as... Figure 8D As shown. In some embodiments, a carrier wafer (not shown) may be bonded to the front side of the integrated circuit wafer 200d, and the semiconductor substrate 201 may be flipped so that the back side of the semiconductor substrate 201 faces upward for back-side processing. Back-side polishing is performed to thin the semiconductor substrate 201. For example, back-side polishing, such as a chemical-mechanical polishing (CMP) process, may be performed to expose alignment features (e.g., buried source / drain features) for forming back-side contacts.

[0176] In operation 310 of method 300, back-side contact features are formed (e.g., back-side source / drain contacts 204bmd), and the MEOL layer of the through-hole tower according to embodiments of the present invention is selectively formed, such as... Figure 8E As shown. In Figure 8E In this configuration, a back-side via strip 264d is added to the layout of the back-side source / drain contacts 204bmd for patterning and forming in the same process. Alternatively, other designs may be employed, such as... Figure 4 Back side through-hole strip 264b or Figure 5 The back-side through-hole is 264c.

[0177] In operation 312 of method 300, the back-side interconnect structure 224 is formed using the BEOL process, such as Figure 8F As shown. In some embodiments, the back-side interconnect structure 224 may be a back-side power delivery network (PDN) configured to deliver power to the semiconductor device 204 and through-hole towers 230 formed through the device layer 220 and the front-side interconnect structure 222. In other embodiments, alternately stacked conductive plates and conductive vias may be formed in the back-side interconnect structure 224 as part of the through-hole towers 230.

[0178] Figures 9A to 9EThe diagram schematically illustrates various processing stages during the manufacture of an integrated circuit wafer 200 according to some embodiments of the present disclosure. Specifically, method 300 can be used to manufacture the integrated circuit wafer 200.

[0179] Figure 9A The diagram schematically shows the integrated circuit chip 200 after operation 304. (As shown) Figure 9A As shown, the MEOL layer for the selective use of the through-hole tower region is omitted in operation 304. Figure 9B The integrated circuit chip 200 is schematically shown after operation 308. Figure 9C The integrated circuit chip 200 is schematically shown after operation 310. (As shown) Figure 9C As shown, the MEOL through-hole tower layer is omitted when performing operation 310.

[0180] In operation 312, an opening through the device layer 220 is formed from the back side of the semiconductor substrate 201 to expose the front stack 232. The opening is then filled to form a conductive via 262 and a conductive plate 264, as shown. Figure 9D As shown. After forming the conductive via 262 and the conductive plate 264, operation 312 continues to form the back-side interconnect structure 224, as shown. Figure 9E As shown.

[0181] Figure 10 This is a schematic cross-sectional view of a three-dimensional integrated circuit (3DIC) structure 100a according to some embodiments of the present disclosure. The 3DIC structure 100a is similar to the 3DIC structure 100, except that the 3DIC structure 100a includes an intermediate wafer layer 102m disposed between a top wafer layer 104 and a bottom wafer layer 102. According to embodiments of the present invention, the bottom wafer layer 102 and the intermediate wafer layer 102m may include through-hole towers for transmitting power. In some embodiments, the bottom wafer layer 102 and the intermediate wafer layer 102m may be selected from the aforementioned integrated circuit wafers 200, 200a, 200b, 200c, and 200d. Figure 10 As shown, the bottom wafer layer 102 includes one or more via towers 130a and 130b, and the middle wafer layer 102m includes one or more via towers 130m. The via towers 130a and 130b can be connected to provide power to the stacked wafer layers above through the bottom wafer layer 102.

[0182] An intermediate wafer layer 102m is stacked on a bottom wafer layer 102, forming an electrical path 152a between them. At least two electrical paths 152a are connected to vias 130a and 130b in the bottom wafer layer 102 to provide power to the intermediate wafer layer 102m through the bottom wafer layer 102. A top wafer layer 104 is bonded to the intermediate wafer layer 102m, forming an electrical path 152b between them. At least one electrical path 152b is connected to a via 130m to provide power from the intermediate wafer layer 102m to the top wafer layer 104. At least one via 130a in the bottom wafer layer 102 is aligned with a via 130m in the intermediate wafer layer 102m to form an electrical path 156a to provide power to the top wafer layer 104 through the bottom wafer layer 102 and the intermediate wafer layer 102m.

[0183] During operation, power supply 106 is connected to the bottom wafer layer 102 via bonding pad 160. Bonding pad 160 is electrically connected to via towers 130a and 130b. In some embodiments, bonding pad 160 is connected to a device layer 120 of the bottom wafer layer 102 via a flow path 154, which may include one or more bonding pads 160 and conductive features in the back-side interconnect structure of the bottom wafer layer 102. Power supply 106 is supplied to the intermediate wafer layer 102m via electrical path 156b, which includes a bonding pad 160, a via tower 130b, and an electrical path 152a connected to the via tower 130b. Power supply 106 is supplied to the top wafer layer 104 via electrical path 156a, which includes a bonding pad 160, a via tower 130a, an electrical path 152a connected to the via tower 130a, a via tower 130m, and an electrical path 152b connected to the via tower 130m.

[0184] This invention provides an integrated circuit die including through-hole towers formed by stacking conductive layers formed during the fabrication of semiconductor devices and interconnect structures within the integrated circuit die. The through-hole towers can replace through silicon vias (TSVs). The through-hole towers according to this disclosure reduce manufacturing costs because they are manufactured without additional processing steps (e.g., process steps for manufacturing TSVs). The through-hole towers can be integrated into circuit layouts to form low-resistance power rails, thereby improving performance.

[0185] It should be understood that not all advantages need to be discussed herein, and not all embodiments or examples need to have specific advantages, and other embodiments or examples may provide different advantages.

[0186] This disclosure relates to a semiconductor package in several embodiments. The semiconductor package includes a first integrated circuit wafer layer, which includes a device layer, a first interconnect structure, a second interconnect structure, and a via tower. The device layer includes a plurality of semiconductor devices. The first interconnect structure is disposed on a first side of the device layer, and the second interconnect structure is disposed on a second side of the device layer. The via tower is configured to provide electrical connections through the first interconnect structure, the device layer, and the second interconnect structure, wherein the via tower includes a stack of conductors through the device layer and at least one of the first and second interconnect structures. The semiconductor package further includes a second integrated circuit wafer layer bonded to the first integrated circuit wafer layer, wherein the via tower is electrically connected to the second integrated circuit wafer layer via bonding pad features.

[0187] In some embodiments, the via tower includes a first conductor stack and a second conductor stack, the first conductor stack (e.g., front stack 232 or 136) being disposed through a first interconnect structure, and the second conductor stack (e.g., intermediate stack 236 or 134) being disposed through a device layer, wherein the second conductor stack contacts the first conductor stack, and a bonding pad feature contacts the first conductor stack. In some embodiments, the second interconnect structure includes a back-side power delivery network. In some embodiments, the via tower further includes a third conductor stack (e.g., back stack 132) being disposed through the second interconnect structure, wherein the third conductor stack contacts the second conductor stack. In some embodiments, the second conductor stack includes a front conductor and a back conductor, the front conductor (e.g., front via strip 262b, front via 262c, or front via strip 262d) being disposed on a first side of the device layer, and the back conductor (e.g., back via strip 264b, back via 264c, or back via strip 264d) being disposed on a second side of the device layer. In some embodiments, the second conductor stack further includes an intermediate conductor (e.g., an intermediate layer via strip 266d) disposed between the front conductor and the back conductor, wherein the front conductor and the back conductor are wires along a first direction, and the intermediate conductor is a wire along a second direction.

[0188] This disclosure relates to an integrated circuit wafer in several embodiments. The integrated circuit wafer includes a device layer, a first interconnect structure, a second interconnect structure, and a via tower. The device layer includes a plurality of semiconductor devices, the first interconnect structure is disposed on a first side of the device layer, the second interconnect structure is disposed on a second side of the device layer, and the via tower is configured to provide electrical connections through the first interconnect structure, the device layer, and the second interconnect structure. The via tower includes a first conductor stack (e.g., a front stack 232 or 136) and a second conductor stack (e.g., an intermediate stack 236 or 134), wherein the first conductor stack is disposed through the first interconnect structure, the second conductor stack is disposed through the device layer, and the second conductor stack is in contact with the first conductor stack.

[0189] In some embodiments, the first interconnect structure includes a plurality of inter-metal dielectric layers (e.g., IMD layer 210), and the first conductor stack includes a plurality of embedded conductors in the inter-metal dielectric layers. In some embodiments, each of the embedded conductors includes a conductive plate (e.g., conductive plate 252) and a via strip (e.g., via strip 254) in contact with the conductive plate. In some embodiments, each of the embedded conductors includes a conductive plate (e.g., conductive plate 252) and an array of vias (e.g., an array of conductive vias 254a or an array of vias 254c) in contact with the conductive plate. In some embodiments, the via stack further includes a third conductor stack (e.g., a back-side stack 132) disposed through the second interconnect structure, wherein the third conductor stack contacts the second conductor stack. In some embodiments, the second interconnect structure includes a back-side power delivery network. In some embodiments, the second conductor stack includes a front conductor and a back conductor, the front conductor (e.g., front through-hole strip 262b, front through-hole 262c, or front through-hole strip 262d) being disposed on a first side of the device layer, and the back conductor (e.g., back through-hole strip 264b, back through-hole 264c, or back through-hole strip 264d) being disposed on a second side of the device layer. In some embodiments, the second conductor stack further includes an intermediate conductor (e.g., intermediate layer through-hole strip 266d) disposed between the front conductor and the back conductor, wherein the front conductor and the back conductor are wires along a first direction, and the intermediate conductor is a wire along a second direction.

[0190] This disclosure relates to several embodiments of a method for forming an integrated circuit wafer. The method includes forming a device layer comprising a plurality of semiconductor devices in and on a substrate. The method includes forming a first interconnect structure on a first side of the device layer, wherein the first interconnect structure includes a plurality of inter-metal dielectric layers and a first conductor stack (e.g., a front-side stack 232 or 136) passing through the first interconnect structure and embedded in the inter-metal dielectric layers. The method includes forming a back-side conductor (e.g., a back-side via strip 264b, a back-side via 264c, or a back-side via strip 264d) in the device layer from a second side of the device layer, wherein the back-side conductor is electrically connected to the first conductor stack. The method includes forming a second interconnect structure on the second side of the device layer, wherein the second interconnect structure includes a conductive path to the back-side conductor.

[0191] In some embodiments, the method further includes forming a front conductor (e.g., front via strip 262b, front via strip 262c, or front via strip 262d) in the device layer from a first side of the device layer, wherein a first conductor stack contacts the front conductor. In some embodiments, a back conductor is formed on top of and contacts the front conductor. In some embodiments, the method further includes forming an intermediate conductor (e.g., intermediate layer via strip 266d) in the device layer prior to forming the front conductor, wherein the intermediate conductor is a wire along a first direction, and the front conductor (e.g., front via strip 262d) and the back conductor (e.g., back via strip 264d) are wires along a second direction, and the intermediate conductor contacts the front conductor and the back conductor. In some embodiments, forming the intermediate conductor is performed simultaneously with forming the source / drain contacts of the semiconductor device, and forming the front conductor is performed simultaneously with forming the gate contacts of the semiconductor device. In some embodiments, the second interconnect structure includes a back-side power delivery network.

[0192] The foregoing has outlined the features of numerous embodiments to enable those skilled in the art to better understand the various embodiments of this disclosure. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments of this invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, and modifications can be made to the embodiments of this invention without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, characterized in that, include: A first integrated circuit wafer layer, comprising: A device layer containing multiple semiconductor devices; A first interconnect structure is disposed on a first side of the device layer; A second interconnect structure is disposed on a second side of the device layer; and A through-hole tower configured to provide electrical connections through the first interconnect structure, the device layer, and the second interconnect structure, wherein the through-hole tower includes a conductor stack formed through the device layer and at least one of the first interconnect structure and the second interconnect structure; and A second integrated circuit wafer layer is bonded to the first integrated circuit wafer layer, wherein the via tower is electrically connected to the second integrated circuit wafer layer via a bonding pad feature.

2. The semiconductor package as described in claim 1, characterized in that, The through-hole tower includes: A first conductor stack passes through the first interconnect structure; and A second conductor stack is disposed through the device layer, wherein the second conductor stack is in contact with the first conductor stack, and the bonding pad feature is in contact with the first conductor stack.

3. An integrated circuit chip, characterized in that, include: A device layer containing multiple semiconductor devices; A first interconnect structure is disposed on a first side of the device layer; A second interconnection structure is disposed on a second side of the device layer; as well as A through-hole tower configured to provide electrical connections through the first interconnect structure, the device layer, and the second interconnect structure, wherein the through-hole tower includes: A first conductor stack is disposed through the first interconnect structure; as well as A second conductor stack is disposed through the device layer, wherein the second conductor stack is in contact with the first conductor stack.

4. The integrated circuit chip as described in claim 3, characterized in that, The first interconnect structure includes multiple inter-metal dielectric layers, and the first conductor stack includes multiple embedded conductors in the multiple inter-metal dielectric layers.

5. The integrated circuit chip as described in claim 4, characterized in that, Each of the plurality of embedded conductors includes: A conductive plate; and A through-hole strip is in contact with the conductive plate.

6. The integrated circuit chip as described in claim 4, characterized in that, Each of the plurality of embedded conductors includes: A conductive plate; and An array of through holes is in contact with the conductive plate.

7. The integrated circuit chip as described in claim 3, characterized in that, The through-hole tower further includes: A third conductor stack passes through the second interconnect structure, wherein the third conductor stack is in contact with the second conductor stack.

8. The integrated circuit chip as described in claim 3, characterized in that, The second interconnect structure includes a back-side power delivery network.

9. The integrated circuit chip as described in claim 3, characterized in that, The second conductor stack includes: A front conductor is disposed on the first side of the device layer; and A back-side conductor is disposed on the second side of the device layer.

10. The integrated circuit wafer as described in claim 9, characterized in that, The second conductor stack further includes: An intermediate conductor is disposed between the front conductor and the back conductor, wherein the front conductor and the back conductor are wires along a first direction, and the intermediate conductor is a wire along a second direction.

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