Parallel circuit of alternating-current programmable power supply inverter

Abstract

The utility model discloses an alternating current programmable power supply inverter parallel circuit, which comprises a differential transceiver, a receiving circuit, an enabling circuit and an input circuit, a first optocoupler of the receiving circuit is connected with an input signal, and an output end of the receiving circuit is connected with a first triode and a second triode and then is connected to an R pin of the differential transceiver; a second optocoupler input end of the enable circuit is connected with an enable signal of the differential transceiver, and an output end of the enable circuit is connected with emitters of a third triode and a fourth triode; the input end of a third optocoupler of the input circuit is connected with a D pin of the differential transceiver, and the output end is connected with emitters of a fifth triode and a sixth triode. The circuit integrates start-stop signal synchronization, alarm signals, handshake synchronization signals and the like to ensure output phase synchronization, meets the requirement that the output characteristic of the whole machine is not influenced when a certain inverter breaks down, ensures the consistency of dynamic and static characteristics of the IGBT, and is better in current sharing characteristic of the IGBT.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronic control technology, in particular to an AC program-controlled power supply inverter parallel circuit. BACKGROUND

[0002] At present, in the field of power electronics, generally IGBT modules are used for inverter modules to realize high-power output. The IGBT module is designed in a double-tube package, and two IGBT modules are needed to form an H-bridge structure. Due to the large size of the high-current IGBT module, there are design difficulties in module design and heat dissipation under limited volume.

[0003] In a high-power application scenario, the more IGBTs are connected in parallel in an inverter, the more factors that affect the dynamic and static performance of the IGBTs are increased, which may cause uneven current between modules, and even cause a single module to be overloaded, thereby causing shutdown. Therefore, for a single inverter, whether static or dynamic characteristics, ensuring current sharing between modules is the key to normal operation of the inverter.

[0004] Since the drive module is separated from the drive part, there is a large interference for parallel connection of a high-power inverter, which easily affects the stability of the drive. SUMMARY

[0005] The utility model aims at providing an AC program-controlled power supply inverter parallel circuit, which can solve the above problems, and is achieved by the following technical scheme.

[0006] The AC program-controlled power supply inverter parallel circuit comprises a differential transceiver, a receiving circuit, an enabling circuit and an input circuit.

[0007] The receiving circuit comprises a first optocoupler, a first triode and a second triode. The first optocoupler input end inputs a signal, the first optocoupler output end is connected with the emitter of the first triode and the second triode, the collector of the first triode is connected with a high level, the collector of the second triode is grounded, and the base of the first triode and the second triode is connected to the R pin of the differential transceiver.

[0008] The enabling circuit comprises a second optocoupler, a third triode and a fourth triode. The second optocoupler input end is connected with a Master_Slave enabling signal, the Master_Slave enabling signal is connected with the DE pin of the differential transceiver, the second optocoupler output end is connected with the emitter of the third triode and the fourth triode, the collector of the third triode is connected with a high level, the collector of the fourth triode is grounded, and the base of the third triode and the fourth triode is connected with each other.

[0009] The input circuit comprises a third optocoupler, a fifth transistor and a sixth transistor, the input end of the third optocoupler is connected with the D pin of the differential transceiver, the output end of the third optocoupler is connected with the emitter of the fifth transistor and the sixth transistor, the collector of the fifth transistor is connected with a high level, the collector of the sixth transistor is grounded, and the bases of the fifth transistor and the sixth transistor are connected with each other.

[0010] The first transistor, the third transistor and the fifth transistor are NPN type transistors, and the second transistor, the fourth transistor and the sixth transistor are PNP type transistors.

[0011] Further, the system power supply circuit comprises an isolation power module U41 and a linear voltage stabilizing chip U42.

[0012] Further, the input signal of the receiving circuit is a Syn_clk_in synchronous input signal, the bases of the third transistor and the fourth transistor are connected with a Syn_clk_en synchronous enable signal, and the bases of the fifth transistor and the sixth transistor are connected with a Syn_clk_out synchronous output signal.

[0013] Further, the input signal of the receiving circuit is a HandleA_clk_in handshake input signal, and the bases of the fifth transistor and the sixth transistor are connected with a HandleA_clk_out handshake output signal.

[0014] Further, the input signal of the receiving circuit is a Rst_clk_in reset input signal, and the bases of the fifth transistor and the sixth transistor are connected with a Rst_clk_out reset output signal.

[0015] Further, the input signal of the receiving circuit is an Alarm_in alarm input signal, and the bases of the fifth transistor and the sixth transistor are connected with an Alarm_out alarm output signal.

[0016] Further, the input signal of the receiving circuit is a Wave_syn_in clock input signal, and the bases of the fifth transistor and the sixth transistor are connected with a Wave_syn_out clock output signal.

[0017] The utility model discloses the advantages are as follows: no longer adopt multiple module parallel mode, change to adopt multiple inverter parallel mode, improve the operation reliability of AC program control power supply.

[0018] The AC program control power supply inverter parallel has low drive power, high IGBT utilization, multiple AC program control power supply parallel output and the like advantages, and the single power supply is integrated with control, detection, protection circuit, and the whole inverter fault shutdown is not influenced by the failure of a inverter, and has very strong stability. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is the schematic diagram of synchronous work signal circuit of the utility model;

[0020] Figure 2 It is the schematic diagram of parallel machine handshaking circuit of the utility model;

[0021] Figure 3 It is the schematic diagram of parallel machine synchronous reset circuit of the utility model;

[0022] Figure 4 It is the schematic diagram of parallel machine start-stop circuit of the utility model;

[0023] Figure 5 It is the schematic diagram of parallel machine alarm circuit of the utility model;

[0024] Figure 6 It is the schematic diagram of clock synchronous signal circuit of the utility model;

[0025] Figure 7 It is the schematic diagram of system power supply circuit part of the utility model. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0027] The embodiment discloses an AC program-controlled power supply inverter parallel circuit, which comprises a differential transceiver, a receiving circuit, an enabling circuit, an input circuit and a system power supply circuit, please refer to Figure 1 .

[0028] The receiving circuit comprises a first optocoupler, a first triode and a second triode, the first optocoupler input end is connected with an input signal, the first optocoupler output end is connected with the emitter of the first triode and the second triode, the collector of the first triode is connected with a high level, the collector of the second triode is grounded, and the base of the first triode and the second triode is connected to the R pin of the differential transceiver;

[0029] The enabling circuit comprises a second optocoupler, a third triode and a fourth triode, the second optocoupler input end is connected with a Master_Slave enabling signal, the Master_Slave enabling signal is connected with the DE pin of the differential transceiver, the second optocoupler output end is connected with the emitter of the third triode and the fourth triode, the collector of the third triode is connected with a high level, the collector of the fourth triode is grounded, and the base of the third triode and the fourth triode is connected to each other;

[0030] The input circuit comprises a third optocoupler, a fifth transistor and a sixth transistor, the input end of the third optocoupler is connected with the D pin of the differential transceiver, the output end of the third optocoupler is connected with the emitter of the fifth transistor and the sixth transistor, the collector of the fifth transistor is connected with a high level, the collector of the sixth transistor is grounded, and the bases of the fifth transistor and the sixth transistor are connected with each other.

[0031] The first transistor, the third transistor and the fifth transistor are NPN type transistors, and the second transistor, the fourth transistor and the sixth transistor are PNP type transistors.

[0032] Please refer to Figure 7 The system power supply circuit comprises an isolation power module U41, a linear voltage stabilizing chip U42, capacitors C75, C77, C78, C79, C80, C81 and L1 and Z1, has the functions of decoupling and filter voltage stabilization, and can provide energy for the entire parallel machine circuit.

[0033] The above circuit can be applied as a synchronous working signal circuit, a parallel machine handshake circuit, a parallel machine synchronous reset circuit, a parallel machine start-stop circuit, a parallel machine alarm circuit, a clock synchronous signal circuit and a system power supply circuit.

[0034] Please refer to Figure 1 The master-slave inverter synchronous working signal is generated by the host, uses the RS485 output high-speed synchronous pulse signal, the host outputs the synchronous signal, and all slaves receive the synchronous signal. After the system is powered on, the host and the slave determine the Syn_clk_en level according to the setting. When the host Syn_clk_en is set to a high level, the Q31 third transistor is turned on, the U23 second optocoupler does not work, the 3 pin of the differential transceiver U2 (485 chip) is in a high level state, the 485 chip is in an automatic transceiving state, the host sends various commands through the Syn_clk_out high and low levels, transmits the commands to each slave through the U2, and the slave feeds back the received instructions to the host through the U2.

[0035] Please refer to Figure 2, handshake circuit is used for on-line voltage regulation and programmable function, to ensure that the master and slave machine change consistently, will not cause output loop current due to inconsistent changes. Handshake circuit also uses RS485 transmission, the host sends and receives, the slave only receives. When standby or start state, the host Handle_clk_out signal high-low level conversion, control Q35 third transistor and Q48 fourth transistor alternate conduction, U31 third optocoupler isolation signal, differential transceiver U8 sends the signal to the host transmission to each slave, slave to accept the command by U8 to control the first transistor Q8 and the second transistor Q21 alternate work to answer received data, here U8 3 pin control signal and U2 control signal consistent, both by Syn_clk_en level control, to ensure signal synchronization.

[0036] Please refer to Figure 3 , using RS485 transmission, the host sends and receives, the slave only receives. When the host count 63 will Rst_clk_out is low, count to 127 will Rst_clk_out is high; When the master and slave machine detects the rising edge of Rst_clk_in signal, the hard core internal synchronization signal counter is cleared, to ensure that the system is always in the same phase.

[0037] Please refer to Figure 4 , start-stop circuit for the start-stop of the whole machine. Also use RS485 transmission, the host sends and receives, the slave only receives. When the host detects the start button, the Start_stop_out is high when the count is not 0, the master-slave module detects the rising edge of Start_stop_in, and starts at the next zero point (when the count is 0), so as to realize the system starting from the same time point. Similarly, when the host detects the stop button, the Start_stop_out is immediately low, and the master-slave module detects the falling edge of START_STOP_IN and stops output immediately.

[0038] Please refer to Figure 5 , alarm circuit is used to transmit alarm signal. Also use RS485 transmission, the host and slave can send and receive. When the power is normal, Alarm_out is low, Alarm_in is high; When the power alarm, Alarm_out is high, Alarm_in is low. That is, the FPGA hard core detects the falling edge of Alarm_in, and makes the STOP signal low, so as to lock the PWM. At the same time, the soft core detects that the Alarm_in is low, controls the power alarm and stops output, the host polls the slave to determine the alarm machine and alarm code and displays.

[0039] Please refer to Figure 6The host product generates a wave_syn_out square wave signal to control the fifth transistor Q64 and the sixth transistor Q65 to alternately conduct, and data transmission is performed to each slave through the differential transceiver U13, and the slave sends a signal to the host through U13 to generate a wave_syn_in signal.

[0040] Finally, it should be noted that: the above only for the preferred embodiments of the present application, and not for limiting the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application, should be included in the scope of protection of the present application.

Claims

1. A parallel circuit of AC program-controlled power inverters, characterized in that, The receiving circuit comprises a first optocoupler, a first transistor and a second transistor. The receiving circuit comprises a first optocoupler, a first transistor and a second transistor. The enabling circuit comprises a second optocoupler, a third transistor and a fourth transistor. The input circuit comprises a third optocoupler, a fifth transistor and a sixth transistor. The first transistor, the third transistor and the fifth transistor are NPN transistors, and the second transistor, the fourth transistor and the sixth transistor are PNP transistors.

2. The parallel connection of ac program-controlled power supplies according to claim 1, characterized in that The system power supply circuit comprises an isolation power module U41 and a linear voltage stabilizing chip U42.

3. The parallel connection of ac program-controlled power supplies according to claim 1, characterized in that, The input signal of the receiving circuit is a Syn_clk_in synchronous input signal, the bases of the third transistor and the fourth transistor are connected to a Syn_clk_en synchronous enabling signal, and the bases of the fifth transistor and the sixth transistor are connected to a Syn_clk_out synchronous output signal.

4. The parallel connection of ac program-controlled power supplies according to claim 1, characterized in that, The input signal of the receiving circuit is a HandleA_clk_in handshake input signal, and the bases of the fifth transistor and the sixth transistor are connected to a HandleA_clk_out handshake output signal.

5. The parallel connection of ac program-controlled power supplies according to claim 1, characterized in that, The input signal of the receiving circuit is a Rst_clk_in reset input signal, and the bases of the fifth transistor and the sixth transistor are connected to a Rst_clk_out reset output signal.

6. The parallel connection of ac program-controlled power supplies according to claim 1, characterized in that, The input signal of the receiving circuit is an Alarm_in alarm input signal, and the bases of the fifth transistor and the sixth transistor are connected to an Alarm_out alarm output signal.

7. The parallel connection of ac program-controlled power supplies according to claim 1, characterized in that, The input signal of the receiving circuit is a Wave_syn_in clock input signal, and the bases of the fifth transistor and the sixth transistor are connected to a Wave_syn_out clock output signal.

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