Perovskite-crystalline silicon laminated cell

Abstract

The utility model discloses a perovskite-crystalline silicon laminated cell, which comprises a crystalline silicon cell, the crystalline silicon cell comprises a silicon substrate and a passivation contact structure arranged on the front surface of the silicon substrate, the passivation contact structure comprises a tunneling layer and a first electron transport layer which are sequentially laminated on the front surface of the silicon substrate, and the first electron transport layer is arranged on the front surface of the silicon substrate. The first electron transport layer is an intrinsic ZnO layer or a doped ZnO layer; and the perovskite cell is located on the first electron transport layer. According to the utility model, the intrinsic ZnO layer or the doped ZnO layer is used as the first electron transport layer to form a passivation contact structure of the crystalline silicon cell, and the perovskite cell is directly arranged on the first electron transport layer, so that the loss caused by parasitic light absorption is effectively reduced.

Description

TECHNICAL FIELD

[0001] The utility model belongs to solar technology field, and specifically relates to a perovskite-crystalline silicon laminated cell. BACKGROUND

[0002] The passivation contact technology is the key of the high-efficiency crystalline silicon cell technology, and the current commercial passivation contact technology mainly includes the silicon heterojunction (SHJ) cell and the tunneling oxide passivation contact (TOPCon) cell. Both of them adopt the doped silicon film to construct the passivation contact structure, wherein the passivation contact structure of the SHJ cell is composed of the intrinsic hydrogenated amorphous silicon (a-Si:H) superimposed with the doped a-Si:H, and the passivation contact structure of the TOPCon cell is composed of the tunneling oxide silicon (SiO2) superimposed with the doped polysilicon (poly).

[0003] With the further development of the solar technology, the requirement for the conversion efficiency of the solar cell is further improved. The perovskite-crystalline silicon laminated cell is formed by preparing the perovskite on the front surface of the crystalline silicon cell, so as to fully utilize the light of different wavelengths and improve the conversion efficiency of the solar cell. The perovskite-crystalline silicon laminated cell in the prior art usually adopts the transparent conductive metal oxide film (such as indium tin oxide ITO, zinc-doped indium oxide IZO, etc.) as the intermediate composite layer, or adopts the doped polysilicon or amorphous silicon film as the tunneling junction.

[0004] However, the parasitic light absorption of the silicon film in the SHJ cell and the TOPCon cell is large, which leads to the loss of the short-circuit current of the photovoltaic device, and the deposition process of the silicon film includes the plasma enhanced chemical vapor deposition (PECVD) process and the low pressure chemical vapor deposition (LPCVD) process, the equipment is expensive, and involves toxic and flammable gases (such as silane, phosphine and borane). At the same time, the intermediate composite layer material (ITO, IZO, etc.) of the perovskite-crystalline silicon laminated cell has large optical parasitic absorption, and contains the rare metal indium, so the cost is high. In addition, the ITO material and the IZO material have good lateral conductivity, which is easy to cause the electric leakage when preparing the large-area laminated cell, thereby limiting the application.

[0005] In addition, the doped polysilicon or amorphous silicon film tunneling junction used in the perovskite-crystalline silicon laminated cell in the prior art has large parasitic absorption, and the preparation cost is high. Moreover, in the perovskite-crystalline silicon laminated cell in the prior art, the passivation contact structure of the crystalline silicon cell and the intermediate composite layer are two independent structures, which need to be prepared respectively, and the preparation process is more complex.

[0006] Therefore, in view of the above technical problems, it is necessary to provide a perovskite-crystalline silicon laminated cell. UTILITY MODEL CONTENT

[0007] The utility model discloses a perovskite-crystalline silicon laminated cell which can effectively reduce the loss caused by parasitic light absorption.

[0008] In order to realize the above-mentioned purpose, the utility model provides a technical scheme as follows:

[0009] A perovskite-crystalline silicon laminated cell, the laminated cell comprises:

[0010] The crystalline silicon cell comprises a silicon substrate and a passivation contact structure on the front surface of the silicon substrate, the passivation contact structure comprises a tunneling layer and a first electron transport layer which are sequentially stacked on the front surface of the silicon substrate, and the first electron transport layer is an intrinsic ZnO layer or a doped ZnO layer.

[0011] The perovskite cell is located above the first electron transport layer.

[0012] In an embodiment, the doped ZnO layer is one or more of an aluminum-doped ZnO layer, a boron-doped ZnO layer, a gallium-doped ZnO layer, a hydrogen-doped ZnO layer or a zinc-doped ZnO layer.

[0013] In an embodiment, the doping atomic concentration of the doping element in the doped ZnO layer is 1% to 20%.

[0014] In an embodiment, the tunneling layer is a SiO2 layer, and the thickness of the tunneling layer is 0.5 nm to 2 nm.

[0015] In an embodiment, the perovskite cell comprises a hole transport layer, a perovskite light-absorbing layer, a second electron transport layer, a third electron transport layer and a transparent conductive layer which are sequentially stacked on the first electron transport layer.

[0016] In an embodiment, a first electrode is provided on the transparent conductive layer, and the first electrode is a gate line electrode.

[0017] In an embodiment, a first antireflection layer is provided on the first electrode and the transparent conductive layer.

[0018] In an embodiment, the crystalline silicon cell further comprises a P-type emitter on the back surface of the silicon substrate, and a passivation layer and a second antireflection layer which are sequentially stacked on the P-type emitter.

[0019] In an embodiment, the back surface of the silicon substrate is provided with a second electrode in contact with the P-type emitter.

[0020] Compared with the prior art, the utility model has the following beneficial effects:

[0021] The intrinsic ZnO layer or the doped ZnO layer is used as the first electron transport layer, a passivation contact structure of a crystalline silicon cell is formed, and the perovskite cell is directly arranged on the first electron transport layer, so that loss caused by parasitic light absorption is effectively reduced.

[0022] The first electron transport layer can be combined with the tunneling layer as a passivation contact structure of a crystalline silicon cell, and can also be used as an intermediate composite layer of a perovskite-crystalline silicon stacked cell, so that the process flow is simplified, and the cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description, and obviously, the drawings in the following description are only some embodiments in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0024] Figure 1 It is a structure schematic diagram of the perovskite-crystalline silicon stacked cell in the embodiment 1 of the present application.

[0025] Figures 2a to 2g It is a process flow chart of the preparation method of the perovskite-crystalline silicon stacked cell in the embodiment 1 of the present application.

[0026] Main drawing mark explanation:

[0027] 11-silicon substrate, 121-tunneling layer, 122-first electron transport layer, 13-P type emitter, 14-passivation layer, 15-second anti-reflection layer, 16-second electrode, 21-hole transport layer, 22-perovskite light absorption layer, 23-second electron transport layer, 24-third electron transport layer, 25-transparent conductive layer, 26-first electrode, 27-first anti-reflection layer. DETAILED DESCRIPTION

[0028] In order to make the person in the art better understand the technical solutions in the present application, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application, obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.

[0029] The present application discloses a perovskite-crystalline silicon stacked cell, comprising:

[0030] A crystalline silicon cell, the crystalline silicon cell includes a silicon substrate and a passivation contact structure on the front surface of the silicon substrate, the passivation contact structure includes a tunneling layer and a first electron transport layer stacked in sequence on the front surface of the silicon substrate, and the first electron transport layer is an intrinsic ZnO layer or a doped ZnO layer;

[0031] A perovskite cell, located above the first electron transport layer.

[0032] The following further illustrates the present utility model with specific examples.

[0033] Example 1:

[0034] Refer Figure 1 As shown, the perovskite-crystalline silicon tandem cell in this example includes:

[0035] A crystalline silicon cell, the crystalline silicon cell includes a silicon substrate 11 and a passivation contact structure on the front surface of the silicon substrate 11, the passivation contact structure includes a tunneling layer 121 and a first electron transport layer 122 stacked in sequence on the front surface of the silicon substrate 11, and the first electron transport layer 122 is an intrinsic ZnO layer or a doped ZnO layer;

[0036] A perovskite cell, located above the first electron transport layer 122.

[0037] Among them, the silicon substrate is an N-type crystalline silicon substrate, the tunneling layer 121 is a SiO2 layer, the thickness of the tunneling layer 121 is 0.5 nm to 2 nm, and preferably 1.5 nm in this example.

[0038] The first electron transport layer 122 in this example is a doped ZnO layer, including but not limited to one or more of an aluminum-doped ZnO layer, a boron-doped ZnO layer, a gallium-doped ZnO layer, a hydrogen-doped ZnO layer or a zinc-doped ZnO layer, with a thickness of 1 nm to 200 nm, and the doping atomic concentration of the doping element in the doped ZnO layer is 1% to 20%.

[0039] It should be understood that the thickness and doping concentration of the doped ZnO layer can be controlled by the number of supercycles and the cycle ratio in the doping subcycle in the supercycle atomic layer deposition (ALD) process.

[0040] Specifically, the first electron transport layer 122 in this example is an aluminum-doped ZnO layer with a thickness of 5 nm.

[0041] Furthermore, the crystalline silicon cell in this example further includes a P-type emitter 13 on the back surface of the silicon substrate 11, and a passivation layer 14 and a second antireflection layer 15 stacked in sequence on the P-type emitter 13.

[0042] Specifically, the P-type emitter 13 is prepared by boron diffusion, with a sheet resistance of 100 Ω / sq; the passivation layer 14 is an Al2O3 layer with a thickness of 10 nm; and the second antireflection layer 15 is SiN. x H layer, with a thickness of 65nm.

[0043] More specifically, in this embodiment, the back side of the silicon substrate 11 is also provided with a second electrode 16 that is in contact with the P-type emitter 13, and the second electrode 16 is a silver gate line electrode.

[0044] The perovskite solar cell in this embodiment includes a hole transport layer 21, a perovskite light-absorbing layer 22, a second electron transport layer 23, a third electron transport layer 24, and a transparent conductive layer 25, which are sequentially stacked on the first electron transport layer 122.

[0045] Specifically, the hole transport layer 21 is a self-assembled small molecule layer, and the perovskite light-absorbing layer 22 is made of a wide bandgap Cs with a bandgap of approximately 1.68 eV. 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 The second electron transport layer 23 is a 20nm thick C 60 The third electron transport layer 24 is a 20nm thick SnO2 layer, and the transparent conductive layer 25 is a 100nm thick zinc-doped indium oxide (IZO) layer.

[0046] Furthermore, a first electrode 26 is provided on the transparent conductive layer 25. The first electrode 26 is a silver grid line electrode, and a first antireflection layer 27 is provided on the transparent conductive layer 25 between the first electrode 26 and the grid line. In this embodiment, the first antireflection layer 27 is a magnesium fluoride layer with a thickness of 20 nm.

[0047] The fabrication method of the perovskite-crystalline silicon tandem solar cell in this embodiment includes the following steps:

[0048] S1, Reference Figure 2a As shown, a silicon substrate 11 is provided, and the surface of the silicon substrate 11 is textured to obtain a silicon substrate 11 with a textured surface structure.

[0049] Specifically, the silicon substrate 11 is an N-type crystalline silicon substrate. First, the silicon substrate 11 is etched with a 10wt% NaOH aqueous solution to remove the damaged layer on the surface of the silicon substrate 11. Then, a 2wt% NaOH solution is used to form a micron-scale pyramidal textured surface on the surface of the silicon substrate 11. Finally, the silicon substrate 11 is cleaned using the RCA standard cleaning method.

[0050] S2, Reference Figure 2b As shown, a P-type emitter 13 is fabricated on the back side of the silicon substrate 11.

[0051] Specifically, this step includes:

[0052] 1. The cleaned silicon substrate 11 is placed in a tube furnace for boron diffusion. At a diffusion temperature of 900°C, P-type emitters 13 with a sheet resistance of 100Ω / sq are simultaneously fabricated on the front and back sides of the silicon substrate 11.

[0053] 2. Use diluted hydrofluoric acid solution to remove the borosilicate glass on the surface of silicon substrate 11, and use a single-sided alkaline polishing process to remove the P-type emitter and pyramid texture on the front side of silicon substrate 11.

[0054] S3, Reference Figure 2c As shown, a passivation layer 14 and a second antireflection layer 15 are sequentially fabricated on the P-type emitter 13.

[0055] For example, firstly, an Al2O3 layer of 10 nm is deposited as a passivation layer 14 on the P-type emitter 13 on the back side of the silicon substrate 11 using atomic layer deposition (ALD) process, with the deposition temperature set to 200 °C; then, a 65 nm SiN layer is deposited on the passivation layer 14 using plasma-enhanced chemical vapor deposition (PECVD) process. x Layer H serves as the second antireflective layer 15, with a deposition temperature set to 400℃.

[0056] S4, Reference Figure 2d As shown, a passivated contact structure is fabricated on the front side of silicon substrate 1.

[0057] This step specifically includes:

[0058] 1. A SiO2 layer was prepared on the front side of a silicon substrate 11 as a tunneling layer 121 using ultraviolet ozone oxidation. The thickness of the tunneling layer 121 was 1.5 nm, the oxidation temperature was set to room temperature, and the oxidation time was set to 15 min.

[0059] 2. A 5 nm aluminum-doped ZnO layer was prepared on the tunneling layer 121 as the first electron transport layer 122 by supercycle atomic layer deposition process. The deposition temperature was set to 200℃, the gas pressure was set to 50mT, the doping cycle ratio of Al2O3 to ZnO was set to 1:24, and the number of supercycle cycles was 1.

[0060] 3. An Al2O3 passivation capping layer was prepared on the first electron transport layer 122 by atomic layer deposition. The deposition temperature was set to 200℃, the gas pressure was set to 50mT, and the number of deposition cycles was set to 300.

[0061] 4. The above structure was annealed in an annealing furnace with an atmosphere of 95% N2 and 5% H2. The annealing temperature was set to 500℃ and the annealing time was set to 30min.

[0062] 5. In order to achieve good contact between perovskite solar cells and crystalline silicon solar cells, after annealing, the above structure needs to be placed in a 0.1M Na2CO3 solution and heated to 60°C. After soaking for 8 minutes, the Al2O3 passivation capping layer is removed.

[0063] S5, Participant Figure 2e As shown, a perovskite solar cell is fabricated on the first electron transport layer 122.

[0064] Specifically, this step includes:

[0065] 1. A self-assembled small molecule layer was prepared on the first electron transport layer 122 by spin coating as a hole transport layer 21;

[0066] 2. A perovskite light-absorbing layer 22 with a bandgap of approximately 1.68 eV is prepared on the hole transport layer 21 using a spin-coating method. The material of the perovskite light-absorbing layer 22 is a wide bandgap Cs. 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ;

[0067] 3. A 20nm C20nm layer was prepared on the perovskite light-absorbing layer 22 using a high-temperature thermal evaporation process. 60 The layer serves as the second electron transport layer 23;

[0068] 4. Using atomic layer deposition (ALD) technology in C 60 A 20 nm SnO2 layer was prepared on the layer as the third electron transport layer 24, and the deposition temperature was set to 100 °C.

[0069] 5. A 100 nm zinc-doped indium oxide layer is prepared on the third electron transport layer 24 using magnetron sputtering as a transparent conductive layer 25.

[0070] S6, Participant Figure 2f As shown, the first electrode 26 and the second electrode 16 are prepared.

[0071] A second electrode 16, in contact with the P-type emitter 13, is fabricated on the back side of a silicon substrate using a screen printing process. A first electrode 26 is fabricated on a transparent conductive layer 25 using a high-temperature thermal evaporation process. In this embodiment, both the first electrode 26 and the second electrode 16 are silver grid line electrodes.

[0072] S7, Reference Figure 2g As shown, a first antireflection layer 27 is prepared on the first electrode 26 and the transparent conductive layer 25.

[0073] A first antireflection layer 27 is fabricated on the transparent conductive layer 25 between the first electrode 26 and the gate line using a high-temperature thermal evaporation process. In this embodiment, the first antireflection layer 27 is a magnesium fluoride layer with a thickness of 20 nm.

[0074] The perovskite-crystalline silicon tandem cell in the embodiment can achieve a photoelectric conversion efficiency of 29.8% on an effective area of 1cm 2 .

[0075] From the above technical solution, the utility model has the following beneficial effects:

[0076] The utility model discloses a passivation contact structure of crystalline silicon cell is formed by intrinsic ZnO layer or doped ZnO layer as the first electron transport layer, and the perovskite cell is directly arranged on the first electron transport layer, which effectively reduces the loss caused by parasitic light absorption.

[0077] The first electron transport layer in the utility model can be combined with the tunneling layer as the passivation contact structure of the crystalline silicon cell, and can also be used as the intermediate composite layer of the perovskite-crystalline silicon tandem cell, which simplifies the process flow and reduces the cost.

[0078] For those skilled in the art, it is obvious that the utility model is not limited to the details of the above exemplary embodiments, and the utility model can be realized in other specific forms without departing from the spirit or basic characteristics of the utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, and the scope of the utility model is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the utility model. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0079] In addition, it should be understood that, although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments that those skilled in the art can understand.

Claims

1. A perovskite-crystalline silicon tandem cell, characterized by, The stacked battery comprises: a crystalline silicon battery, comprising a silicon substrate and a passivation contact structure on the front surface of the silicon substrate, wherein the passivation contact structure comprises a tunneling layer and a first electron transport layer stacked in sequence on the front surface of the silicon substrate, and the first electron transport layer is an intrinsic ZnO layer or a doped ZnO layer; a perovskite battery on the first electron transport layer.

2. The perovskite-crystalline silicon tandem cell of claim 1, wherein The doped ZnO layer is one of an aluminum-doped ZnO layer, a boron-doped ZnO layer, a gallium-doped ZnO layer, a hydrogen-doped ZnO layer, or a zinc-doped ZnO layer.

3. The perovskite-crystalline silicon tandem cell of claim 1, wherein The tunneling layer is a SiO2 layer, and the thickness of the tunneling layer is 0.5-2 nm.

4. The perovskite-crystalline silicon tandem cell of claim 1, wherein, The perovskite battery comprises a hole transport layer, a perovskite light-absorbing layer, a second electron transport layer, a third electron transport layer, and a transparent conductive layer stacked in sequence on the first electron transport layer.

5. The perovskite-crystalline silicon tandem cell of claim 4, wherein A first electrode is arranged on the transparent conductive layer, and the first electrode is a gate line electrode.

6. The perovskite-crystalline silicon tandem cell of claim 5, wherein, A first anti-reflection layer is arranged on the first electrode and the transparent conductive layer.

7. The perovskite-silicon tandem cell of claim 1, wherein The crystalline silicon battery further comprises a P-type emitter on the back surface of the silicon substrate, and a passivation layer and a second anti-reflection layer stacked in sequence on the P-type emitter.

8. The perovskite-crystalline silicon tandem cell of claim 1, wherein, A second electrode is arranged on the back surface of the silicon substrate and in contact with the P-type emitter.

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