Driving circuit

Abstract

The utility model relates to a driving circuit. The gate driving circuit includes stages, where each stage of the gate driving circuit includes: a second transistor connected between the first node and the second node and including a first gate connected to a second terminal through which the first voltage is supplied and a second gate connected to a third terminal through which the second voltage is supplied; a fourth transistor connected between the second terminal and the output terminal and including a first gate connected to the second node and a second gate connected to the third node; a first capacitor connected between the second node and the output terminal; and a second capacitor connected between the third node and the output terminal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0035430, filed on March 13, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to a drive circuit configured to output a gate signal and a display device including the drive circuit. Background Technology

[0004] The display device includes a pixel region, a gate driving circuit, a data driving circuit, a controller, etc., wherein the pixel region includes multiple pixels. The gate driving circuit includes stages connected to gate lines, and each stage provides gate signals to the gate lines connected to it. Utility Model Content

[0005] One or more embodiments include a drive circuit capable of stably outputting a gate signal at low power and a display device including the drive circuit.

[0006] According to one or more embodiments, the driving circuit includes multiple stages, wherein each of the multiple stages includes: a first transistor connected between a first node and a first terminal and including a gate connected to a clock terminal, wherein a start signal is input through the first terminal and a clock signal is input through the clock terminal; a second transistor connected between the first node and a second node and including a first gate connected to the second terminal and a second gate connected to a third terminal, wherein a first voltage is provided through the second terminal and a second voltage is provided through the third terminal; a third transistor connected between the first node and the third node and including a gate connected to the third terminal; a fourth transistor connected between the second terminal and an output terminal and including a first gate connected to the second node and a second gate connected to the third node; a fifth transistor connected between the third terminal and the output terminal and including a gate connected to the third node; a first capacitor connected between the second node and the output terminal; and a second capacitor connected between the third node and the output terminal, wherein the first voltage is a high-level voltage and the second voltage is a low-level voltage.

[0007] In an embodiment, the driving circuit may further include: a sixth transistor connected between the first node and the third terminal and including a gate connected to a fourth terminal, the fourth terminal being configured to provide a reset signal; and a third capacitor connected between the first node and the second terminal.

[0008] In an embodiment, the first transistor, the third transistor, and the fifth transistor can be P-type transistors, and the second transistor and the fourth transistor can be N-type transistors.

[0009] In an embodiment, the start signal can include an external signal or an output signal output by a previous stage.

[0010] In an embodiment, the driving circuit can further include a seventh transistor connected between the output terminal and the fifth transistor and including a gate connected to the third node.

[0011] In an embodiment, the clock signal can alternate between a first voltage level and a second voltage level, wherein the first voltage level can be a high-level voltage level and the second voltage level can be a low-level voltage level.

[0012] In an embodiment, a clock signal input to a clock terminal of an even stage among the plurality of stages can be shifted by a half period from a clock signal input to a clock terminal of an odd stage among the plurality of stages.

[0013] In an embodiment, in a first section in which the start signal of the first voltage level is input and the clock signal of the second voltage level is input, the voltages of the first node and the third node can be at the first voltage level, and the voltage of the second node can be at a third voltage level higher than the first voltage level, and the output signal of the first voltage level can be output from the output terminal through the turned-on fourth transistor.

[0014] In an embodiment, in a second section after the first section and in which the start signal of the first voltage level is input and the clock signal of the first voltage level is input, the voltages of the first node and the third node can be at the first voltage level, and the voltage of the second node can be at the third voltage level, and the output signal of the first voltage level can be output from the output terminal through the turned-on fourth transistor.

[0015] In an embodiment, in a third section after the second section and in which the start signal of the second voltage level is input and the clock signal of the first voltage level is input, the voltages of the first node and the second node can be at the first voltage level, and the voltage of the third node can be at the third voltage level, and the output signal of the first voltage level can be output from the output terminal through the turned-on fourth transistor.

[0016] In an embodiment, in a fourth segment after the third segment and in which the start signal of the second voltage level is input and in which the clock signal of the first voltage level is input, the voltages of the first node and the second node can be at the second voltage level, and the voltage of the third node can be at a fourth voltage level, the fourth voltage level being lower than the second voltage level, and the output signal of the second voltage level can be output from the output terminal through the fifth transistor turned on.

[0017] In an embodiment, in a fifth segment after the fourth segment and in which the start signal of the second voltage level is input and in which the clock signal of the first voltage level is input, the voltages of the first node and the second node can be at the second voltage level, and the voltage of the third node can be at a fourth voltage level, and the output signal of the second voltage level can be output from the output terminal through the fifth transistor turned on.

[0018] In an embodiment, the driving circuit can further include a sixth transistor connected between the second node and the third terminal and including a gate connected to the third node.

[0019] According to one or more embodiments, the driving circuit includes a plurality of stages, wherein each of the plurality of stages includes: a first transistor connected between a first node and a first terminal and including a gate connected to a clock terminal, a start signal being input through the first terminal, a clock signal being input through the clock terminal; a second transistor connected between the first node and a second node and including a first gate connected to a second terminal and a second gate connected to a third terminal, a first voltage being supplied through the second terminal, a second voltage being supplied through the third terminal; a third transistor connected between the first node and a third node and including a gate connected to a fourth terminal, a third voltage being supplied through the fourth terminal; a fourth transistor connected between the second terminal and an output terminal and including a first gate connected to the second node and a second gate connected to a fifth terminal, a fourth voltage being supplied through the fifth terminal; a fifth transistor connected between the fourth terminal and the output terminal and including a gate connected to the third node; a first capacitor connected between the second node and the output terminal; and a second capacitor connected between the third node and the output terminal, wherein the first voltage is a high voltage level, and the third voltage is a low voltage level.

[0020] In an embodiment, the driving circuit can further include: a sixth transistor connected between the first node and the fourth terminal and including a gate connected to a sixth terminal, the sixth terminal being configured to supply a reset signal; and a third capacitor connected between the first node and the second terminal.

[0021] In an embodiment, the driving circuit can further include a seventh transistor connected between the third transistor and a third node and including a gate connected to the fourth terminal, and an eighth transistor connected between a fourth node and a seventh terminal and including a gate connected to the third node, the fourth node being between the third transistor and the seventh transistor, a fifth voltage being supplied through the seventh terminal, wherein the fifth voltage can be lower than the third voltage.

[0022] In an embodiment, the first transistor, the third transistor, the fifth transistor, the seventh transistor, and the eighth transistor can be P-type transistors, and the second transistor and the fourth transistor can be N-type transistors.

[0023] In an embodiment, the second voltage can be equal to the first voltage.

[0024] In an embodiment, the third terminal can be connected to the first node.

[0025] In an embodiment, the fourth voltage can be a negative constant voltage having an absolute value greater than that of the third voltage. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 FIG. 1 is a diagram schematically illustrating a stage constituting a driving circuit according to an embodiment;

[0028] Figure 2 FIG. 2 is a diagram schematically illustrating transistors included in a stage according to an embodiment;

[0029] Figure 3 FIG. 3 is a diagram schematically illustrating a driving circuit according to an embodiment;

[0030] Figure 4 FIG. 4 is a timing diagram schematically illustrating input / output signals of a driving circuit according to an embodiment;

[0031] Figure 5 FIG. 5 is a circuit diagram showing an example of a stage included in a driving circuit according to an embodiment; Figure 3

[0032] Figure 6 FIG. 6 is a timing diagram describing driving of a stage according to an embodiment; Figure 5

[0033] Figure 7A FIG. 7 is a diagram for describing a signal input to a terminal connected to a transistor included in a stage according to an embodiment;

[0034] Figure 7B ​​is a graph schematically showing a voltage-current graph of a transistor in a certain section according to an embodiment;

[0035] Figure 8A is a graph for describing a signal input to a terminal connected to a transistor included in a stage according to an embodiment;

[0036] Figure 8B is a graph schematically showing a voltage-current graph of a transistor in a certain section according to an embodiment;

[0037] Figure 9A is a graph for describing a signal input to a terminal connected to a transistor included in a stage according to an embodiment;

[0038] Figure 9B is a graph schematically showing a voltage-current graph of a transistor in a certain section according to an embodiment;

[0039] Figure 10A is a graph for describing a signal input to a terminal connected to a transistor included in a stage according to an embodiment;

[0040] Figure 10B is a graph schematically showing a voltage-current graph of a transistor in a certain section according to an embodiment;

[0041] Figure 11A is a circuit diagram showing an example of a stage included in a drive circuit according to an embodiment; Figure 3

[0042] Figure 11B is a circuit diagram showing an example of a stage included in a drive circuit according to an embodiment; Figure 3

[0043] Figure 11C is a circuit diagram showing an example of a stage included in a drive circuit according to an embodiment; Figure 3

[0044] Figure 11D is a circuit diagram showing an example of a stage included in a drive circuit according to an embodiment; Figure 3

[0045] Figure 12 is a circuit diagram showing an example of a stage included in a drive circuit according to an embodiment; Figure 3

[0046] Figure 13 is a circuit diagram showing an example of a stage included in a drive circuit according to an embodiment; Figure 3

[0047] Figure 14 ​​​​​​is a circuit diagram showing an example of a stage included in a driving circuit of the display device according to the embodiment; Figure 3 is a circuit diagram showing an example of a stage included in a driving circuit of the display device according to the embodiment; and

[0048] Figure 15 is a diagram schematically showing the display device according to the embodiment. DETAILED DESCRIPTION

[0049] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. It shall be understood that the present disclosure can be directed to various embodiments and modifications embodied in the following detailed description thereof. The effects and features of the present disclosure will become apparent from the detailed description of the embodiments given below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described below, and can be implemented in various modes.

[0050] The present disclosure can include various embodiments and modifications, and specific embodiments thereof are illustrated in the accompanying drawings and will be described in detail herein. The effects and features of the present disclosure will become apparent from the detailed description of the embodiments given below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described below, and can be implemented in various modes.

[0051] It will be understood that, although the terms such as "first" and "second" can be used herein to describe various elements, the elements should not be limited by these terms, and the terms are used only to distinguish one element from another element.

[0052] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0053] Further, it will be understood that the terms "comprises", "comprising", "includes" and "including" as used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0054] It will be understood that when a layer, region, area, component or element is referred to as being "on" another layer, region, area, component or element, it can be "directly" on the other layer, region, area, component or element or intervening layers, regions, areas, components or elements can also be present.

[0055] Further, the size of elements in the drawings can be exaggerated for the purpose of description. In other words, since the size and thickness of elements in the drawings are arbitrarily shown for the purpose of description, the present disclosure is not limited thereto.

[0056] As used herein, "A and / or B" means A, B, or both A and B. Further, "at least one of A and B" means A, B, or both A and B.

[0057] In the following embodiments, when X and Y are connected to each other, X and Y can be electrically connected to each other, X and Y can be functionally connected to each other, or X and Y can be physically connected to each other. Further, when X and Y are connected to each other, X and Y can be directly connected to each other, or X and Y can be indirectly connected to each other with one or more other elements disposed therebetween. Here, X and Y can be elements (for example, a device, a component, a circuit, a wire, an electrode, a terminal, a film, a layer, or a region).

[0058] For example, when X and Y are electrically connected to each other, X and Y can be directly electrically connected to each other, or X and Y can be indirectly electrically connected to each other with one or more other elements therebetween. When X and Y are indirectly electrically connected to each other, one or more components (for example, a switch, a transistor, a capacitor, an inductor, a resistor, or a diode) that achieve electrical connection between X and Y can be connected between X and Y. Thus, the present disclosure is not limited to a specific connection relationship, for example, a connection relationship indicated in the drawings or the detailed description, and can also include any other connection relationship in addition to the connection relationship indicated in the drawings or the detailed description.

[0059] In the following embodiments, "on" used in connection with a device state can mean an activation state of the device, and "off" can mean a deactivation state of the device. "On" used in connection with a signal received by a device can mean a signal that activates the device, and "off" can mean a signal that deactivates the device. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-type transistor (P-channel transistor) can be activated by a low-level voltage, and an N-type transistor (N-channel transistor) can be activated by a high-level voltage. Thus, it is understood that the "on" voltage of the P-type transistor and the N-type transistor has an opposite voltage level (low voltage level vs. high voltage level). Hereinafter, a voltage that activates (turns on) a transistor will be referred to as a gate-on voltage, and a voltage that deactivates (turns off) a transistor will be referred to as a gate-off voltage.

[0060] Figure 1 FIG. 1 is a diagram schematically illustrating a stage constituting a driving circuit according to an embodiment. Figure 2 FIG. 2 is a diagram schematically illustrating a transistor included in a stage according to an embodiment.

[0061] In an embodiment and with reference toFigure 1 and Figure 2 The driving circuit can include a plurality of stages ST, wherein each stage ST can receive at least one input signal In and generate at least one output signal Out. The at least one input signal In can include a start signal, at least one clock signal, and at least one voltage signal.

[0062] Each stage ST can include a plurality of transistors, wherein some of the plurality of transistors can be P-type transistors and some other transistors can be N-type transistors.

[0063] Each of the P-type transistors and the N-type transistors can be a three-terminal device including a gate G, a source S, and a drain D. In an embodiment, each of the P-type transistors and the N-type transistors can be a four-terminal device including a gate G, a source S, a drain D, and a back gate BG.

[0064] The P-type transistors can be silicon transistors, wherein the silicon transistors can include a silicon semiconductor, and the silicon semiconductor can include amorphous silicon, polysilicon, etc. For example, the silicon transistors can be low temperature polysilicon (LTPS) thin film transistors.

[0065] The N-type transistors can be oxide transistors, wherein the oxide transistors can include an oxide semiconductor, and the oxide semiconductor can include a zinc oxide-based material such as zinc oxide, indium zinc oxide, or gallium indium zinc oxide. In some embodiments, the oxide semiconductor can be an indium gallium zinc oxide (IGZO) semiconductor. In some embodiments, the oxide semiconductor can be an indium tin gallium zinc oxide (ITGZO) semiconductor. For example, the oxide transistors can be low temperature polysilicon oxide (LTPO) thin film transistors.

[0066] For a 4-terminal N-type oxide transistor, when a (-) voltage is applied to its back gate BG, its threshold voltage can increase and thus can be forward shifted (positive shift), and when a (+) voltage is applied to it, the threshold voltage can decrease and thus can be negative shifted (negative shift).

[0067] The threshold voltage of the oxide transistor can decrease due to process dispersion, and thus the oxide transistor can not be turned off. To adjust the threshold voltage of the oxide transistor, a (-) voltage can be applied to its back gate BG to forward shift the threshold voltage. However, the operating speed of the oxide transistor can decrease, and thus its on current can decrease. When a (+) voltage is applied to the back gate BG of the oxide transistor, the decrease in the operating speed and the decrease in the on current of the oxide transistor can be minimized, but its threshold voltage can be negative shifted.

[0068] Figure 3 FIG. 1 is a diagram schematically illustrating a driving circuit according to an embodiment.Figure 4 is a timing chart schematically illustrating input / output signals of a driving circuit according to an embodiment.

[0069] In an embodiment and with reference to Figure 3 , the driving circuit DRV can include a plurality of stages ST1 to STn, wherein the plurality of stages ST1 to STn can sequentially output output signals GS[1], GS[2], GS[3], GS[4], …, GS[n] to the signal line.

[0070] Each of the stages ST1 to STn can include a plurality of terminals through which a plurality of signals are input. The plurality of signals can include a start signal, clock signals CLK1 and CLK2, voltage signals VGH and VGL, and a reset signal ESR. The plurality of terminals can include an input terminal IN, a first voltage input terminal V1, a second voltage input terminal V2, a clock terminal CK, and an output terminal OUT.

[0071] The start signal can be input (provided) to the input terminal IN. The plurality of stages ST1 to STn can output the output signals GS[1], GS[2], GS[3], GS[4], …, GS[n] to the signal line and output the output signals GS[1], GS[2], GS[3], GS[4], …, GS[n] to the input terminal IN of a corresponding next stage as carry signals CR[1], CR[2], CR[3], CR[4], …, respectively, in response to the start signal. The start signal can be an external signal FLM or an output signal (hereinafter, referred to as a previous output signal) output by a previous stage. The external signal FLM can be input to the input terminal IN of the first stage ST1 as the start signal, and the output signal (previous carry signal) output by the previous stage can be input to the input terminal IN of each of the second stage ST2 to the nth stage STn as the start signal. The previous stage can be a stage located at at least one stage before a current stage. Figure 3 An embodiment in which the previous stage is a stage immediately before the current stage is illustrated. For example, the output signal GS[3] output from the third stage ST3 can be input to the input terminal IN of the fourth stage ST4 as the start signal.

[0072] The first voltage VGH can be input to the first voltage input terminal V1, and the second voltage VGL can be input to the second voltage input terminal V2, wherein the second voltage VGL can be lower than the first voltage VGH. Hereinafter, the first voltage VGH can be referred to as a high-level voltage, and the second voltage VGL can be referred to as a low-level voltage.

[0073] A first clock signal CLK1 or a second clock signal CLK2 can be input to the clock terminal CK. In one embodiment, the first clock signal CLK1 can be input to the clock terminal CK of each of the odd-numbered stages ST1, ST3, ..., and the second clock signal CLK2 can be input to the clock terminal CK of each of the even-numbered stages ST2, ST4, ... In another embodiment, the second clock signal CLK2 input to the clock terminal CK of each of the odd-numbered stages ST1, ST3, ..., and the first clock signal CLK1 can be input to the clock terminal CK of each of the even-numbered stages ST2, ST4, ... In yet another embodiment, the second clock signal CLK2 input to the clock terminal CK of each of the even-numbered stages ST2, ST4, ... can be shifted by half a cycle from the first clock signal CLK1 input to the clock terminal CK of each of the odd-numbered stages ST1, ST3, ...

[0074] In the implementation and as Figure 4 As shown, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals alternating between high-level voltages and low-level voltages. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals alternating between a first voltage VGH and a second voltage VGL. In an embodiment, for the first clock signal CLK1 and the second clock signal CLK2, the duration of the high-level voltage holding for one cycle can be longer than the duration of the low-level voltage holding for one cycle.

[0075] In the implementation, odd-numbered stages ST1, ST3, ... can output output signals GS[1], GS[3], ... from the output terminal OUT synchronously with the first clock signal CLK1 input to the clock terminal CK. For example... Figure 4 As shown, the output signals GS[1], GS[3], ... output from the output terminals OUT of the odd-numbered stages ST1, ST3, ... can be shifted sequentially at specific intervals. In the embodiment, the odd-numbered stages ST1, ST3, ... can sequentially output high-level voltage output signals GS[1], GS[3], ... by shifting the high-level voltage output signals GS[1], GS[3], ... by the period of the first clock signal CLK1.

[0076] Even-numbered stages ST2, ST4, ... can output output signals GS[2], GS[4], ... from the output terminal OUT in sync with the second clock signal CLK2 input to the clock terminal CK. For example... Figure 4As illustrated in FIG. 1, output signals GS[2], GS[4],... output from the output terminals OUT of the even-stage ST2, ST4,... can be sequentially shifted at a certain interval. In an embodiment, the even-stage ST2, ST4,... can sequentially output the output signals GS[2], GS[4],... of the high-level voltage by shifting the output signals GS[2], GS[4],... of the high-level voltage by a period of the second clock signal CLK2.

[0077] In an embodiment and with reference again to Figure 3 , a reset signal ESR can be input to the reset terminal RESET. The reset signal ESR of the gate-on voltage can be input to the gate of the corresponding transistor at a certain timing, and the reset signal ESR of the gate-off voltage can be input to the gate of the corresponding transistor at another timing. For example, when a power is input to the display device (power on), the reset signal ESR can be input to the stages ST1 to STn as the gate-on voltage for a certain period of time, and can be input to the stages ST1 to STn as the gate-off voltage after a lapse of the certain period of time. The reset signal ESR can be input as the gate-off voltage when the stages ST1 to STn operate to generate the output signals GS[1], GS[2], GS[3], GS[4],..., GS[n].

[0078] Figure 5 is a circuit diagram illustrating an example of a stage included in a driving circuit of Figure 3 according to an embodiment. Figure 6 is a timing diagram describing driving of a stage of Figure 5 according to an embodiment.

[0079] In an embodiment and with reference again to Figure 5 , the stage STka can include a control circuit 131 and an output circuit 135, each of which can include at least one transistor. The at least one transistor can include an N-type transistor and / or a P-type transistor. For example, the first transistor T1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 of the stage STka can be P-type transistors, and the second transistor T2 and the fourth transistor T4 thereof can be N-type transistors. In an embodiment, each of the second transistor T2 and the fourth transistor T4 can be a four-terminal device including a source, a drain, a gate, and a back gate. The gate-on voltage of the P-type transistor can be a low-level voltage, and the gate-off voltage thereof can be a high-level voltage. The gate-on voltage of the N-type transistor can be a high-level voltage, and the gate-off voltage thereof can be a low-level voltage. Hereinafter, the high-level voltage can be a first voltage level H (hereinafter, referred to as a high level H) (see Figure 6 ), and the low-level voltage can be a second voltage level L (hereinafter, referred to as a low level L) (seeFigure 6 ), the high-level voltage higher than the high level can be a third voltage level HH (see Figure 6 ), and the low-level voltage lower than the low level can be a fourth voltage level LL (see Figure 6 ).

[0080] In addition, the first terminal of each of the first to sixth transistors T1 to T6 can be a source or a drain, respectively, and the second terminal thereof can be a terminal different from the first terminal, depending on the transistor type (P-type or N-type) and / or the operation condition. For example, when the first terminal is a source, the second terminal can be a drain.

[0081] The control circuit 131 can control the voltages of the first node Q and the second node QB in response to signals input to the input terminal IN and the clock terminal CK. For example, the control circuit 131 can control the voltages of the first node Q and the second node QB in response to a start signal (e.g., an external signal FLM (see Figure 3 ) or a previous output signal) or a clock signal CLK. Figure 5 An example in which the kth stage STka receives, as a start signal, an input of a previous output signal GS[k-1] output from the (k-1)th stage and outputs an output signal GS[k] is shown. Referring to Figure 5 In an embodiment, the control circuit 131 can include the first to third transistors T1 to T3 and the sixth transistor T6. The control circuit 131 can further include a third capacitor C3.

[0082] In an embodiment, the first transistor T1 can be connected between the input terminal IN and the third node A. The gate of the first transistor T1 can be connected to the clock terminal CK. When the first clock signal CLK1 or the second clock signal CLK2 input to the clock terminal CK is at a low level, the first transistor T1 can be turned on to transmit a start signal GS[k-1] input through the input terminal IN to the third node A. In an embodiment, the first clock signal CLK1 or the second clock signal CLK2 can be input to the clock terminal CK of each of odd-numbered stages ST1, ST3, …, and the second clock signal CLK2 or the first clock signal CLK1 can be input to the clock terminal CK of each of even-numbered stages ST2, ST4, …

[0083] In an embodiment, the second transistor T2 can be connected between the first node Q and the third node A. A gate of the second transistor T2 can be connected to the first voltage input terminal V1 configured to provide the first voltage VGH, and a back gate thereof can be connected to the second voltage input terminal V2 configured to provide the second voltage VGL. The second transistor T2 can be turned on by the first voltage VGH input to the first voltage input terminal V1, and can be configured to transmit a voltage of the third node A to the first node Q.

[0084] In an embodiment, the third transistor T3 can be connected between the second node QB and the third node A. A gate of the third transistor T3 can be connected to the second voltage input terminal V2 configured to provide the second voltage VGL. The third transistor T3 can be turned on by the second voltage VGL input to the second voltage input terminal V2, and can be configured to transmit a voltage of the third node A to the second node QB.

[0085] In an embodiment, the sixth transistor T6 can be connected between the second voltage input terminal V2 and the third node A. A gate of the sixth transistor T6 can be connected to the reset terminal RESET, such that when a reset signal ESR of a low level is applied to the reset terminal RESET, the sixth transistor T6 can be turned on to set a voltage of the third node A to the second voltage VGL.

[0086] In an embodiment, the third capacitor C3 can be connected between the third node A and the first voltage input terminal V1, wherein a voltage difference between the third node A and the first voltage input terminal V1 can be stored in the third capacitor C3.

[0087] In an embodiment, the output circuit 135 can be connected between the first voltage input terminal V1 and the second voltage input terminal V2. The output circuit 135 can output an output signal GS[k] of a first voltage level voltage or a second voltage level voltage according to voltage levels of the first node Q and the second node QB. The first voltage level voltage can be a high level voltage, and the second voltage level voltage can be a low level voltage. The output circuit 135 can include a fourth transistor T4 and a fifth transistor T5, and can further include a first capacitor C1 and a second capacitor C2.

[0088] In an embodiment, the fourth transistor T4 can be connected between the first voltage input terminal V1 and an output terminal OUT. A gate of the fourth transistor T4 can be connected to the first node Q, and a back gate thereof can be connected to the second node QB. The fourth transistor T4 can be a pull-up transistor configured to transmit a high level voltage to the output terminal OUT. When the first node Q is at a high level, the fourth transistor T4 can be turned on to transmit the first voltage VGH input through the first voltage input terminal V1 to the output terminal OUT.

[0089] In an embodiment, the fifth transistor T5 can be connected between the second voltage input terminal V2 and the output terminal OUT, and the gate of the fifth transistor T5 can be connected to the second node QB. The fifth transistor T5 can be a pull-down transistor configured to transmit a low-level voltage to the output terminal OUT. When the second node QB is at a low level, the fifth transistor T5 can be turned on to transmit the second voltage VGL input through the second voltage input terminal V2 to the output terminal OUT. The first capacitor C1 can be connected between the first node Q and the output terminal OUT. The voltage of the first node Q can be maintained by the first capacitor C1 even when the first transistor T1 is turned off. When the voltage level at the output terminal OUT is converted from the second voltage level to the first voltage level, the first voltage level of the first node Q can be up-bootstrapped to the third voltage level by the coupling of the first capacitor C1.

[0090] In an embodiment, the second capacitor C2 can be connected between the second node QB and the output terminal OUT. The voltage of the second node QB can be maintained by the second capacitor C2 even when the first transistor T1 is turned off. When the voltage level at the output terminal OUT is converted from the first voltage level to the second voltage level, the second voltage level of the second node QB can be down-bootstrapped to the fourth voltage level by the coupling of the second capacitor C2.

[0091] Figure 6 The previous output signal GS[k-1] as a start signal, the first clock signal CLK1 input to the clock terminal CK of each of the odd stages ST1, ST3, …, the second clock signal CLK2 input to the clock terminal CK of each of the even stages ST2, ST4, …, the voltage VQ of the first node Q, the voltage VQB of the second node QB, the voltage VA of the third node A, and the output signal GS[k] are shown. The second clock signal CLK2 can be shifted by half a period from the first clock signal CLK1. The following will be described with reference to the timing chart of FIG. 6. Figure 6An example in which the k-th stage STka is an odd stage in which an input of the first clock signal CLK1 is received through the clock terminal CK is described. The first stage ST1 can operate identically to the operation described in detail below except that the external signal FLM is input to the input terminal IN as a start signal. The operation of the odd stages ST1, ST3, … can be similarly applied to the operation of the even stages ST2, ST4, …. In the first section P1, the previous output signal GS[k-1] of the high level H can be provided to the input terminal IN from the previous stage, and the first clock signal CLK1 of the low level L can be provided to the clock terminal CK. In this case, the previous output signal GS[k-1] of the high level H transmitted to the input terminal IN can be an output signal output from the previous even stage in response to the second clock signal CLK2 of the low level L.

[0092] The first transistor T1 can be turned on by the first clock signal CLK1 of the low level L. When the back-gate-source voltage Vbs of the second transistor T2 becomes Vbs(T2)<0 as the voltage VA of the third node A changes from the low level L to the high level H, the second transistor T2 turned on by the first voltage VGH provided to the gate thereof can be turned off. The third transistor T3 can be turned on by the second voltage VGL of the low level L.

[0093] The previous output signal GS[k-1] of the high level H can be transmitted to the third node A through the turned-on first transistor T1, and the voltage VA of the third node A can change from the low level L to the high level H. The voltage VA of the high level H of the third node A can be transmitted to the first node Q through the second transistor T2 turned on by the first voltage VGH provided to the gate thereof. Accordingly, the fourth transistor T4 can be turned on, and thus the first voltage VGH of the high level H can be transmitted to the output terminal OUT. Accordingly, the output signal GS[k] of the high level H can be output from the output terminal OUT through the turned-on fourth transistor T4.

[0094] In addition, the voltage VA of the high level H of the third node A can be transmitted to the second node QB through the third transistor T3 turned on by the second voltage VGL provided to the gate thereof, and the voltage VQB of the second node QB can be the voltage of the high level H. Accordingly, the fifth transistor T5 can be turned off. The voltage difference between the output terminal OUT and the first node Q can be stored in the first capacitor C1.

[0095] As the voltage VA of the third node A rises to the high level H, when the back-gate-source voltage Vbs of the second transistor T2 becomes Vbs(T2) < 0, the second transistor T2 can be turned off, and the electrical connection of the first node Q to the third node A can be disconnected. As the voltage of the output terminal OUT rises from the low level L to the high level H, the voltage VQ of the first node Q can be pulled up to the third voltage level HH by the coupling of the first capacitor C1. The voltage difference between the output terminal OUT and the first node Q can be stored in the first capacitor C1.

[0096] In the second section P2, the previous output signal GS[k-1] of the high level can be provided to the input terminal IN, and the first clock signal CLK1 of the high level can be provided to the clock terminal CK.

[0097] The first transistor T1 can be turned off by the first clock signal CLK1 of the high level H, and the second transistor T2 can be turned off because the back-gate-source voltage Vbs of the second transistor T2 becomes Vbs < 0 due to the voltage VA of the high level H of the third node A. The third transistor T3 can be turned on by the second voltage VGL of the low level L.

[0098] In the second section P2, when the first transistor T1 is turned off, the voltage VA of the third node A can be maintained at the high level H in the first section P1. The voltage VQ of the first node Q can be maintained at the third voltage level HH by the first capacitor C1, and thus, the fourth transistor T4 can be turned on. The first voltage VGH can be transmitted to the output terminal OUT by the turned-on fourth transistor T4, and the voltage VA of the high level H of the third node A can be transmitted to the second node QB by the third transistor T3 which is maintained in the turned-on state by the second voltage VGL provided to the gate thereof, and the voltage VQB of the second node QB can be the voltage of the high level H. Thus, the fifth transistor T5 can be turned off.

[0099] Thus, the output signal GS[k] of the high level H can be output from the output terminal OUT by the turned-on fourth transistor T4. The voltage difference between the output terminal OUT and the first node Q can be stored in the first capacitor C1.

[0100] In the third section P3, the previous output signal GS[k-1] of the low level L can be provided to the input terminal IN, and the first clock signal CLK1 of the high level H can be provided to the clock terminal CK.

[0101] The voltage level of the signal provided to the input terminal IN in the third section P3 can be the low level L, and the voltage level of the signal provided to the input terminal IN in the second section P2 can be the high level H, which can be different from each other. However, the first transistor T1 can be turned off by the first clock signal CLK1 of the high level H, and thus the voltage VQ of the first node Q, the voltage VQB of the second node QB, the voltage VA of the third node A, and the voltage level of the output signal GS[k] in the second section P2 can also be maintained in the third section P3.

[0102] In the fourth section P4, the previous output signal GS[k-1] of the low level L can be provided to the input terminal IN, and the first clock signal CLK1 of the low level L can be provided to the clock terminal CK.

[0103] The first transistor T1 can be turned on by the first clock signal CLK1 of the low level L, the second transistor T2 can be turned on by the first voltage VGH, and the third transistor T3 can be turned off as the voltage VA of the third node A changes to the second voltage level L.

[0104] The previous output signal GS[k-1] of the low level L can be transmitted to the third node A through the turned-on first transistor T1, and the voltage VA of the third node A can be at the low level L. When the voltage VA of the third node A falls to the low level L, the second transistor T2 can be turned on because the back-gate-source voltage Vbs of the second transistor T2 can become Vbs(T2)=0 and the gate-source voltage Vgs of the second transistor T2 can become Vgs(T2)>0. Through the turned-on second transistor T2, the voltage VA of the low level L of the third node A can be transmitted to the first node Q, and the voltage VQ of the first node Q can be at the low level L. Accordingly, the fourth transistor T4 can be turned off.

[0105] In addition, the voltage VA of the third node A of the high level H can be transmitted to the second node QB through the third transistor T3 which maintains the turned-on state by the second voltage VGL provided to the gate thereof. Accordingly, the fifth transistor T5 can be turned on, and thus the second voltage VGL of the low level L can be transmitted to the output terminal OUT. Accordingly, the output signal GS[k] of the low level L can be output from the output terminal OUT through the turned-on fifth transistor T5. The voltage difference between the output terminal OUT and the second node QB can be stored in the second capacitor C2.

[0106] As the voltage VA of the third node A falls to the low level L, the third transistor T3 can be turned off when the gate-source voltage Vgs of the third transistor T3 becomes Vgs(T3) = 0, and the electrical connection of the second node QB to the third node A can be broken. As the voltage of the output terminal OUT falls from the high level H to the low level L, the voltage VQB of the second node QB can be pulled down to the fourth voltage level LL by the coupling of the second capacitor C2.

[0107] In the fifth segment P5, the previous output signal GS[k-1] of the low level L can be provided to the input terminal IN, and the first clock signal CLK1 of the high level H can be provided to the clock terminal CK.

[0108] The first transistor T1 can be turned off by the first clock signal CLK1 of the high level H, and the second transistor T2 can be turned on by the first voltage VGH. As the voltage VA of the third node A is maintained at the low level L by the turned-off first transistor T1, the third transistor T3 can be maintained in the turned-off state.

[0109] In the fifth segment P5, as the first transistor T1 is turned off, the voltage VA of the third node A can be maintained at the low level L in the fourth segment P4. The voltage VA of the third node A can be transmitted to the first node Q by the turned-on second transistor T2, and the voltage VQ of the first node Q can be at the low level L. Accordingly, the fourth transistor T4 can be maintained in the turned-off state. The voltage VQB of the second node QB can be maintained at the fourth voltage level LL by the second capacitor C2, and accordingly, the fifth transistor T5 can be turned on. The second voltage VGL can be transmitted to the output terminal OUT by the turned-on fifth transistor T5.

[0110] Accordingly, the output signal GS[k] of the low level L can be output from the output terminal OUT by the turned-on fifth transistor T5. The voltage difference between the output terminal OUT and the second node QB can be stored in the second capacitor C2.

[0111] Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A are graphs for describing signals input to terminals connected to transistors included in a stage according to embodiments. Figure 7B 、 Figure 8B 、 Figure 9B and Figure 10B are graphs schematically showing voltage-current graphs of transistors in a certain segment according to embodiments.

[0112] In embodiments and with reference to Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10Aincluding each of the second transistor T2 and the fourth transistor T4 in the stage STka shown in Figure 5 Each of the second transistor T2 and the fourth transistor T4 in the stage STka can be an N-type oxide transistor, and can be a four-terminal device including a source, a drain, a gate, and a back gate.

[0113] In an embodiment, an alternating current (AC) voltage can be applied to the gate and / or the back gate of each of the second transistor T2 and the fourth transistor T4. For example, a low-level voltage can be applied to the gate and / or the back gate of each of the second transistor T2 and the fourth transistor T4 in some sections of the operation section of the stage STka, and a high-level voltage can be applied to the gate and / or the back gate of each of the second transistor T2 and the fourth transistor T4 in some other sections thereof. In an embodiment, the AC voltage can be a voltage of a particular node in the stage STka, whose voltage level changes.

[0114] Figure 7A A state in which the fourth transistor T4 is turned off after the fourth section P4 is shown. In an embodiment, the source electrode of the fourth transistor T4 is connected to the output terminal OUT, and the source electrode voltage of the fourth transistor T4 can be the voltage of the output terminal OUT. Because the voltage of the output terminal OUT after the fourth section P4 is the second voltage VGL, the second voltage VGL can be provided to the source electrode of the fourth transistor T4. The drain electrode of the fourth transistor T4 can be connected to the first voltage input terminal V1 to provide the first voltage VGH.

[0115] The gate of the fourth transistor T4 can be connected to the first node Q, and the voltage VA of the third node A can be transmitted to the first node Q through the turned-on second transistor T2. In the fourth section P4, the voltage of the previous output signal GS[k-1] of the low-level L can be lowered by the threshold voltage Vth of the first transistor T1 as a P-type transistor and then transmitted to the third node A through the turned-on first transistor T1. In an embodiment, the voltage of the previous output signal GS[k-1] of the low-level L can be the second voltage VGL. In this embodiment, the voltage VA of the third node A can be given by VGL+|Vth|, which is smaller than the second voltage VGL by the threshold voltage Vth. The voltage VA of the third node A can be transmitted to the first node Q through the turned-on second transistor T2, and the voltage given by VGL+|Vth| can be provided to the gate of the fourth transistor T4. Because the gate-source voltage Vgs of the fourth transistor T4 is given by Vgs(T4)=(VGL+|Vth|)-VGL and Vgs(T4)=|Vth|>0, the fourth transistor T4, which should be turned off, can be turned on, and thus the voltage level of the output signal GS[k] can be changed.

[0116] In an embodiment, the back gate of the fourth transistor T4 can be connected to the second node QB. In an embodiment, after the fourth segment P4, the voltage VQB of the second node QB can be the fourth voltage level LL, and the voltage of the fourth voltage level LL can be 2VGL, which is about twice the second voltage VGL. Thus, a voltage of about 2VGL can be provided to the back gate of the fourth transistor T4. In this case, referring to Figure 7B Because the back gate-source voltage Vbs of the fourth transistor T4 is given by Vbs(T4) = 2VGL - VGL and Vbs(T4) = VGL < 0, as the threshold voltage of the fourth transistor T4 is positively shifted, the current-voltage plot can be shifted to the right, and the fourth transistor T4 can be completely turned off.

[0117] Figure 8A An embodiment showing a state in which the fourth transistor T4 is turned on in the first segment PI, the second segment P2, and the third segment P3 is shown. The drain electrode of the fourth transistor T4 can be connected to the first voltage input terminal VI to provide the first voltage VGH.

[0118] The gate of the fourth transistor T4 can be connected to the first node Q. In an embodiment, in the first segment PI, the second segment P2, and the third segment P3, the voltage VQ of the first node Q can be the third voltage level HH, and the voltage of the third voltage level HH can be given by 2VGH, which is about twice the first voltage VGH. Thus, a voltage of about 2VGH can be provided to the gate of the fourth transistor T4.

[0119] The back gate of the fourth transistor T4 can be connected to the second node QB. In an embodiment, in the first segment PI, the second segment P2, and the third segment P3, the voltage VQB of the second node QB can be the first voltage level H. Thus, a voltage of the first voltage VGH can be provided to the back gate of the fourth transistor T4.

[0120] In an embodiment and referring to Figure 8B, the gate-source voltage Vgs of the fourth transistor T4 can be given by Vgs(T4)=2VGH-VGH and Vgs(T4)=VGH>0. In this case, the gate-source voltage Vgs of the fourth transistor T4 can become greater than the threshold voltage, and thus the current Ids can flow in the on state of the fourth transistor T4. Unlike when the fourth transistor T4 is off, the back gate-source voltage Vbs of the fourth transistor T4 can be given by Vbs(T4)=VGH-VGH and Vbs(T4)=0. Thus, the characteristics of the threshold voltage and the current-voltage graph of the fourth transistor T4, which are shifted in the positive direction, can be restored by moving to the left, and thus the current Ids can flow through the fourth transistor T4, which is on. Accordingly, through the fourth transistor T4, which is on, the first voltage VGH can be provided to the source electrode of the fourth transistor T4 connected to the output terminal OUT.

[0121] Figure 9A A state in which the second transistor T2 is turned on after the fourth section P4 is shown. In an embodiment, the source electrode of the second transistor T2 can be connected to the third node A. In the fourth section P4, the voltage of the previous output signal GS[k-1] of the low level L can be lowered by the threshold voltage Vth of the first transistor T1, which is a P-type transistor, and then can be transmitted to the third node A through the first transistor T1, which is on. In an embodiment, the voltage of the previous output signal GS[k-1] of the low level L can be the second voltage VGL. In this case, the voltage VA of the third node A can be given by VGL+|Vth|, which is smaller than the second voltage VGL by the threshold voltage Vth. The voltage VA of the third node A in the fourth section P4 (VGL+|Vth|) can also be maintained after the fifth section P5.

[0122] The gate of the second transistor T2 can be connected to the first voltage input terminal V1 to provide the first voltage VGH, and the back gate of the second transistor T2 can be connected to the second voltage input terminal V2 to provide the second voltage VGL.

[0123] Reference Figure 9B, the gate-source voltage Vgs of the second transistor T2 can be given by Vgs(T2) = VGH - (VGL + |Vth|) and Vgs > 0. In this case, the gate-source voltage Vgs of the second transistor T2 can become greater than the threshold voltage, and thus the current Ids can flow in the on state of the second transistor T2. Unlike when the second transistor T2 is off, the back gate-source voltage Vbs of the second transistor T2 in the on state can be Vbs(T2) = (VGL + |Vth|) - VGL and Vbs(T2) = |Vth| ≒ 0. Thus, as described below, the characteristics of the current-voltage graph of the forward-shifted second transistor T2 can be restored by moving to the left, and thus the current Ids can flow through the on second transistor T2. The voltage VA of the third node A can be transmitted to the first node Q through the on second transistor T2, and a voltage of VGL + |Vth| can be provided to the drain electrode of the second transistor T2.

[0124] Figure 10A An embodiment is shown in which the second transistor T2 is off in the first section P1, the second section P2, and the third section P3. The gate of the second transistor T2 can be connected to the first voltage input terminal V1 to provide the first voltage VGH, and the back gate of the second transistor T2 can be connected to the second voltage input terminal V2 to provide the second voltage VGL. In the embodiment, the source electrode of the second transistor T2 can be connected to the third node A. In the first section P1, the first voltage VGH, which is the previous output signal GS[k-1], can be transmitted to the third node A through the on first transistor T1. The high-level first voltage VGH transmitted to the third node A in the first section P1 can also be maintained in the second section P2 and the third section P3.

[0125] The drain electrode of the second transistor T2 can be connected to the first node Q. The first voltage VGH, which is the voltage VA of the third node A, can be transmitted to the first node Q through the on second transistor T2, and thus the fourth transistor T4 can be turned on.

[0126] In the embodiment and with reference to Figure 10B, the gate-source voltage Vgs of the second transistor T2 can be given by Vgs(T2) = VGH - VGH and Vgs(T2) = 0. The back gate-source voltage Vbs of the second transistor T2 can be given by Vbs(T2) = VGL - VGH and Vbs(T2) < 0. Thus, as the threshold voltage of the second transistor T2 is positively shifted, the current-voltage graph can be shifted to the right and the second transistor T2 can be turned off. The voltage VQ of the first node Q can be raised to a third voltage level HH by the coupling of the first capacitor C1. The voltage of the third voltage level HH can be given by 2VGH, which is about twice the first voltage VGH. Thus, a voltage of about 2VGH can be provided to the drain electrode of the second transistor T2.

[0127] Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12 、 Figure 13 and Figure 14 each show a circuit diagram showing an example of a stage included in a drive circuit according to an embodiment. Figure 3 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12 、 Figure 13 and Figure 14 each show various modifications of the circuit included in the stage STka of Figure 5 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12 、 Figure 13 and Figure 14 are the same as or partially different from a part of the circuit diagram shown in Figure 5 Figure 5

[0128] In an embodiment and with reference to Figure 11A , the stage STkb is an example in which a seventh transistor T7a is further included in the control circuit 131 of the stage STka shown in Figure 5

[0129] ​​​​​The seventh transistor T7a can be connected between the first node Q and the second voltage input terminal V2. The gate of the seventh transistor T7a can be connected to the second node QB. As such, when the voltage VQB of the second node QB is at a low level, the seventh transistor T7a can be turned on, and the second voltage VGL input through the second voltage input terminal V2 can be transmitted to the first node Q.

[0130] When the stage STkb further includes the seventh transistor T7a, because the second voltage VGL can be directly provided to the first node Q from the second voltage input terminal V2 even when the previous output signal GS[k-1] is at a low level, the voltage of the first node Q can be the second voltage VGL, instead of the voltage given by VGL+|Vth|, which is smaller than the second voltage VGL by the threshold voltage Vth, and the gate-source voltage Vgs of the fourth transistor T4 can be given by Vgs(T4)=0. Thus, the gate-source voltage Vgs of the fourth transistor T4 can be lower than |Vth| from the case shown in FIG. 7, and thus, the fourth transistor T4 can become a relatively stable off state. Figure 5

[0131] Figure 11B 、 Figure 11C and Figure 11D respectively show various modifications of the circuit included in the stage STkb of FIG. 6. Figure 11A

[0132] The stage STkb1 shown in FIG. 8 can be an example in which the sixth transistor T6, which is a reset transistor that initializes the voltage VA of the third node A to the second voltage VGL, is removed from the stage STkb of FIG. 6. Figure 11B Figure 11A The stage STkb2 shown in FIG. 9 can be an example in which the third capacitor C3, which stores the voltage difference between the first voltage input terminal V1 and the third node A, is removed from the stage STkb of FIG. 6.

[0133] Figure 11C Figure 11A The stage STkb3 shown in FIG. 10 can be an example in which both the sixth transistor T6 and the third capacitor C3 are removed from the stage STkb of FIG. 6.

[0134] Figure 11D The stage STkb4 shown in FIG. 11 can be an example in which the fourth transistor T4 is removed from the stage STkb of FIG. 6. Figure 11A

[0135] 、 Figure 11B and Figure 11C may be various implementations that can reduce the cost and dead zone by removing elements that do not affect the core operation of the circuit included in the stage STkb shown in FIG. 6. Figure 11D Figure 11A ​​​​​

[0136] In an embodiment and with reference to Figure 12 , the stage STkc can be one in which Figure 5 The output circuit 135 of the stage STka shown in FIG. 13 further includes an example of a seventh transistor T7b. In an embodiment, the seventh transistor T7b can be a P-type silicon transistor.

[0137] The seventh transistor T7b can be connected between a fourth node B and the output terminal OUT, where the fourth node B can be a node provided between the fifth transistor T5 and the seventh transistor T7b. The gate of the seventh transistor T7b can be connected to the second node QB, and the seventh transistor T7b can be turned on when the voltage VQB of the second node QB is at a low level. By connecting the seventh transistor T7b in series with the fifth transistor T5, a leakage current from the fifth transistor T5 that is turned off can be blocked when the first voltage VGH of a high level is output from the output terminal OUT for a long time. Thus, the defect rate of the display device 10 (see FIG. 1) can be reduced by preventing the leakage current from flowing into the output signal GS[k] that is output from the output terminal OUT. Figure 15

[0138] In an embodiment and with reference to Figure 13 , the stage STkd can be one in which a specific voltage is provided to Figure 5 An example in which a first specific voltage Cas1 is provided to the back gate of the second transistor T2 and a second specific voltage Cas2 is provided to the back gate of the fourth transistor T4 in the stage STka shown in FIG. 14. The first specific voltage Cas1 can be provided to the back gate of the second transistor T2, and the second specific voltage Cas2 can be provided to the back gate of the fourth transistor T4.

[0139] In an embodiment, the first specific voltage Cas1 can be the first voltage VGH. In this case, when the second transistor T2 is turned on, the back gate-source voltage Vbs can become Vbs(T2)=VGH-(VGL+|Vth|), and thus can become greater than Vbs(T2) in the case in which the second voltage VGL is provided to the back gate of the second transistor T2. Thus, the threshold voltage of the second transistor T2 can be negatively shifted, and thus, the current-voltage graph can be moved to the left, and the current Ids can flow relatively well. Also, when the second transistor T2 is turned off, because the back gate-source voltage Vbs becomes Vbs(T2)=VGH-VGH=0, the characteristics of the threshold voltage of the negatively shifted second transistor T2 and the current-voltage graph can be restored by moving to the right.

[0140] ​In this implementation, the first specific voltage Cas1 can be the voltage VA of the third node A. That is, the first specific voltage input terminal can be connected to the first terminal of the second transistor T2. In this case, the back gate-source voltage Vbs of the second transistor T2 can be given by Vbs(T2) = 0. Therefore, the second transistor T2 can be turned on and off according to the gate-source voltage Vgs.

[0141] In this implementation, the second specific voltage Cas2 can be a negative constant voltage (DC), and the value of the negative constant voltage (DC) applied as the second specific voltage Cas2 can be greater than the absolute value of the second voltage VGL (|VGL|). In this case, when the fourth transistor T4 is turned off, the back gate-source voltage Vbs can become Vbs(T4) < 0, and therefore the threshold voltage of the fourth transistor T4 can be positively shifted. As the characteristics of the current-voltage diagram of the fourth transistor T4 shift positively, the fourth transistor T4 can become a more stable off-state than in the case without a back gate.

[0142] In the implementation and reference Figure 14 STke can also be used in Figure 13 The control circuit 131 of stage STkd shown includes a seventh transistor T7c and an eighth transistor T8. In an embodiment, the seventh transistor T7c and the eighth transistor T8 may be P-type silicon transistors.

[0143] The seventh transistor T7c can be connected between the fifth node C and the second node QB. The fifth node C can be a node located between the third transistor T3 and the seventh transistor T7c. The gate of the seventh transistor T7c can be connected to the second voltage input terminal V2. The eighth transistor T8 can be connected between the fifth node C and the fifth voltage input terminal V3, and the fifth voltage VGL2 is provided through the fifth voltage input terminal V3. The gate of the eighth transistor T8 can be connected to the second node QB. In this embodiment, the fifth voltage VGL2 can be a low-level voltage L and can be equal to or different from the second voltage VGL. For example, the fifth voltage VGL2 can be lower than the second voltage VGL.

[0144] To output the second voltage VGL of the low level L from the output terminal OUT, the fourth transistor T4 should be stably turned off, and in this case, the voltage VQB of the second node QB connected to the back gate of the fourth transistor T4 should be maintained at 2VGL. Specifically, in the case of driving at a low frequency such as 1 Hz, the voltage VQB of the second node QB should be maintained at 2VGL for a long time to output the second voltage VGL of the low level L from the output terminal OUT. In this case, a leakage current can occur from the third transistor T3 in the off state, and thus, the voltage VQB of the second node QB can rise to about VGL. When the voltage VQB of the second node QB rises to about VGL, the fourth transistor T4 can not be completely turned off, and thus, since a voltage of not the second voltage VGL but VGL+|Vth| can be output from the output terminal OUT, a defect of the display device 10 (see Figure 15 ) can occur.

[0145] In an embodiment, the fifth voltage VGL2 of the low level L can be provided to a fifth node C between the third transistor T3 and the second node QB, and the seventh transistor T7c can be connected in series to the third transistor T3 to block a leakage current of the third transistor T3. The third transistor T3 and the seventh transistor T7c can be connected in series to each other to minimize the leakage current of the third transistor T3, and thus, the voltage of the second node QB can be stably maintained, and a defect rate of the display device 10 (see Figure 15 ) can be reduced.

[0146] Figure 15 is a diagram schematically illustrating a display device according to an embodiment.

[0147] In an embodiment and referring to Figure 15 , the display device 10 can include a pixel area 110, a gate driving circuit 130, a data driving circuit 150, a power supply circuit 170, and a controller 190.

[0148] The pixel area 110 can correspond to a display area in which an image is displayed. Various conductive lines for transmitting an electrical signal to be applied to the display area, a peripheral driving circuit electrically connected to a pixel circuit, and / or a pad to which a printed circuit board or a driver IC chip is attached can be located in a peripheral area (a non-display area) outside the display area. For example, the gate driving circuit 130, the data driving circuit 150, the power supply circuit 170, and the controller 190 can be disposed in the peripheral area.

[0149] A plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected thereto can be arranged in a pixel area 110. The plurality of pixels PX can be repeatedly arranged in a first direction (x direction or row direction) and a second direction (y direction or column direction). The plurality of pixels PX can be arranged in various forms such as a stripe arrangement, a pentile arrangement, a diamond arrangement, and a mosaic arrangement to implement an image. Each of the plurality of pixels PX can include an organic light emitting diode as a display element, and the organic light emitting diode can be connected to a pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor. The pixel PX can emit, for example, red light, green light, blue light, or white light from the organic light emitting diode (OLED). Each pixel PX can be connected to at least one corresponding gate line of the plurality of gate lines GL and a corresponding data line of the plurality of data lines DL.

[0150] In an embodiment, the plurality of transistors included in the pixel circuit can be P-type silicon transistors. In an embodiment, the plurality of transistors included in the pixel circuit can be N-type oxide transistors. In an embodiment, some of the plurality of transistors included in the pixel circuit can be P-type silicon transistors, and some other transistors thereof can be N-type oxide transistors.

[0151] In an embodiment, each of the gate lines GL can extend in the x direction (row direction) to be connected to the pixels PX located in the same row. Each of the gate lines GL can be configured to transmit a gate signal to the pixels PX in the same row. Each of the data lines DL can extend in the y direction (column direction) to be connected to the pixels PX located in the same column. Each of the data lines DL can be configured to transmit a data signal to each of the pixels PX in the same column in synchronization with the gate signal.

[0152] The gate driving circuit 130 can be connected to the plurality of gate lines GL, can generate a gate signal GSS in response to a gate driving control signal GCS from the controller 190, and can sequentially supply the gate signal GSS to the gate lines GL. The gate lines GL can be connected to gates of the transistors included in the pixels PX, and the gate signal GSS can be a gate control signal for controlling the turn-on and turn-off of the transistors to which the gate lines are connected. The gate signal GSS can include a gate turn-on voltage at which the transistors can be turned on and a gate turn-off voltage at which the transistors can be turned off. The gate driving circuit 130 can include a plurality of stages that sequentially generate and output the gate signal GSS.

[0153] In an embodiment, the gate driving circuit 130 can be implemented as Figure 3The gate signals GSS output to each of the gate lines GL by the gate drive circuit 130 can correspond to the output signals of a high level output to the signal lines by each of the plurality of stages ST1 to STn of the drive circuit DRV, for example. Each of the stages ST1 to STn can be connected to the gate lines arranged in the corresponding row of the pixel region 110. Each of the stages ST1 to STn can generate the gate signal GSS as the output signal and output the gate signal GSS to the connected gate line GL. That is, each of the stages ST1 to STn can supply the gate signal GSS of a high level to the gate line GL arranged in the corresponding row. In an embodiment, each of the stages ST1 to STn of the gate drive circuit 130 can be a stage STka shown in FIG. 13A, Figure 5 a stage STkb shown in FIG. 13B, Figure 11A a stage STkb shown in FIG. 13B, Figure 11B a stage STkb1 shown in FIG. 13C, Figure 11C a stage STkb2 shown in FIG. 13D, Figure 11D a stage STkb3 shown in FIG. 13E, Figure 12 a stage STkc shown in FIG. 13F, Figure 13 a stage STkd shown in FIG. 13G, or Figure 14 a stage STke shown in FIG. 13H.

[0154] The number of stages constituting the gate drive circuit 130 according to the embodiment can vary according to the number of rows (horizontal lines) arranged in the pixel region 110.

[0155] The data drive circuit 150 can be connected to the plurality of data lines DL and can supply the data signal DATA to the data lines DL in response to a data drive control signal DCS from the controller 190. The data signal DATA supplied to the data lines DL can be supplied to the pixels PX to which the gate signal GSS is supplied. The data drive circuit 150 can convert the input image data having the gradation input from the controller 190 into the data signal DATA in the form of voltage or current.

[0156] ​The power supply circuit 170 can generate signals (voltage and current) necessary to drive the pixels PX of the pixel region 110 in response to a power drive control signal PCS from the controller 190. When the display device 10 is an organic light emitting display device, the power supply circuit 170 can generate a first power voltage ELVDD and a second power voltage ELVSS, and supply them to the pixels PX. The first power voltage ELVDD can be a high-level voltage supplied to one terminal of a driving transistor connected to a first electrode (pixel electrode or anode) of an organic light emitting diode included in the pixel PX. The second power voltage ELVSS can be a low-level voltage supplied to a second electrode (opposite electrode or cathode) of the organic light emitting diode. The first power voltage ELVDD and the second power voltage ELVSS can be driving voltages for light emission of a plurality of pixels PX.

[0157] The power supply circuit 170 can generate the first voltage VGH, the second voltage VGL, and the fifth voltage VGL2 described above with reference to Figure 5 and Figure 14 The power supply circuit 170 can generate the first voltage VGH, the second voltage VGL, and the fifth voltage VGL2 described above with reference to Figure 3 , a plurality of clock signals CLK1 and CLK2 (see Figure 3 ), and an external signal FLM (see Figure 3 ), and supply them to the gate driving circuit 130.

[0158] The controller 190 can generate the gate driving control signal GCS, the data driving control signal DCS, and the power drive control signal PCS based on a signal inputted from the outside. The controller 190 can supply the gate driving control signal GCS to the gate driving circuit 130, supply the data driving control signal DCS to the data driving circuit 150, and supply the power drive control signal PCS to the power supply circuit 170.

[0159] Although Figure 15 the display device 10 independently includes the power supply circuit 170 and the controller 190, the present disclosure is not limited thereto. In an embodiment, the power supply circuit 170 can be included in the controller 190.

[0160] In an embodiment, the display device 10 can include a display panel, and the display panel can include a substrate in which the pixels PX can be arranged in a display area of the substrate. In a process of forming transistors constituting a pixel circuit in the display area of the substrate, a part or all of the gate driving circuit 130 can be directly formed in a peripheral area of the substrate. Each of the data driving circuit 150, the power supply circuit 170, and the controller 190 can be formed in a form of a separate integrated circuit chip or a single integrated circuit chip, and disposed on a flexible printed circuit board (FPCB) electrically connected to pads arranged on one side of the substrate. In other embodiments, the data driving circuit 150, the power supply circuit 170, and the controller 190 can be directly disposed on the substrate by using a chip on glass (COG) method or a chip on plastic (COP) method.

[0161] According to an embodiment, the driving circuit can use an NMOS charge pump (e.g., the second transistor T2, the fourth transistor T4, and the first capacitor C1) and a PMOS charge pump (e.g., the third transistor T3, the fifth transistor T5, and the second capacitor C2), and a back gate voltage of some NMOS transistors can be adjusted to secure a driving margin, reduce power consumption, and increase operational stability. According to an embodiment, a gate driving circuit capable of stably outputting a gate signal and reducing power consumption by reducing the number of signals provided to a stage, and a display device including the same, can be provided.

[0162] Effects of the present disclosure are not limited to the above-mentioned effects and various extensions can be made without departing from the spirit and scope of the present disclosure.

[0163] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure. In addition, embodiments or portions thereof can be combined together or combined in whole or in part with other embodiments or portions thereof, without departing from the scope of the present disclosure.

Claims

1. A driving circuit, characterized in that, The driving circuit includes multiple stages. Each of the plurality of levels includes: A first transistor is connected between a first node and a first terminal and includes a gate connected to a clock terminal, wherein a start signal is input through the first terminal and a clock signal is input through the clock terminal; A second transistor is connected between the first node and the second node and includes a first gate connected to a second terminal and a second gate connected to a third terminal, wherein a first voltage is provided through the second terminal and a second voltage is provided through the third terminal; A third transistor is connected between the first node and the third node and includes a gate connected to the third terminal; A fourth transistor is connected between the second terminal and the output terminal and includes a first gate connected to the second node and a second gate connected to the third node; A fifth transistor is connected between the third terminal and the output terminal and includes a gate connected to the third node; A first capacitor is connected between the second node and the output terminal; and The second capacitor is connected between the third node and the output terminal. Wherein, the first voltage is a high-level voltage, and the second voltage is a low-level voltage.

2. The driving circuit according to claim 1, characterized in that, The driving circuit also includes: A sixth transistor, connected between the first node and the third terminal and including a gate connected to a fourth terminal configured to provide a reset signal; and A third capacitor is connected between the first node and the second terminal.

3. The driving circuit according to claim 1, characterized in that, The first transistor, the third transistor, and the fifth transistor are P-type transistors, and The second transistor and the fourth transistor are N-type transistors.

4. The driving circuit according to claim 2, characterized in that, The starting signal includes an external signal or an output signal from the previous stage.

5. The driving circuit according to claim 2, characterized in that, The driving circuit also includes a seventh transistor connected between the output terminal and the fifth transistor and includes a gate connected to the third node.

6. The driving circuit according to claim 1, characterized in that, The clock signal alternates between a first voltage level and a second voltage level, and Wherein, the first voltage level is a high voltage level, and the second voltage level is a low voltage level.

7. The driving circuit according to claim 6, characterized in that, The clock signal input to the even-numbered clock terminals of the plurality of stages is shifted by half a cycle from the clock signal input to the odd-numbered clock terminals of the plurality of stages.

8. The driving circuit according to claim 7, characterized in that, In the first segment where the start signal of the first voltage level is input and the clock signal of the second voltage level is input, The voltages of the first node and the third node are at the first voltage level, and the voltage of the second node is at the third voltage level, wherein the third voltage level is higher than the first voltage level. When the fourth transistor is turned on, the first voltage level output signal is output from the output terminal through the fourth transistor.

9. The driving circuit according to claim 8, characterized in that, In the second segment following the first segment and wherein the start signal of the first voltage level is input and the clock signal of the first voltage level is input, The voltages of the first node and the third node are at the first voltage level, and the voltage of the second node is at the third voltage level. When the fourth transistor is turned on, the first voltage level output signal is output from the output terminal through the fourth transistor.

10. The driving circuit according to claim 9, characterized in that, In the third segment following the second segment, where the start signal of the second voltage level is input and the clock signal of the first voltage level is input, The voltages of the first node and the second node are at the first voltage level, and the voltage of the third node is at the third voltage level. When the fourth transistor is turned on, the first voltage level output signal is output from the output terminal through the fourth transistor.

11. The driving circuit according to claim 10, characterized in that, In the fourth segment following the third segment, where the start signal of the second voltage level is input and the clock signal of the second voltage level is input, The voltages of the first node and the second node are at the second voltage level, and the voltage of the third node is at the fourth voltage level, wherein the fourth voltage level is lower than the second voltage level. When the fifth transistor is turned on, the output signal of the second voltage level is output from the output terminal through the fifth transistor.

12. The driving circuit according to claim 11, characterized in that, In the fifth segment, following the fourth segment and wherein the start signal of the second voltage level is input and the clock signal of the first voltage level is input, The voltages of the first node and the second node are at the second voltage level, and the voltage of the third node is at the fourth voltage level. When the fifth transistor is turned on, the output signal of the second voltage level is output from the output terminal through the fifth transistor.

13. The driving circuit according to claim 1, characterized in that, The driving circuit further includes a sixth transistor connected between the second node and the third terminal and includes a gate connected to the third node.

14. A driving circuit, characterized in that, The driving circuit includes multiple stages. Each of the plurality of levels includes: A first transistor is connected between a first node and a first terminal and includes a gate connected to a clock terminal, wherein a start signal is input through the first terminal and a clock signal is input through the clock terminal; A second transistor is connected between the first node and the second node and includes a first gate connected to a second terminal and a second gate connected to a third terminal, wherein a first voltage is provided through the second terminal and a second voltage is provided through the third terminal; A third transistor is connected between the first node and the third node and includes a gate connected to a fourth terminal, through which a third voltage is provided; A fourth transistor is connected between the second terminal and the output terminal and includes a first gate connected to the second node and a second gate connected to the fifth terminal, through which a fourth voltage is provided; A fifth transistor is connected between the fourth terminal and the output terminal and includes a gate connected to the third node; A first capacitor is connected between the second node and the output terminal; and The second capacitor is connected between the third node and the output terminal. Wherein, the first voltage is a high-level voltage, and the third voltage is a low-level voltage.

15. The driving circuit according to claim 14, characterized in that, The driving circuit also includes: A sixth transistor, connected between the first node and the fourth terminal and including a gate connected to the sixth terminal, the sixth terminal being configured to provide a reset signal; and A third capacitor is connected between the first node and the second terminal.

16. The driving circuit according to claim 14, characterized in that, The driving circuit also includes: A seventh transistor, connected between the third transistor and the third node and including a gate connected to the fourth terminal; and An eighth transistor, connected between a fourth node and a seventh terminal, and including a gate connected to the third node, the fourth node being between the third and seventh transistors, wherein a fifth voltage is provided through the seventh terminal. The fifth voltage is lower than the third voltage.

17. The driving circuit according to claim 16, characterized in that, The first transistor, the third transistor, the fifth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and The second transistor and the fourth transistor are N-type transistors.

18. The driving circuit according to claim 14, characterized in that, The second voltage is equal to the first voltage.

19. The driving circuit according to claim 14, characterized in that, The third terminal is connected to the first node.

20. The driving circuit according to claim 14, characterized in that, The fourth voltage is a negative constant voltage with an absolute value larger than that of the third voltage.

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