MOSFET device

Abstract

The utility model discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises a drift layer with a first doping type, the drift layer comprises a first surface deviating from a substrate, source regions are arranged in the drift layer at intervals, the drift layer is provided with drift layer regions located between adjacent source regions, and each source region is provided with a first side surface in contact with the adjacent drift layer, a plurality of first injection regions and a plurality of second injection regions, the first injection regions are located in the drift layer region, each first injection region has a second doping type, the multiple first injection regions are arranged at intervals in the first direction, and the first direction is parallel to the first side face; the gate structure comprises a gate oxide layer and a gate, the gate oxide layer is located on the side, away from the substrate, of the drift layer region and located on the side, away from the substrate, of the partial source region, the gate oxide layer makes contact with the first injection region, and the gate is located on the side, away from the substrate, of the gate oxide layer. The utility model aims to solve the problems of low long-term reliability and increased on resistance of the MOSFET device in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOSFET device. Background Technology

[0002] The performance of traditional silicon-based semiconductor devices is gradually approaching the physical limits of the materials, while devices made using third-generation semiconductor materials, such as silicon carbide (SiC), possess superior capabilities including high frequency, high voltage, high temperature resistance, and radiation resistance. Due to the high critical breakdown electric field of SiC, SiC of the same thickness exhibits a higher breakdown electric field and lower on-resistance than Si. For SiC MOSFET devices, the high critical electric field of SiC, combined with the continuity of electric displacement, can lead to excessively high electric field strength at the oxide layer, potentially causing premature breakdown of the gate oxide layer, or a decrease in long-term device reliability due to the time-dependent breakdown effect of the oxide layer.

[0003] In addition, due to the different heat dissipation efficiencies in different areas of the chip, the central area of ​​the chip often exhibits a higher junction temperature. This means that silicon carbide MOSFET chips are still at risk of high-temperature failure even when the junction temperature in some areas has not reached its limit, which adversely affects the reliability of silicon carbide MOSFET devices. Utility Model Content

[0004] This application provides a MOSFET device to address the problems of low long-term reliability and increased on-resistance in related technologies.

[0005] According to one aspect of this application, a MOSFET device is provided, including a substrate and a drift layer and a plurality of source regions stacked on the substrate. The drift layer has a first doping type and includes a first surface facing away from the substrate. The source regions are spaced apart in the drift layer, and the surface of the source region facing away from the substrate is located in the first surface. The drift layer has a drift layer region located between adjacent source regions, and the source regions have a first side surface in contact with adjacent drift layers. The MOSFET device further includes: a plurality of first implantation regions located in the drift layer region, the first implantation regions having a second doping type, wherein the plurality of first implantation regions are spaced apart in a first direction parallel to the first side surface; and a gate structure including a gate oxide layer and a gate, the gate oxide layer being located on the side of the drift layer region facing away from the substrate and the gate oxide layer being located on the side of a portion of the source regions facing away from the substrate, the gate oxide layer contacting the first implantation region, and the gate being located on the side of the gate oxide layer facing away from the substrate.

[0006] Optionally, the width of the plurality of first injection regions gradually increases along the first direction.

[0007] Optionally, the spacing between any two adjacent first injection regions in the first direction decreases along the first direction.

[0008] Optionally, the drift layer regions are arranged in an array in the first direction and the second direction, where the second direction is the direction from the source region to the adjacent source region.

[0009] Optionally, in the drift layer region between any two adjacent source regions, there are m first injection regions along the second direction, where: m is an even number, and the width of the 1st to the m / 2nd first injection region decreases along the second direction, while the width of the (m / 2)+1th to the mth first injection region increases along the second direction; or m is an odd number, and the width of the 1st to the (m+1) / 2nd first injection region decreases along the second direction, while the width of the (m+1) / 2nd to the mth first injection region increases along the second direction.

[0010] Optionally, the first implantation region and a portion of the drift layer region located between any two adjacent first implantation regions constitute a first region. The gate oxide layer includes a first gate oxide region and a second gate oxide region. The first gate oxide region is located at least on the side of the first region away from the substrate, and the second gate oxide region is located at least on the side of the source region away from the substrate. In a third direction, the thickness of the first gate oxide region is greater than the thickness of the second gate oxide region, wherein the third direction is perpendicular to the first surface.

[0011] Optionally, the gate oxide layer has a second surface in contact with the first implantation region, the first gate oxide region has a first sub-surface located in the second surface, the second gate oxide region has a second sub-surface located in the second surface, and the distance from the first sub-surface to the substrate in the third direction is less than the distance from the second sub-surface to the substrate.

[0012] Optionally, the MOSFET device further includes: a plurality of second injection regions, the second injection regions being located on the side of the source region near the drift layer region, and each of the source regions being in contact with the second injection region, the second injection region being in contact with the gate oxide layer, and the second injection region having the first doping type.

[0013] Optionally, the projection of the first injection region in the fourth direction is located on the side of the second injection region that contacts the source region, wherein the fourth direction is perpendicular to the first side.

[0014] Optionally, the doping concentration of the second implantation region is greater than the doping concentration of the drift layer.

[0015] This invention provides a MOSFET device with multiple first injection regions in the JFET region. This reduces the gate-drain capacitance and improves dynamic characteristics. Simultaneously, it effectively reduces the peak electric field in the oxide layer during reverse blocking. Specifically, the first injection regions in the drift layer region (i.e., the JFET region) employ intermittent injection to balance the device's current-carrying characteristics. Furthermore, the multiple first injection regions are spaced apart along a first direction, shielding the gate electric field lines and reducing the gate-drain capacitance without significantly increasing the device's on-resistance. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 This is a cross-sectional structural schematic diagram of a first MOSFET device according to an embodiment of this application;

[0018] Figure 2 This is a cross-sectional structural schematic diagram of a second MOSFET device according to an embodiment of this application;

[0019] Figure 3 This is a cross-sectional structural schematic diagram of a third type of MOSFET device according to an embodiment of this application;

[0020] Figure 4 This is a cross-sectional structural schematic diagram of a fourth MOSFET device according to an embodiment of this application;

[0021] Figure 5 This is a top view of a first MOSFET device according to an embodiment of this application;

[0022] Figure 6 This is a top view of a second MOSFET device according to an embodiment of this application;

[0023] Figure 7 This is a top view of a third type of MOSFET device according to an embodiment of this application;

[0024] Figure 8 This is a top view of a fourth MOSFET device according to an embodiment of this application;

[0025] Figure 9 This is a top view of a fifth MOSFET device according to an embodiment of this application;

[0026] Figure 10 This is a top view of a sixth MOSFET device according to an embodiment of this application;

[0027] Figure 11 A flowchart illustrating the fabrication process of a MOSFET device according to an embodiment of this application is shown;

[0028] Figure 12 A flowchart illustrating the fabrication process of another MOSFET device according to an embodiment of this application is shown.

[0029] The above figures include the following reference numerals:

[0030] 10. Substrate; 20. Drift layer; 201. First surface; 202. Drift layer region; 203. First region; 30. Source region; 301. First heavily doped region; 302. Second heavily doped region; 303. Body region; 31. First side surface; 40. First implantation region; 50. Gate structure; 501. Gate oxide layer; 5011. First gate oxide region; 5012. Second gate oxide region; 502. Gate; 60. Second implantation region; 71. First conductive layer; 72. Second conductive layer. Detailed Implementation

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, products, or devices.

[0034] As described in the background section, in the prior art, for silicon carbide MOSFET devices, due to the high critical electric field of SiC, the electric field strength at the oxide layer is too high due to the continuity of electric displacement, which may lead to premature breakdown of the gate oxide layer, or the long-term reliability of the device may be reduced due to the breakdown effect of the oxide layer over time. In order to solve the above technical problems, this application provides a MOSFET device.

[0035] According to one aspect of this application, a MOSFET device is provided, such as... Figures 1 to 4 As shown, Figures 1 to 4 The diagram shows a cross-sectional view of the MOSFET device described above. The MOSFET device includes a substrate 10, a drift layer 20, and a plurality of source regions 30 stacked on the substrate 10. The drift layer 20 has a first doping type and includes a first surface 201 facing away from the substrate 10. The source regions 30 are spaced apart within the drift layer 20, with the surface of each source region 30 facing away from the substrate 10 located within the first surface 201. The drift layer 20 has drift layer regions 202 located between adjacent source regions 30, and each source region 30 has a contact area with an adjacent drift layer 20. The first side 31 of the MOSFET device further includes: a plurality of first implantation regions 40, each first implantation region 40 being located in a drift layer region 202 and having a second doping type; a gate structure 50, the gate structure 50 including a gate oxide layer 501 and a gate 502, the gate oxide layer 501 being located on the side of the drift layer region 202 facing away from the substrate 10 and the gate oxide layer 501 being located on the side of a portion of the source region 30 facing away from the substrate 10, the gate oxide layer 501 being in contact with the first implantation regions 40, and the gate 502 being located on the side of the gate oxide layer 501 facing away from the substrate 10; wherein, as Figures 5 to 9 As shown, Figures 5 to 9The diagram shows a top view of the MOSFET device. Multiple first injection regions 40 are spaced apart along a first direction A, parallel to the first side surface 31. These first injection regions are located within the drift layer region 202, which contacts the source region 30 on both sides along a second direction B. This MOSFET device, with multiple first injection regions in the JFET region, can reduce the gate-drain capacitance and improve dynamic characteristics. Simultaneously, it can effectively reduce the peak electric field in the oxide layer during reverse blocking. Furthermore, the multiple first injection regions spaced apart along the first direction can shield the gate electric field lines and reduce the gate-drain capacitance without significantly increasing the device's on-resistance.

[0036] Specifically, Figure 1 for Figures 5 to 8 A cross-sectional view of position aa′ in the top view of any MOSFET device structure shown. Figures 2 to 4 for Figure 9 The cross-sectional view of the MOSFET device structure shown in the top view at position bb′.

[0037] For example, Figure 1 for Figure 5 The cross-sectional view of position aa′ in the top view of the MOSFET device structure shown is as follows: Figure 5 As shown, in this MOSFET device, a plurality of first injection regions 40 are spaced apart in a first direction A, and the width of the first injection regions 40 in the first direction A is the same.

[0038] Junction Field Effect Transistor (JFET) utilizes an electric field effect to control the current flow in a semiconductor device, thereby controlling the device current. In this application, the drift layer region is a JFET structure, where the first implantation region and the drift layer have different doping types. When a reverse voltage is applied to the device, the first implantation region and the drift layer form a reverse-biased PN junction, which can shield the electric field at the corners of the source regions on both sides, thereby improving the reliability of the gate oxide layer. The doping concentration of the first implantation region is 1.0 × 10⁻⁶. 18 cm -3 ~1.0×10 20 cm -3 The specific doping concentration is not limited in this application.

[0039] In some alternative implementations, such as Figures 1 to 4As shown, the source region 30 includes a first heavily doped region 301, a second heavily doped region 302, and a body region 303. The body region 303 is located on the side of the drift layer 20 facing away from the substrate 10. The first heavily doped region 301 and the second heavily doped region 302 are arranged side-by-side in the body region 303, and the heavily doped region formed by the first heavily doped region 301 and the second heavily doped region 302 is isolated from the drift layer 20 by the body region 303. The first heavily doped region 301 and the body region 303 have the same second doping type, while the second heavily doped region 302, the substrate 10, and the drift layer 20 have the same first doping type. The body region 303 is in contact with the gate oxide layer 501, and a portion of the second heavily doped region 302 is also in contact with the gate oxide layer 501. In the MOFETS device's on-state, this structure forms a channel in the body region 303 in contact with the gate oxide layer, and the current regulation of the MOS device is achieved by controlling the gate voltage.

[0040] In some alternative embodiments, the first implantation region has a second doping type, and the first implantation regions are spaced apart along a first direction. The doping concentration of the first implantation region is 1.0 × 10⁻⁶. 18 cm -3 ~1.0×10 20 cm -3 The implantation width of the first implantation region is 0.1 μm to 1 μm, and the implantation depth is the same as the depth of the first heavily doped region. The sum of the widths of the multiple first implantation regions 40 in the first direction A does not exceed 1 / 2 of the width of the drift layer region. The specific parameters are not specifically limited in this application.

[0041] In the embodiments of this application, if the first doping type is P-type, then the second doping type is N-type, or if the first doping type is N-type, then the second doping type is P-type. N-type doping involves doping a semiconductor material with a pentavalent element, which includes, but is not limited to, phosphorus, arsenic, and antimony. P-type doping involves doping a semiconductor material with a trivalent element, which includes, but is not limited to, boron, aluminum, and gallium. The specific doping element is not specifically limited in this application.

[0042] Specifically, the orthographic projection of the first injection region on the surface where the substrate and the drift layer meet includes any one or more of the following: rectangle, square, circle, ellipse, triangle, and polygon. More specifically, the orthographic projections of multiple first injection regions on the surface where the substrate and the drift layer meet can be of the same shape, such as all being squares; or they can be a combination of different shapes, such as the orthographic projection of 1 / 2 of the first injection regions being in the positive direction and the orthographic projection of 1 / 2 of the first injection regions being a circle. This application does not make any specific limitation.

[0043] In some alternative implementations, the width of the plurality of first injection regions gradually increases along the first direction.

[0044] Specifically, such as Figure 6 As shown, the multiple first widths H1 increase progressively along the first direction A. In a MOSFET chip, the first direction A is the direction from the chip center to the chip edge. That is, in the JFET region of the MOSFET chip, the first widths H1 of the multiple first injection regions 40 gradually increase along the direction from the chip center to the chip edge. This is because different regions of the chip have different heat dissipation efficiencies. The central region of the chip often exhibits a higher junction temperature, which means that the silicon carbide MOSFET chip still faces the risk of high-temperature failure even when the junction temperature in some regions has not reached its limit, which will adversely affect the reliability of the silicon carbide MOSFET device. In the JFET region, the first injection regions are spaced apart in the epitaxial region, and the first width H1 gradually increases from the chip center to the chip edge. The contact area of ​​the PN junction formed by the first injection region 40 and the drift layer 20 also gradually increases. This design can increase the current-carrying area in the chip center region, reduce the temperature in the chip center region, reduce the risk of high-temperature failure of the chip, and increase the reliability of the device. The sum of the first widths H1 of the multiple first injection regions 40 in the first direction A does not exceed 1 / 2 of the width of the drift layer region 202.

[0045] In some alternative embodiments, the spacing between any two adjacent first injection regions in the first direction decreases along the first direction.

[0046] Specifically, such as Figure 7 As shown, the multiple first spacings D1 decrease along the first direction A. In a MOSFET chip, the first direction A is also the direction from the chip center to the chip edge. In the JFET region, the first injection regions 40 are spaced apart in the drift layer region 202, and the first spacing D1 gradually decreases from the chip center to the chip edge. This design can increase the current-carrying area in the chip center region and reduce the temperature in the chip center region. The sum of the widths of the multiple first injection regions 40 in the first direction A does not exceed 1 / 2 of the width of the drift layer region 202.

[0047] In some alternative embodiments, the spacing between any two adjacent first injection regions in the first direction decreases along the first direction, and the spacing between any two adjacent first injection regions in the first direction decreases along the first direction.

[0048] Specifically, such as Figure 8 As shown, multiple first widths H1 increase along the first direction A, and multiple first spacings D1 decrease along the first direction A. This design increases the current-carrying area in the chip's central region, further reducing the temperature in the chip's central region, lowering the risk of high-temperature chip failure, and increasing device reliability. The sum of the first widths H1 of the multiple first injection regions 40 along the first direction A does not exceed half the width of the drift layer region 202.

[0049] In some alternative implementations, the drift layer regions are arranged in an array in a first direction and a second direction, the second direction being the direction from the source region to the adjacent source region.

[0050] Specifically, such as Figures 2 to 4 and Figure 9 As shown, where, Figures 2 to 4 for Figure 9 The cross-sectional view at position bb′ in the top view of the MOSFET device structure shown. As shown in Figure 9, the first direction A is parallel to the first side surface 31, as... Figures 2 to 4 and Figure 9 As shown, the second direction B is the direction from source region 30 to the adjacent source region 30, where, as Figure 9 As shown, the first direction A is perpendicular to the second direction B. Figure 9 As shown, the drift layer region 202 includes a plurality of first injection regions 40 in the second direction B, and the plurality of first injection regions 40 are arranged at intervals in the second direction, that is, the first injection regions 40 are arranged in an array in the first direction A and the second direction B, which further reduces the gate-drain capacitance of the device, improves dynamic characteristics, and can effectively reduce the peak electric field in the oxide layer during reverse blocking. The sum of the widths of the plurality of first injection regions 40 in the second direction B is between 1 / 2 and 3 / 5 of the width of the drift layer region 202.

[0051] In some specific implementations, there are m first injection regions along the second direction in the drift layer region between any two adjacent source regions, where: m is an even number, the width of the first injection region to the m / 2th injection region decreases along the second direction, and the width of the (m / 2)+1th injection region to the mth injection region increases along the second direction; or m is an odd number, the width of the first injection region to the (m+1) / 2th injection region decreases along the second direction, and the width of the (m+1) / 2th injection region to the mth injection region increases along the second direction.

[0052] Specifically, such as Figure 9 and Figure 10As shown, each drift layer region 202 has m spaced first injection regions in the second direction B. The width of the first injection region 40 in the second direction B is the second width H2. Any two adjacent first injection regions 40 have a second spacing D2 in the second direction B. The second width H2 of the multiple first injection regions 40 increases from the middle of the drift layer region 202 to the first side surface 31. The cross section where the center of the drift layer region 202 is located is the surface where 1 / 2 of the width of the drift layer region 202 in the second direction B is located. This is because when the MOSFET device is turned on, the electric field in the middle region of the drift layer is smaller than the electric field on both sides of the drift layer. Carriers are more likely to accumulate on both sides of the drift layer. The contact area of ​​the PN junction formed by the first injection region located in the center of the drift layer and the drift layer is smaller than the contact area of ​​the PN junction formed by the first injection region located on both sides of the drift layer and the drift layer. The current flow area from the middle of the drift layer to both sides is increased, making it easier for carriers on both sides to flow, thereby reducing the gate-drain capacitance of the device and improving dynamic characteristics. At the same time, it can effectively reduce the peak electric field in the oxide layer during reverse blocking.

[0053] For example, such as Figure 10 As shown, there are three first injection regions 40 along the second direction B in the drift layer region. The second width H2 of the first injection region 40 is greater than the second width H2 of the second injection region 40, and the second width H2 of the second injection region 40 is less than the second width H2 of the third injection region 60.

[0054] In another example, such as Figure 9 As shown, there are four second injection regions 60 along the second direction B in the drift layer region 202. The second width H2 of the first injection region 40 is greater than the second width H2 of the second injection region 40, and the second width H2 of the third injection region 40 is less than the second width H2 of the fourth injection region 60. Figure 10 The positional relationships of the other structures shown in the figure are similar to those of the structures shown in the figure. Figure 9 The positional relationships of the structures are the same, so they will not be repeated here.

[0055] The difference in the second width of the first injection region in the second direction is 0.01 μm to 0.1 μm, and in each drift layer region, the second widths of the multiple first injection regions are symmetrical about the middle of the drift layer region.

[0056] In some alternative implementations, such as Figures 2 to 4As shown, the first implantation region 40 and the portion of the drift layer region 202 located between any two adjacent first implantation regions 40 constitute the first region 203. The gate oxide layer 501 includes a first gate oxide region 5011 and a second gate oxide region 5012. The first gate oxide region 5011 is located at least on the side of the first region 203 facing away from the substrate 10; the second gate oxide region 5012 is located at least on the side of the source region 30 facing away from the substrate 10. The thickness of the first gate oxide region 5011 in the third direction C is greater than the thickness of the second gate oxide region 5012. The third direction C is perpendicular to the first surface 201, and the second direction B is perpendicular to the third direction C. Additionally, as... Figure 1 As shown, if there is only one first implantation region 40 in the second direction B in the drift layer region 202, then the first gate oxide region 5011 is located at least on the side of the first implantation region 40 away from the substrate 10.

[0057] Specifically, MOSFET devices, as high-performance and reliable power devices, require high voltage withstand capability and low on-resistance to reduce operating losses and achieve high efficiency, environmental friendliness, and energy saving. However, due to the limitations of MOSFET device materials, the electric field of the gate oxide layer is too high. Even with the addition of a first injection region in the drift layer region to reduce the risk of gate oxide breakdown, the device still faces the risk of gate oxide breakdown during long-term use, reducing its reliability. By increasing the thickness of the gate oxide layer in contact with the first region, and the thinner thickness of the gate oxide layer in the channel contact region of the dual-source region, the voltage withstand capability and reliability of the gate oxide layer can be enhanced without increasing the device's threshold voltage and on-resistance.

[0058] The thickness of the first gate oxide region in the third direction is 50 nm to 300 nm, and the thickness of the second gate oxide region in the third direction is 50 nm to 80 nm. The material of the gate oxide layer includes, but is not limited to, any one or more of silicon oxide, silicon nitride, aluminum oxide (Al2O3), titanium oxide (TiO2), germanium oxide (GeO2), gallium oxide (Ga2O3), indium tin oxide (In2O5Sn), and hafnium oxide (HfO2), and this application does not make a specific limitation.

[0059] In some alternative implementations, such as Figures 1 to 3 As shown, the gate oxide layer 501 has a second surface in contact with the first implantation region 40, the first gate oxide region 5011 has a first sub-surface located in the second surface, and the second gate oxide region 5012 has a second sub-surface located in the second surface. The distance from the first sub-surface to the substrate 10 in the third direction C is less than the distance from the second sub-surface to the substrate 10. In some other alternative embodiments, such as... Figure 4As shown, the gate oxide layer 501 has a third surface facing away from the first implantation region 40. The first gate oxide region 5011 has a third sub-surface located within the third surface, and the second gate oxide region 5012 has a fourth sub-surface located within the third surface. The distance from the first sub-surface to the substrate 10 in the third direction C is greater than the distance from the second sub-surface to the substrate 10. Both embodiments employ different process steps to fabricate the gate oxide layer, both of which can enhance the withstand voltage and reliability performance of the gate oxide layer 501.

[0060] The drift layer region has a width of the third width in the second direction, and the first gate oxide region has a width of the fourth width in the second direction. The third width being greater than or equal to the fourth width can enhance the voltage resistance and reliability of the gate oxide layer.

[0061] In some alternative implementations, such as Figures 1 to 10 As shown, the MOSFET device further includes a plurality of second injection regions 60, wherein the second injection regions 60 are located on the side of the source region 30 near the drift layer region 202, and each source region 30 is in contact with the second injection region 60, as shown. Figures 1 to 4 As shown, the second implantation region 60 is in contact with the gate oxide layer 501, and the second implantation region 60 has a first doping type.

[0062] Specifically, the introduction of the first implantation region in the drift layer region forms a PN junction structure, increasing the on-resistance of the device. The second implantation region has a first doping type, and since it is located in the drift layer region and contacts the source regions on both sides, it can reduce the on-resistance of the drift layer region, thereby reducing the on-resistance of the device.

[0063] In some specific implementations, the projection of the first injection region in the fourth direction is located on the side where the second injection region contacts the source region, wherein the fourth direction is perpendicular to the first side and may coincide with the second direction.

[0064] Specifically, a second injection region is formed on the side where the source region contacts the drift layer region. The length of the second injection region in the first direction is greater than the length of the projection of multiple first injection regions in the drift layer region in the fourth direction. That is, in the first direction, the resistance introduced by the first injection region can be shared by the second injection regions located on both sides, which reduces the on-resistance of the device, reduces the abnormal increase in local resistance in the drift layer region, and makes the resistance in the drift layer more uniformly distributed.

[0065] In some other specific implementations, the doping concentration of the second implantation region is greater than the doping concentration of the drift layer.

[0066] Specifically, the second implantation region is in contact with the source region, and specifically, the second implantation region is in contact with the channel in the source region. The second implantation region has a large doping concentration, which makes the second implantation region have more free charge carriers. The more free charge carriers there are, the higher the conductivity is, thereby enhancing the conductivity of the channel and reducing the on-resistance of the device.

[0067] The doping concentration of the second implantation region is 1.0 × 10⁻⁶. 19 cm -3 ~1.0×10 21 cm -3 The width of the second injection region is 0.1μm to 0.5μm.

[0068] In some alternative implementations, such as Figures 1 to 4 As shown, the MOSFET device further includes: a first conductive layer 71 and a second conductive layer 72. The first conductive layer 71 is located on the side of the first heavily doped region 301 away from the substrate 10, and the first conductive layer 71 is located on the side of the second heavily doped region 302 adjacent to the first heavily doped region 301 away from the substrate 10; the second conductive layer 72 is located on the side of the substrate 10 away from the drift layer 20.

[0069] Specifically, the materials of the first conductive layer and the second conductive layer may include conductive materials, including but not limited to alloys of one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium. Those skilled in the art can make reasonable selections according to actual needs, and this application does not impose specific limitations.

[0070] The first conductive layer and the second conductive layer serve as the source electrode and drain electrode of the MOSFET device, respectively, and play the role of current input and output of the MOSFET device.

[0071] It should be noted that the use of this invention does not limit the voltage level of the MOSFET device. Therefore, the width of the body region, the width, depth, and concentration of the drift layer region all vary according to the voltage level. For example, for a 1200V MOSFET device, the body region depth is 0.6μm to 1.4μm, and the concentration is 1.0×10⁻⁶. 16 cm -3 ~5.0×10 17 cm -3 Within this range, the depth of the first and second doped regions is approximately 0.2 μm to 0.4 μm, and the concentration is 1.0 × 10⁻⁶. 19 cm -3 The drift layer region has a depth of approximately 0.6 μm to 1.4 μm and a concentration of 1.0 × 10⁻⁶. 16 cm -3 ~5.0×10 18 cm-3 The injection depths are approximately 0.2 μm to 0.4 μm, with a concentration of 1.0 × 10⁻⁶. 19 cm -3 above.

[0072] According to one embodiment of this application, such as Figure 11 As shown, the fabrication process of the above-mentioned MOSFET device may include the following steps:

[0073] Step S101: Provide a substrate;

[0074] Step S102: A drift layer is formed on one side of the substrate. The drift layer has a first doping type and includes a first surface facing away from the substrate.

[0075] Step S103: A plurality of source regions are formed in the drift layer, the source regions are spaced apart in the drift layer, the surface of the source region facing away from the substrate is located in the first surface, the drift layer has a drift layer region located between adjacent source regions, and the source region has a first side surface in contact with the adjacent drift layer.

[0076] Step S104: A plurality of first implantation regions are formed in the drift layer region. The first implantation regions have a second doping type. The plurality of first implantation regions are spaced apart in a first direction, which is parallel to the first side.

[0077] Step S105: Form a gate structure, which includes a gate oxide layer and a gate. The gate oxide layer is located on the side of the drift layer region away from the substrate and the gate oxide layer is located on the side of the source region away from the substrate. The gate oxide layer is in contact with the first implantation region and the gate is located on the side of the gate oxide layer away from the substrate.

[0078] Using the above-described fabrication process of the embodiments of this application, a multi-channel ion implantation process is used to form multiple first implantation regions arranged at intervals along the first direction in the drift layer region. This reduces the gate-drain capacitance of the device, improves dynamic characteristics, and effectively reduces the peak electric field in the oxide layer during reverse blocking. In particular, the P+ region of the JFET region adopts intermittent implantation and width gradient method to take into account the current carrying characteristics of the device and optimize the temperature distribution of the device.

[0079] According to another embodiment of this application, such as Figure 12 As shown, the fabrication process of the above-mentioned MOSFET device may include the following steps:

[0080] Step S401: Provide a substrate;

[0081] Step S402: A drift layer is formed on one side of the substrate, the drift layer having a first doping type, the drift layer including a first surface facing away from the substrate;

[0082] Step S403: A plurality of source regions are formed in the drift layer, the source regions are spaced apart in the drift layer, the surface of the source region facing away from the substrate is located in the first surface, the drift layer has a drift layer region located between adjacent source regions, and the source region has a first side surface in contact with the adjacent drift layer.

[0083] Step S404: A plurality of first implantation regions and a plurality of second implantation regions are formed in the drift layer region. The first implantation regions have a second doping type and the second implantation regions have a first doping type. The plurality of first implantation regions are spaced apart in a first direction, which is parallel to the first side. The second implantation regions are located on the side of the source region close to the drift layer region, and each source region is in contact with the second implantation region. The second implantation regions are in contact with the gate oxide layer.

[0084] Step S405: Form a gate structure, which includes a gate oxide layer and a gate. The gate oxide layer is located on the side of the drift layer region away from the substrate and the gate oxide layer is located on the side of the source region away from the substrate. The gate oxide layer is in contact with the first implantation region and the gate is located on the side of the gate oxide layer away from the substrate.

[0085] The fabrication process described in this application involves using a multi-channel ion implantation process to form a second implantation region and multiple first implantation regions spaced apart along a first direction in the drift layer region. The first implantation regions reduce the gate-drain capacitance of the device, improve dynamic characteristics, and effectively reduce the peak electric field in the oxide layer during reverse blocking. Specifically, the P+ region of the JFET region employs intermittent implantation with a gradually varying width to balance current conduction characteristics and optimize temperature distribution. Furthermore, the second implantation region has a first doping type and is located in the drift layer region, contacting both source regions on either side. This reduces drift layer depletion, increases current channels, and consequently lowers the on-resistance of the device.

[0086] Exemplary embodiments of the fabrication process of the MOSFET device according to this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited only to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0087] First, step S101 is performed: a substrate is provided.

[0088] Specifically, the substrate material may include silicon carbide, or it may include silicon, gallium nitride, gallium oxide, gallium arsenide, and aluminum nitride, etc. Those skilled in the art may make reasonable selections according to actual needs, without applying for specific limitations.

[0089] For example, the substrate material includes a doped SiC substrate to form a Schottky contact at the source, reducing the forward voltage drop of the MOSFET device and increasing the breakdown voltage.

[0090] After the step of providing the substrate, step S102 is performed: forming a drift layer on the substrate.

[0091] Specifically, the material of the drift layer may include silicon carbide, or it may include silicon, gallium nitride, gallium oxide, gallium arsenide, and aluminum nitride, etc. Those skilled in the art may make a reasonable selection according to actual needs, and no specific limitation is made hereby. The material of the drift layer may be the same as the material of the substrate, and the drift layer and the substrate may have the same doping type.

[0092] In some alternative implementations, the process of forming the drift layer includes, but is not limited to, deposition and epitaxial growth processes. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, making it easy to achieve the target doping distribution. This is not only applicable to silicon-based power devices, but can also avoid the difficulties of implantation doping in silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate, and has low cost. The deposition process includes, but is not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD). Physical Vapor Deposition (PVD) includes, but is not limited to, magnetron sputtering, reactive sputtering, DC sputtering, AC sputtering, vacuum coating, and arc evaporation. Chemical Vapor Deposition (CVD) includes, but is not limited to, Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal-Organic Chemical Vapor Deposition (MOCVD), and Laser-Induced Chemical Vapor Deposition (LCVD). Those skilled in the art can choose the appropriate process according to actual needs, and no specific limitations are imposed without application.

[0093] After the drift layer is formed, step S103 is performed to form the source region.

[0094] Specifically, the steps for forming the source region structure include: first, forming multiple third implantation regions in the drift layer using a doping process, wherein the third implantation regions are alternately located in the drift layer and extend from the first surface toward the substrate; then, implanting different types of dopant ions into the body region using a doping process to form a first heavily doped region and a second heavily doped region in contact, wherein the depth of the first heavily doped region and the second heavily doped region is less than the implantation depth of the body region, and the sum of the widths of the first heavily doped region and the second heavily doped region in the second direction is less than the width of the body region, wherein the first heavily doped region, the second heavily doped region and the body region constitute the source region.

[0095] The drift layer located between two adjacent source regions is called the drift layer region, which is in contact with the volume regions of the source regions on both sides.

[0096] Specifically, the processes for the first doped region, the second doped region, and the bulk region include, but are not limited to, ion implantation and diffusion processes. Ion implantation involves injecting a high-energy ion beam into a semiconductor material; it is a process where ions collide with semiconductor atoms and embed the ions into the semiconductor crystal. Ion implantation allows for precise control of concentration and depth, and can achieve ion doping at relatively low temperatures. However, ion implantation equipment is expensive, resulting in high costs. Diffusion, on the other hand, involves allowing impurity atoms to diffuse freely along the crystal's thermal gradient within the semiconductor under conditions of thermal equilibrium, through high temperatures or chemical reactions, to achieve doping. Diffusion does not require expensive equipment but requires precise control of temperature and time. It cannot precisely control the distribution and concentration of impurity atoms. Those skilled in the art can choose the appropriate method based on actual needs; no specific limitations are imposed.

[0097] After the source region is formed, step S104 is performed to form multiple first injection regions in the drift layer region.

[0098] Specifically, the first implantation region has a second doping type, and the first implantation regions are spaced apart along a first direction. The doping concentration of the first implantation region is 1.0 × 10⁻⁶. 18 cm -3 ~1.0×10 20 cm -3 The implantation width of the first implantation region is 0.1 μm to 1 μm, and the implantation depth is the same as the depth of the first heavily doped region. The sum of the widths of the multiple first implantation regions 40 in the first direction A does not exceed 1 / 2 of the width of the drift layer region.

[0099] Exemplary, specific, such as Figure 6As shown, the multiple first widths H1 increase incrementally along the first direction A. In the MOSFET chip, the first direction A is the direction from the chip center to the chip edge. That is, in the JFET region of the MOSFET chip, the first widths H1 of the multiple first injection regions 40 gradually increase along the direction from the chip center to the chip edge.

[0100] Another example, such as Figure 7 As shown, the multiple first spacings D1 decrease along the first direction A. In a MOSFET chip, the first direction A is also the direction from the chip center to the chip edge.

[0101] In another example, the plurality of first widths H1 increase along the first direction A, and the plurality of first spacings D1 decrease along the first direction A.

[0102] In some alternative embodiments, such as Figure 9 As shown, the first injection regions 40 are arranged at intervals along the second direction B. In the drift layer region 202 between any two adjacent source regions 30, there are m first injection regions 40 along the second direction B, where m is an even number. The width of the first injection region 40 to the m / 2th injection region 40 along the second direction B decreases, and the width of the (m / 2)+1th injection region 40 to the mth injection region 40 increases along the second direction B. The sum of the widths of the multiple first injection regions 40 along the second direction B is between 1 / 2 and 3 / 5 of the width of the drift layer region 202.

[0103] In some other alternative embodiments, such as Figure 10 As shown, the first injection regions 40 are arranged at intervals along the second direction B. In the drift layer region 202 between any two adjacent source regions 30, there are m first injection regions 40 along the second direction B, where m is an odd number. The width of the first first injection region 40 to the (m+1) / 2th first injection region 40 along the second direction B decreases along the second direction B, and the width of the (m+1) / 2th first injection region 40 to the mth first injection region 40 increases along the second direction B.

[0104] In some alternative implementations, step S104 further includes forming a second injection region.

[0105] Specifically, on the side where the source region contacts the drift layer region, an ion implantation process is used to implant a second implantation region, which contacts the source region. The projections of the first implantation regions in the fourth direction are all located on the side where the second implantation region contacts the source region, and the fourth direction is perpendicular to the first side. That is, the length of the second implantation region in the first direction A is greater than the length of the projections of multiple first implantation regions in the drift layer region in the fourth direction.

[0106] The second implantation region has a first doping type with a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 ~1.0×10 21 cm -3 The width of the second implantation region is 0.1 μm to 0.5 μm, and the implantation depth is the same as the depth of the second heavily doped region.

[0107] In the embodiments of this application, if the first doping type is P-type, then the second doping type is N-type, or if the first doping type is N-type, then the second doping type is P-type. N-type doping involves doping a semiconductor material with a pentavalent element, which includes, but is not limited to, phosphorus, arsenic, and antimony. P-type doping involves doping a semiconductor material with a trivalent element, which includes, but is not limited to, boron, aluminum, and gallium. The specific doping element is not specifically limited in this application.

[0108] In some specific implementations, the first implantation region and the first heavily doped region have the same doping type. In the fabrication process of the MOSFET device, the first implantation region and the first heavily doped region can be fabricated using the same implantation process, which reduces the number of process steps and lowers the process cost.

[0109] In some other specific implementations, the second implantation region and the second heavily doped region have the same doping type. Similarly, in the fabrication process of MOSFET devices, the same implantation process can be used to prepare the second implantation region and the second heavily doped region, reducing the process steps and lowering the process cost.

[0110] After the first injection region is formed, step S105 is performed to form the gate structure.

[0111] Specifically, the gate oxide layer includes a first gate oxide region and a second gate oxide region. The first gate oxide region is located at least on the side of the first region away from the substrate. The first region includes a first implantation region and a portion of the drift layer region located between any two adjacent first implantation regions. The second gate oxide region is located at least on the side of the source region away from the substrate. The thickness of the first gate oxide region is greater than the thickness of the second gate oxide region in the third direction, wherein the third direction is perpendicular to the first surface.

[0112] In some embodiments, the steps of forming the gate structure include: first, forming a first trench in a first region using an etching process; then, forming a gate oxide material layer in the first trench and on the surface of the semiconductor structure using a dry oxidation process and a deposition process; then, removing the gate oxide material layer located on a portion of the source region structure using an etching process, leaving the remaining gate oxide material layer as the gate oxide layer; and then, forming the gate on the surface of the gate oxide layer using a deposition process.

[0113] The depth of the first groove is 50nm to 300nm, and the width of the first groove in the second direction can be greater than the width of the first region and less than the width of the drift layer region, or the width of the first groove in the second direction can be equal to the width of the first region.

[0114] In other embodiments, the steps of forming the gate structure include: first, forming a first gate oxide layer on the semiconductor structure using a high-temperature dry oxidation process, wherein the first gate oxide layer includes a first sub-gate oxide layer, a second sub-gate oxide layer, and a third sub-gate oxide layer; the first sub-gate oxide layer includes a first gate oxide layer located on a first heavily doped region and a portion of a second heavily doped region adjacent to the first heavily doped region; the second sub-gate oxide layer includes a first gate oxide layer located on the remaining second heavily doped regions; and the third sub-gate oxide layer includes a first gate oxide layer located on a first region; then, removing the first sub-gate oxide layer using an etching process to expose the first heavily doped region and a portion of the second heavily doped region; then, etching away the second sub-gate oxide layer of different thicknesses using an etching process, leaving the remaining second sub-gate oxide layer as the second gate oxide region and the third sub-gate oxide layer as the first gate oxide region.

[0115] In some optional embodiments, the above preparation process further includes: step S1051: forming a first conductive layer and a second conductive layer.

[0116] Specifically, the steps for forming the first conductive layer include: firstly, forming a first dielectric layer on a semiconductor structure; then, using a deposition process to form a via extending through a first heavily doped region and a portion of a second heavily doped region adjacent to the first heavily doped region in the dielectric layer; then, using a deposition process to fill the via with conductive material to form the first conductive layer; and then, removing the remaining first dielectric layer.

[0117] Specifically, the steps for forming the second conductive layer include: first, thinning the substrate; and then, forming the second conductive layer on the side of the substrate away from the drift layer using a deposition process.

[0118] The materials of the first conductive layer and the second conductive layer may include conductive materials, including but not limited to alloys of one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium. Those skilled in the art can make reasonable selections according to actual needs, and this application does not impose specific limitations.

[0119] Specifically, the first conductive layer and the second conductive layer serve as the source electrode and drain electrode of the MOSFET device, respectively, and play the role of current input and output of the MOSFET device.

[0120] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes that element.

[0121] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A MOSFET device, characterized in that, The device includes a substrate and a drift layer and a plurality of source regions stacked on the substrate. The drift layer has a first doping type and includes a first surface facing away from the substrate. The source regions are spaced apart in the drift layer, and the surface of the source region facing away from the substrate is located in the first surface. The drift layer has drift layer regions located between adjacent source regions, and each source region has a first side surface in contact with an adjacent drift layer. The MOSFET device further includes: Multiple first implantation regions are located in the drift layer region and have a second doping type. The multiple first implantation regions are spaced apart in a first direction, which is parallel to the first side. A gate structure comprising a gate oxide layer and a gate, wherein the gate oxide layer is located on the side of the drift layer region away from the substrate and the gate oxide layer is located on the side of the source region away from the substrate, the gate oxide layer is in contact with the first implantation region, and the gate is located on the side of the gate oxide layer away from the substrate.

2. The MOSFET device according to claim 1, characterized in that, The width of the plurality of first injection regions gradually increases along the first direction.

3. The MOSFET device according to claim 1, characterized in that, The spacing between any two adjacent first injection regions in the first direction decreases along the first direction.

4. The MOSFET device according to claim 1, characterized in that, The drift layer regions are arranged in an array in the first direction and the second direction, where the second direction is the direction from the source region to the adjacent source region.

5. The MOSFET device according to claim 4, characterized in that, In the drift layer region between any two adjacent source regions, there are m first injection regions along the second direction, where: m is an even number, and the width of the first injection region to the m / 2th injection region decreases along the second direction, while the width of the (m / 2)+1th injection region to the mth injection region increases along the second direction; or m is an odd number. In the second direction, the width of the first injection region from the first injection region to the (m+1) / 2th first injection region decreases along the second direction, and the width of the first injection region from the (m+1) / 2th first injection region to the mth first injection region increases along the second direction.

6. The MOSFET device according to claim 1, characterized in that, The first injection region and the portion of the drift layer region located between any two adjacent first injection regions constitute a first region. The gate oxide layer includes a first gate oxide region and a second gate oxide region. The first gate oxide region is located at least on the side of the first region away from the substrate, and the second gate oxide region is located at least on the side of the source region away from the substrate. In a third direction, the thickness of the first gate oxide region is greater than the thickness of the second gate oxide region, wherein the third direction is perpendicular to the first surface.

7. The MOSFET device according to claim 6, characterized in that, The gate oxide layer has a second surface in contact with the first implantation region, the first gate oxide region has a first sub-surface located in the second surface, the second gate oxide region has a second sub-surface located in the second surface, and in the third direction, the distance from the first sub-surface to the substrate is less than the distance from the second sub-surface to the substrate.

8. The MOSFET device according to any one of claims 1 to 7, characterized in that, Also includes: Multiple second implantation regions are located on the side of the source region near the drift layer region, and each source region is in contact with a second implantation region. The second implantation region is in contact with the gate oxide layer, and the second implantation region has the first doping type.

9. The MOSFET device according to claim 8, characterized in that, The projection of the first injection region in the fourth direction is located on the side of the second injection region that contacts the source region, wherein the fourth direction is perpendicular to the first side.

10. The MOSFET device according to claim 8, characterized in that, The doping concentration of the second injection region is greater than the doping concentration of the drift layer.

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