PMOS (P-channel Metal Oxide Semiconductor) tube gate drive circuit

Abstract

The utility model provides a PMOS transistor gate drive circuit, which is used for controlling the conduction and cut-off of a PMOS transistor, and comprises a PMOS transistor, a clamping module, a charging module and a discharging module, the source electrode of the PMOS transistor is connected with direct current bus voltage, the drain electrode of the PMOS transistor is connected with the positive electrode of the input end of a load, the gate electrode of the PMOS transistor is respectively connected with the first end of the discharging module and the first end of the charging module, and the first end of the discharging module is connected with the second end of the PMOS transistor. The first end of the clamping module is connected with a PWM signal, the second end of the clamping module is connected with the second end of the charging module and the second end of the discharging module, and the third end of the discharging module is connected with the source electrode of the PMOS tube. According to the application, the selection of the charging module and the discharging module is correspondingly realized through the level of the PWM signal and the arrangement of the clamping module, so that the switching on and switching off of the PMOS tube are realized. According to the invention, the required cost is low, the duty ratio of 100% can be realized, and the use is flexible.

Description

TECHNICAL FIELD

[0001] The utility model relates to a circuit technical field especially relates to a PMOS pipe grid drive circuit. BACKGROUND

[0002] Metal-oxide-semiconductor field-effect transistor (MOS) is common in control system of each industry, and in high frequency and large current occasions, a special gate driver must be matched to drive the MOS pipe, especially in power supply, brushless motor control system. However, the cost of various gate drivers is relatively high. The following is a PMOS upper bridge arm drive circuit with 100% duty cycle.

[0003] That is, how to provide a PMOS pipe grid drive circuit with 100% duty cycle to achieve the technical effect of saving cost is a technical problem that needs to be solved in the field. UTILITY MODEL CONTENT

[0004] In view of the above problems, the utility model aims at providing a PMOS pipe grid drive circuit, which at least solves the above at least one technical problem.

[0005] The utility model provides a PMOS pipe grid drive circuit for controlling the conduction and cut-off of PMOS pipe, and the circuit comprises:

[0006] PMOS pipe Q3, clamping module, charging module and discharging module, the source electrode of PMOS pipe Q3 is accessed direct current bus voltage, the drain electrode of PMOS pipe Q3 is connected with the input positive pole of load, the grid of PMOS pipe Q3 is connected with the first end of discharging module and the first end of charging module respectively, the first end of clamping module is accessed PWM signal, the second end of clamping module is connected with the second end of charging module and the second end of discharging module respectively, the third end of discharging module is connected with the source electrode of PMOS pipe Q3.

[0007] Preferably, the clamping module comprises:

[0008] Conversion triode Q1, the emitter of conversion triode Q1 is grounded;

[0009] First resistance R1, one end of first resistance R1 is the first end of clamping module, the other end of first resistance R1 is connected with the base of conversion triode Q1;

[0010] Clamping diode D1, the anode of clamping diode D1 is connected with the collector of conversion triode Q1, and the cathode of clamping diode D1 is the second end of clamping module.

[0011] Preferably, the clamping module further comprises:

[0012] A second resistor R2, one end of the second resistor R2 is connected with the base of the conversion triode Q1, and the other end of the second resistor R2 is grounded.

[0013] Preferably, the discharging module comprises:

[0014] A discharging triode Q2, the base of the discharging triode Q2 is the second end of the discharging module, and the emitter of the discharging triode Q2 is the first end of the discharging module;

[0015] A discharging drive resistor R3, one end of the discharging drive resistor R3 is the third end of the discharging module, and the other end of the discharging drive resistor R3 is connected with the base of the discharging triode Q2;

[0016] A discharging deceleration resistor R4, one end of the discharging deceleration resistor R4 is connected with one end of the discharging drive resistor R3, and the other end of the discharging deceleration resistor R4 is connected with the collector of the discharging triode Q2.

[0017] Preferably, the charging module comprises:

[0018] A charging deceleration resistor R5, one end of the charging deceleration resistor R5 is the second end of the charging module;

[0019] A charging diode D2, the cathode of the charging diode D2 is connected with the other end of the charging deceleration resistor R5, and the anode of the charging diode D2 is the first end of the charging module.

[0020] Preferably, the discharging module further comprises:

[0021] A gate pull-down resistor R6, one end of the gate pull-down resistor R6 is connected with one end of the discharging deceleration resistor R4, and the other end of the gate pull-down resistor R6 is connected with the emitter of the discharging triode Q2.

[0022] Preferably, the clamping diode D1 is a reverse voltage stabilizing diode.

[0023] Preferably, the conversion triode Q1 and the discharging triode Q2 are both NPN triodes.

[0024] Preferably, the model numbers of the conversion triode Q1 and the discharging triode Q2 are both SS8050.

[0025] Preferably, the model number of the charging diode D2 is IN4148.

[0026] Compared with the prior art, the utility model has the beneficial effects that:

[0027] Specifically, the utility model provides a PMOS pipe gate drive circuit for driving the gate of PMOS pipe to control the conduction and cut off of PMOS pipe, and the gate drive circuit includes PMOS pipe Q3, clamping module, charging module and discharging module, the source of PMOS pipe Q3 is connected with direct current bus voltage, the drain of PMOS pipe Q3 is connected with the input positive pole of load, the gate of PMOS pipe Q3 is connected with the first end of discharging module and the first end of charging module respectively, the first end of clamping module is connected with PWM signal, the second end of clamping module is connected with the second end of charging module and the second end of discharging module respectively, the third end of discharging module is connected with the source of PMOS pipe Q3.

[0028] The above description is only a summary of the technical scheme of the utility model, in order to more clearly understand the technical means of the utility model, can be implemented according to the content of the specification, and in order to let the above and other purposes, characteristics and advantages of the utility model can be more obvious and easy to understand, the following specific embodiment of the utility model is described. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical scheme in the embodiment of the present application or prior art, the drawings needed in the embodiment will be briefly introduced as follows, obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained without creative labor under the premise of these drawings.

[0030] Figure 1 It is the connection schematic diagram of PMOS pipe gate drive circuit in the embodiment of the present application.

[0031] Reference signs:

[0032] 1, clamping module;

[0033] 2, charging module;

[0034] 3, discharging module. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present specification will be described clearly and completely in the following with reference to the drawings in the embodiments of the present specification. Obviously, the described embodiments are only part of the embodiments of the present specification, rather than all the embodiments. Based on the embodiments in the present specification, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present specification; wherein the keyword "and / or" involved in the present embodiment represents two cases of and or, in other words, A and / or B mentioned in the embodiments of the present specification represents two cases of A and B, A or B, which describes three states of A and B.

[0036] Meanwhile, in the embodiments of the present specification, when one component is considered to be "connected" to another component, it can be directly connected to the other component or a middle component can exist at the same time. When one component is considered to be "arranged on" another component, it can be directly arranged on the other component or a middle component can exist at the same time.

[0037] The embodiments of the present specification will be described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present specification from the content disclosed in the present specification. The present specification can also be implemented or applied through other different specific embodiments, and each detail in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present specification.

[0038] Embodiment one

[0039] Please refer to Figure 1 Specifically, in the embodiment of the PMOS gate drive circuit, the PMOS gate drive circuit provided by the present application is used to control the conduction and cutoff of the PMOS tube, and the gate drive circuit comprises: a PMOS tube Q3, a clamping module 1, a charging module 2 and a discharging module 3. The source of the PMOS tube Q3 is connected to the DC bus voltage, the drain of the PMOS tube Q3 is connected to the positive input end of the load, the gate of the PMOS tube Q3 is connected to the first end of the discharging module 3 and the first end of the charging module 2 respectively, the first end of the clamping module 1 is connected to the PWM signal, the second end of the clamping module 1 is connected to the second end of the charging module 2 and the second end of the discharging module 3 respectively, and the third end of the discharging module 3 is connected to the source of the PMOS tube Q3.

[0040] Specifically, the utility model provides a PMOS tube gate drive circuit for driving the gate of PMOS tube Q3 to control the conduction and cut -off of PMOS tube Q3, and the gate drive circuit comprises PMOS tube Q3, clamping module 1, charging module 2 and discharging module 3, the source of PMOS tube Q3 is connected with DC bus voltage, the drain of PMOS tube Q3 is connected with the positive pole of the input end of load, the gate of PMOS tube Q3 is connected with the first end of discharging module 3 and the first end of charging module 2 respectively, the first end of clamping module 1 is connected with PWM signal, the second end of clamping module 1 is connected with the second end of charging module 2 and the second end of discharging module 3 respectively, and the third end of discharging module 3 is connected with the source of PMOS tube Q3. The voltage range of the bus voltage output to the load is determined by clamping module 1, the charging conduction of PMOS tube Q3 is realized by charging module 2, the discharging cut -off of PMOS tube Q3 is realized by discharging module 3, the selection of charging module 2 and discharging module 3 is realized by the level of PWM signal and the setting of clamping module 1, and then the conduction and turn -off of PMOS tube Q3 are realized. The cost required by the application is lower, and 100% duty ratio can be realized, and the use is flexible, and the fine adjustment of each parameter can be realized because discrete devices are used.

[0041] The drain of PMOS tube Q3 in the application corresponds to the output positive pole (such as OUT+ in the attached Figure 1 , and the negative pole of the output of the circuit provided by the application is grounded and connected with the negative pole of the input end of load.

[0042] In a possible implementation, clamping module 1 comprises conversion triode Q1, first resistor R1 and clamping diode D1, the emitter of conversion triode Q1 is grounded, one end of first resistor R1 is the first end of clamping module 1 and is connected with PWM signal, the other end of first resistor R1 is connected with the base of conversion triode Q1, the anode of clamping diode D1 is connected with the collector of conversion triode Q1, and the cathode of clamping diode D1 is the second end of clamping module 1. Among them, clamping diode D1 is a reverse voltage stabilizing diode.

[0043] Specifically, the clamping module 1 of the application determines the voltage range of the output positive pole (OUT+ in the attached Figure 1 ), that is, the voltage range output to the load. In the application, the voltage range of DC bus voltage is 7V~25V, so when the clamping voltage is 0V, the voltage range output to the load through the DC bus is 7V~25V, and if the clamping voltage is 20V, the voltage range output to the load is 27~45V. In clamping module 1, first resistor R1 is used for current limiting, and the clamping voltage of clamping diode D1 determines the voltage range output to the load through the DC bus.

[0044] In a possible implementation, the clamping module 1 further includes a second resistor R2, one end of the second resistor R2 is connected with the base of the conversion triode Q1, and the other end of the second resistor R2 is grounded, so as to impede the current generated by the interference signal through the second resistor R2, thereby reducing the propagation of the interference signal in the circuit and reducing the influence of the interference signal on other parts of the circuit.

[0045] In a possible implementation, the discharging module 3 includes a discharging triode Q2, a discharging drive resistor R3 and a discharging deceleration resistor R4, the base of the discharging triode Q2 is the second end of the discharging module 3, and the emitter of the discharging triode Q2 is the first end of the discharging module 3; one end of the discharging drive resistor R3 is the third end of the discharging module 3, and the other end of the discharging drive resistor R3 is connected with the base of the discharging triode Q2; one end of the discharging deceleration resistor R4 is connected with one end of the discharging drive resistor R3, and the other end of the discharging deceleration resistor R4 is connected with the collector of the discharging triode Q2.

[0046] Further, the charging module 2 includes a charging deceleration resistor R5 and a charging diode D2, one end of the charging deceleration resistor R5 is the second end of the charging module 2; the cathode of the charging diode D2 is connected with the other end of the charging deceleration resistor R5, and the anode of the charging diode D2 is the first end of the charging module 2. The model of the charging diode D2 can be selected as IN4148.

[0047] Specifically, when the PWM signal is at a high level, the conversion triode Q1 is turned on, the discharging triode Q2 is turned off, the negative electrode level of the one-way charging diode D2 is the clamping voltage, the charging deceleration resistor R5 is the charging deceleration resistor of the PMOS tube Q3, so as to prevent the rising edge of the drain of the PMOS tube Q3 from being too fast to generate resonance through the charging deceleration resistor R5, and at this time, the PMOS tube Q3 is turned on; when the PWM signal is at a low level, the conversion triode Q1 is turned off, and the discharging triode Q2 is turned on, at this time, the PMOS tube Q3 is turned off, and the discharging deceleration resistor R4 is set to prevent the PMOS tube Q3 from being turned off too fast to generate resonance.

[0048] In a possible implementation, the discharging module 3 further includes a gate pull-down resistor R6, one end of the gate pull-down resistor R6 is connected with one end of the discharging deceleration resistor R4, and the other end of the gate pull-down resistor R6 is connected with the emitter of the discharging triode Q2, so as to pull down the gate voltage through the gate pull-down resistor R6, thereby ensuring the safety and reliability of the circuit.

[0049] In a possible implementation, the conversion triode Q1 and the discharging triode Q2 are both NPN triodes, and the model of the conversion triode Q1 and the discharging triode Q2 can be selected as SS8050.

[0050] The application is suitable for application in various multi-load occasions needing common ground (negative electrode), and can be used alone, and the duty ratio can reach 100%, such as being used in DC brush motor speed regulation, power converter and power control and other devices needing gate drive circuit, so as to realize gate drive at extremely low cost. The bus voltage range is wide, depends on the clamping voltage of the clamping module 1, the frequency can reach more than 100Khz, and the discrete devices used can be flexibly adjusted. In the circuit provided by the application, the resistance values of the first resistor R1, the second resistor R2, the discharge drive resistor R3, the discharge deceleration resistor R4, the charging deceleration resistor R5 and the gate pull-down resistor R6 are set to 2KΩ, 51KΩ, 5.1KΩ, 5.1KΩ, 10Ω, 10Ω and 5.1KΩ respectively.

[0051] It should be noted that the structures, proportions, sizes and the like shown in the drawings attached to the present specification are only used to cooperate with the content disclosed in the specification, so as to be understood and read by those skilled in the art, and do not have technical significance, any modification of structure, change of proportion relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the application, should still fall within the scope of the technical content disclosed by the application. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" in the present specification are only for the convenience of clear description, and are not used to limit the scope of the application, the change or adjustment of relative relationship without substantial change of technical content is also regarded as the scope of the application.

[0052] The above is only the preferred embodiment of the application, and does not limit the application in any form, although the application has been disclosed as above, however, it is not used to limit the application, any skilled person in the art can make some changes or modifications as equivalent embodiments without departing from the scope of the technical scheme of the application, as long as the content of the application is not deviated, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the application are still within the scope of the technical scheme of the application.

Claims

1. A PMOS transistor gate drive circuit for controlling the conduction and cutoff of a PMOS transistor, characterized in that, The circuit includes: The system comprises a PMOS transistor Q3, a clamping module, a charging module, and a discharging module. The source of the PMOS transistor Q3 is connected to the DC bus voltage, and the drain of the PMOS transistor Q3 is connected to the positive input terminal of the load. The gate of the PMOS transistor is connected to the first terminal of the discharging module and the first terminal of the charging module. The first terminal of the clamping module is connected to a PWM signal, and the second terminal of the clamping module is connected to the second terminal of the charging module and the second terminal of the discharging module. The third terminal of the discharging module is connected to the source of the PMOS transistor Q3.

2. The PMOS transistor gate drive circuit as described in claim 1, characterized in that, The clamping module includes: A switching transistor Q1 is used, and the emitter of the switching transistor Q1 is grounded; The first resistor R1 has one end as the first terminal of the clamping module and the other end as the base of the switching transistor Q1. Clamping diode D1, the anode of clamping diode D1 is connected to the collector of switching transistor Q1, and the cathode of clamping diode D1 is the second terminal of clamping module.

3. The PMOS transistor gate drive circuit as described in claim 2, characterized in that, The clamping module also includes: The second resistor R2 has one end connected to the base of the switching transistor Q1, and the other end grounded.

4. The PMOS transistor gate drive circuit as described in claim 3, characterized in that, The discharge module includes: The discharge transistor Q2 has its base at the second terminal of the discharge module and its emitter at the first terminal of the discharge module. The discharge driving resistor R3 has one end as the third terminal of the discharge module and the other end as connected to the base of the discharge transistor Q2. The discharge deceleration resistor R4 is connected at one end to one end of the discharge drive resistor R3, and at the other end to the collector of the discharge transistor Q2.

5. The PMOS transistor gate drive circuit as described in claim 4, characterized in that, The charging module includes: A charging deceleration resistor R5, one end of which is the second terminal of the charging module; The charging diode D2 has its cathode connected to the other end of the charging deceleration resistor R5, and its anode is the first terminal of the charging module.

6. The PMOS transistor gate drive circuit as described in claim 4, characterized in that, The discharge module further includes: A gate pull-down resistor R6 is provided, one end of which is connected to one end of the discharge deceleration resistor R4, and the other end of which is connected to the emitter of the discharge transistor Q2.

7. The PMOS transistor gate drive circuit as described in claim 2, characterized in that, The clamping diode D1 is a reverse Zener diode.

8. The PMOS transistor gate drive circuit as described in claim 4, characterized in that, Both the switching transistor Q1 and the discharge transistor Q2 are NPN transistors.

9. The PMOS transistor gate drive circuit as described in claim 8, characterized in that, Both the switching transistor Q1 and the discharge transistor Q2 are SS8050 models.

10. The PMOS transistor gate drive circuit as described in claim 5, characterized in that, The charging diode D2 is model number IN4148.

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