Circuit structure

Abstract

The present disclosure provides a circuit structure including a first bipolar junction transistor (BJT) formed on a superlattice structure, the first bipolar junction transistor having a first base, a first emitter, and a first collector; and a second bipolar junction transistor formed on the superlattice structure, the second bipolar junction transistor having a second base, a second emitter and a second collector, in which the first emitter is electrically coupled to the second base, and the first collector and the second collector are electrically coupled to each other.

Description

Technical Field

[0001] This utility model relates to a semiconductor device, and more particularly to a bipolar junction transistor device. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to miniaturize semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, FinFETs, and bipolar junction transistors (BJTs). This miniaturization has increased the complexity of semiconductor manufacturing processes. Utility Model Content

[0003] This disclosure provides a circuit structure including a first bipolar junction transistor (BJT) formed on a superlattice structure, the first BJT having a first base, a first emitter, and a first collector; and a second bipolar junction transistor formed on the superlattice structure, the second BJT having a second base, a second emitter, and a second collector, wherein the first emitter is electrically coupled to the second base, and the first collector and the second collector are electrically coupled to each other.

[0004] Furthermore, the superlattice structure is an alternating stack of multiple silicon layers and multiple silicon-germanium layers.

[0005] Furthermore, the first bipolar junction transistor and the second bipolar junction transistor are dual PNP type bipolar junction transistors.

[0006] Furthermore, the width ratio of the plurality of emitter regions, plurality of base regions, and plurality of collector regions of the first bipolar junction transistor and the second bipolar junction transistor is 1:5:1.

[0007] Furthermore, the first bipolar junction transistor and the second bipolar junction transistor are dual NPN bipolar junction transistors.

[0008] Furthermore, the width ratio of the plurality of emitter regions, plurality of base regions, and plurality of collector regions of the first bipolar junction transistor and the second bipolar junction transistor is 5:1:5.

[0009] Furthermore, the first base is electrically coupled to the first collector and the second collector.

[0010] Furthermore, the multiple emitter regions, multiple base regions, and multiple collector regions of the first bipolar junction transistor and the second bipolar junction transistor are located within the superlattice structure.

[0011] Furthermore, it also includes a metallization structure, which includes at least one rear metal layer and at least one front metal layer.

[0012] Furthermore, it also includes a well placement that separates the first bipolar junction transistor from the second bipolar junction transistor. Attached Figure Description

[0013] The embodiments disclosed herein will be better understood from the following embodiments and accompanying drawings. It should be noted that, in accordance with common industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased to make the discussion clearer and easier to understand.

[0014] Figure 1A-1 and Figure 1B-1 This is a cross-sectional view of a bipolar junction transistor as shown in some embodiments of the present disclosure.

[0015] Figure 1A-2 and Figure 1B-2 This is a cross-sectional view of a bipolar junction transistor as shown in some embodiments of the present disclosure.

[0016] Figure 2 As shown in some embodiments of this disclosure, it is used for manufacturing Figure 1A-1 , Figure 1A-2 , Figure 1B-1 and Figure 1B-2 The flowchart illustrates a method for using a bipolar junction transistor.

[0017] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 and Figure 7 As shown in some embodiments of this disclosure, Figure 1A-1 , Figure 1A-2 , Figure 1B-1 and Figure 1B-2 The diagram shows top plan views and cross-sectional views of bipolar junction transistors at various stages of their manufacturing process.

[0018] Figure 8 This is a circuit diagram of a Darlington circuit according to some embodiments of the present disclosure.

[0019] Figure 9 and Figure 10 These are cross-sectional and top plan views of a PNP bipolar junction transistor in a Darlington circuit configuration, as shown in some embodiments of this disclosure.

[0020] Figure 11 This is a circuit diagram of a Darlington circuit according to some embodiments of the present disclosure.

[0021] Figure 12 and Figure 13 These are cross-sectional and top plan views of an NPN bipolar junction transistor in a Darlington circuit configuration, as shown in some embodiments of this disclosure.

[0022] Symbol Explanation

[0023] 100A: PNP bipolar junction transistor

[0024] 100B: NPN bipolar junction transistor

[0025] 102: Substrate

[0026] 104: Dielectric layer

[0027] 105: Superlattice structure

[0028] 106: Emitter

[0029] 108: Base

[0030] 110: Collection

[0031] 112: n wells

[0032] 121: Nanostructure layer

[0033] 122: Nanostructure layer

[0034] 200: Method

[0035] 202-210: Operation

[0036] 402: N+ masking area

[0037] 404: Isolation Mask Area

[0038] 406: P+masking area

[0039] 600A: Dual Lateral Bipolar Junction Transistor

[0040] 600B: Dual Lateral Bipolar Junction Transistor

[0041] 602: p well

[0042] 604: n wells

[0043] 700: Multi-layer metallized structure

[0044] 702: Contact Layer

[0045] 704: Through hole

[0046] 706: First metal layer

[0047] 708: Second metal layer

[0048] 710: Third metal layer

[0049] 720: First rear metal layer

[0050] 722: Second rear metal layer

[0051] 724: Interlayer Dielectric

[0052] 726: Through-silicon via

[0053] 728: Oxide perforation

[0054] 800: Darlington Circuit Configuration

[0055] 1100: Darlington Circuit Configuration

[0056] B: Base

[0057] B1: Base Endon

[0058] B2: Base extremum

[0059] C: Collector

[0060] C1: Set of extreme subunits

[0061] C2: Set of extreme sub-units

[0062] E: Emitter

[0063] E1: emitter terminal

[0064] E2: Shooting End Pole

[0065] Wi: Width of placement

[0066] WN+: Planting width

[0067] WP+: Plant width Detailed Implementation

[0068] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and arrangements of this disclosure are described below for simplification. Naturally, these are merely examples and are not intended to limit this disclosure. For example, if the description shows a first feature formed on or above a second feature, it may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact.

[0069] Furthermore, this disclosure may use spatial relative terms such as “below,” “below,” “lower,” “above,” “above,” and similar words to describe the relationship between one element or feature and other elements or features in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be turned to different orientations, “rotated 64 degrees or other orientations,” and the spatial relative terms used herein will be interpreted accordingly.

[0070] In some embodiments of this disclosure, the terms "about" and "substantially" may refer to a given quantity that varies within 20% of that value (e.g., values ​​of ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20%). These values ​​are merely illustrative and not intended to limit this disclosure. The terms "about" and "substantially" may refer to a percentage of a value as understood by one of ordinary skill in the art based on the teachings of this disclosure.

[0071] It should be understood that the implementation section, rather than the summary section of this disclosure, is intended to be used to interpret the claims. The summary section of this disclosure may illustrate one or more, but not all, possible embodiments conceived by the inventors, and is therefore not intended to limit the claims in any way.

[0072] Bipolar junction transistors (BJTs) are used in integrated circuits to implement high-power devices, such as high-voltage switches, high-current switches, analog circuits, and radio frequency (RF) signal amplifiers for wireless applications (e.g., mobile phones and mobile computing). Low-power devices for logic and memory applications can be implemented as field-effect transistors (FETs), such as MOSFETs. BJTs are fabricated together with planar or two-dimensional FETs (e.g., MOSFETs or complementary MOSFETs) in a hybrid process known as bipolar complementary metal-oxide-semiconductor (BiCMOS). With the advent of FinFETs and gate-all-around FETs (GAAFETs), there has been a need for a fabrication process in which these three-dimensional FETs can be fabricated together with BJTs on a shared substrate. The structures and methods described herein use ion implantation to form emitter, base, and collector regions within a silicon (Si) / silicon-germanium (SiGe) stack compatible with the GAAFET process.

[0073] Figure 1A-1 , Figure 1A-2 , Figure 1B-1 and Figure 1B-2 According to some embodiments of this disclosure, examples of PNP and NPN bipolar junction transistors formed on Si / SiGe stacks are shown, respectively. Figure 1A-1 The top plan view of the top surface of the PNP bipolar junction transistor 100A is shown. Figure 1B-1 The top plan view of the top surface of the NPN bipolar junction transistor 100B is shown. Figure 1A-2 The corresponding cross-sectional view of the PNP bipolar junction transistor 100A is shown. Figure 1B-2 The corresponding cross-sectional view of the NPN bipolar junction transistor 100B is shown.

[0074] PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B can be formed side-by-side on the same substrate 102. A dielectric layer 104 can be deposited on the substrate 102 and followed by a superlattice structure 105. Each of the PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B includes an emitter 106, a base 108, and a collector 110, which are formed by implanting dopants into the superlattice structure 105. The PNP bipolar junction transistor 100A further includes an n-well 112, which is formed by implanting n-type dopants into the superlattice structure 105. The emitter 106, base 108, and collector 110 of the PNP bipolar junction transistor 100A are disposed in the n-well 112. In some embodiments of this disclosure, the emitter 106, base 108, and collector 110 of the NPN bipolar junction transistor 100B are not disposed in a well structure.

[0075] In some embodiments of this disclosure, the superlattice structure 105 may be formed as an alternating stack of nanostructure layers 121 (e.g., Si) and nanostructure layers 122 (e.g., SiGe). The superlattice structure 105 located in one region of the substrate 102 may be used to form one or more GAAFETs, while the superlattice structure 105 located in another region of the substrate 102 may be used to form one or more bipolar junction transistors. The two regions of the superlattice structure 105 carrying the GAAFET and the bipolar junction transistor may be adjacent to each other on the substrate 102, separated from each other in different regions of the same integrated circuit (IC) chip, or located on different IC chips formed on the substrate 102. The formation of the emitter 106, base 108, and collector 110 of the bipolar junction transistor within the superlattice structure 105 will be described in more detail below.

[0076] Figure 2 This is a flowchart illustrating a method 200 for manufacturing a PNP bipolar junction transistor 100A and an NPN bipolar junction transistor 100B, according to some embodiments of this disclosure. For illustrative purposes, Figure 2 The operation shown will refer to Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 and Figure 7The processes used to manufacture PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B are described, wherein... Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 and Figure 7 These are cross-sectional and top-view views of PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B at various manufacturing stages, as shown in some embodiments. Depending on the specific application, the operations of method 200 may be performed in different sequences, or not at all. It should be noted that method 200 may not produce a complete bipolar junction transistor. Therefore, it should be understood that additional processes may be provided before, during, or after method 200, and some of these additional processes may be briefly described herein.

[0077] Reference Figure 2 According to some embodiments of this disclosure, in operation 202, for both PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B, a dielectric layer 104 may be formed on the substrate 102, such as... Figure 3A and Figure 3B As shown.

[0078] As used herein, the term "substrate" describes a material on which subsequent material layers are added. The substrate may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Substrate 102 may be a bulk semiconductor wafer or a top semiconductor layer of a semiconductor-on-insulator (SOI) wafer (not shown), such as silicon-on-insulator. In some embodiments of this disclosure, substrate 102 may include a crystalline semiconductor layer with its top surface parallel to (100), (110), (111), or c-(0001) crystal planes. Alternatively, substrate 102 may be made of a non-conductive material, such as glass or sapphire wafers, or a plastic substrate. Substrate 102 may include one or more of a variety of semiconductor materials, such as, but not limited to, silicon (Si). In some embodiments of this disclosure, substrate 102 may include (i) elemental semiconductors, such as germanium (Ge); (ii) compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) alloy semiconductors, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) combinations thereof. Further, substrate 102 may be doped with p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or n-type dopant (e.g., phosphorus (P) or arsenic (As)). In some embodiments of this disclosure, different portions of substrate 102 may have opposite types of dopant.

[0079] In some embodiments of this disclosure, the dielectric layer 104 may include one or more of the following materials: silicon nitride (SiN), silicon dioxide (SiO2), carbon-doped SiO2, silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), tetraethyl orthosilicate (TEOS), low-k dielectrics such as fluorosilicate glass (FSG), spin-on dielectrics such as hydrosilsesquioxane (HSQ) and methylsilsesquioxane (MSQ), and combinations thereof. In some embodiments of this disclosure, the dielectric layer 104 may be formed using methods such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), flow-through chemical vapor deposition (FCVD), atomic layer deposition (ALD), electron beam evaporation, physical vapor deposition (PVD), spin coating, or any other suitable deposition process, and the resulting thickness may be between about 50 nanometers (nm) and about 70 nm. In some embodiments, the dielectric layer 104 may be a multilayer composite, such as a silicon layer having a thickness of about 50 nm and a dielectric layer having a thickness of about 10 nm.

[0080] Reference Figure 2 According to some embodiments of this disclosure, in operation 204, for both PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B, a superlattice structure 105 may be formed on the dielectric layer 104, such as... Figure 3A and Figure 3B As shown.

[0081] The superlattice structure 105 may include a stack of nanostructure layers 121 and 122 arranged in an alternating configuration. In some embodiments of this disclosure, nanostructure layer 121 comprises materials similar to each other, such as epitaxial Si, while nanostructure layer 122 comprises materials similar to each other, such as epitaxial SiGe. Although Figure 3A and Figure 3B Three nanostructure layers 121 (e.g., Si) and three nanostructure layers 122 (e.g., SiGe) are shown, but each superlattice structure 105 may include any number of nanostructure layers. The alternating configuration of the superlattice structures 105 can be achieved by alternating deposition or epitaxial growth of SiGe layers on top of SiGe layers, beginning with SiGe on dielectric layer 104. The Si layers can form nanostructure layers 121, which are interleaved with SiGe nanostructure layers 122. The thickness of each of the nanostructure layers 121 and 122 can range from about 1 nm to about 5 nm. In some embodiments of this disclosure, the topmost nanostructure layer (e.g., Si layer) of the superlattice structure 105 may be thicker than the underlying nanostructure layers.

[0082] After the first nanostructure layer 122 is formed on the dielectric layer 104, a stack of two different semiconductor layers constituting the superlattice structure 105 can be formed by an epitaxial growth process. The epitaxial growth process may include (i) chemical vapor deposition (CVD), such as low-pressure CVD (LPCVD), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), and other suitable CVD processes; (ii) molecular beam epitaxy (MBE); (iii) other suitable epitaxial processes; or (iv) combinations thereof. In some embodiments of this disclosure, the nanostructure layers 121 and 122 may be grown by an epitaxial deposition / partial etching process, which repeats the epitaxial deposition / partial etching process at least once. This epitaxial deposition / partial etching process is often referred to as a "cyclic deposition etch (CDE) process." In some embodiments of this disclosure, the nanostructure layers 121 and 122 may be grown by a selective epitaxial growth (SEG) process, in which an etching gas may be added to promote selective growth on the substrate 102 or the exposed semiconductor surface of the nanostructure layers 121 and 122, rather than directly on an insulating material (e.g., the material of the dielectric layer 104).

[0083] The superlattice structure 105 can be in-situ doped by introducing one or more precursors during the epitaxial growth process described above. For example, a stack of two different semiconductor layers can be in-situ doped using p-type doping precursors (e.g., diborane (B₂H₆) and boron trifluoride (BF₃)) during the epitaxial growth process. In some embodiments of this disclosure, a stack of two different semiconductor layers can be in-situ doped using n-type doping precursors (e.g., phosphine (PH₃) and arsene (AsH₃)) during the epitaxial growth process.

[0084] In some embodiments of this disclosure, the term "p-type" defines a structure, thin layer, and / or region as doped with, for example, boron (B), indium (In), or gallium (Ga). In some embodiments of this disclosure, the term "n-type" defines a structure, thin layer, and / or region as doped with, for example, phosphorus (P) or arsenic (As).

[0085] Reference Figure 2 According to some embodiments of this disclosure, in operation 206, the superlattice structure 105 may be doped to form emitter, base, and collector regions. Doping of the superlattice structure 105 can be accomplished by ion implantation through a mask, as in the case of an NPN bipolar junction transistor 100B. Figure 4A , Figure 4B , Figure 5B-1 and Figure 5B-2 As shown, and for PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B as... Figure 5A-1 , Figure 5A-2 , Figure 5B-1 and Figure 5B-2 As shown. In some embodiments of this disclosure, instead of in-situ doping during the deposition of nanostructure layers 121 and 122, or in addition to in-situ doping during the deposition of nanostructure layers 121 and 122, the superlattice structure 105 may be doped after its complete formation. An annealing process may follow the doping operation to repair damage to the surrounding lattice.

[0086] Figure 4A It reproduced Figure 1B-1 The top view of the NPN bipolar junction transistor 100B shown includes three photoresist masking regions: an N+ masking region 402, an isolation masking region 404, and a P+ masking region 406. The isolation masking region 404 separates the N+ masking region 402 from the P+ masking region 406. Each masking region is associated with a corresponding fabrication width W. N+ W i and W P+ Related, such as Figure 4A As shown. Planting width W N+ The width of the N+ shielding region 402 is through which negative ions are implanted into the superlattice structure 105 to form the regions of emitter 106 and collector 110, respectively; the implantation width W P+ The width of the P+ masking region 406 is through which positive ions are implanted into the superlattice structure 105 to form the base 108; and the implantation width W i To isolate the width of the masking region 404, no implantation occurs through it in the superlattice structure 105.

[0087] like Figure 5A-1 , Figure 5A-2 , Figure 6A-1 and Figure 6A-2 As shown, p-well and n-well regions can be formed in a similar manner by implanting a superlattice structure 105, wherein the implantation of the superlattice structure 105 uses a photoresist mask designed for well implantation, as described below. Compared to the emitter, base, and collector regions, wells occupy a larger area and are doped with a lower ion concentration. When wells are present, for example in a PNP bipolar junction transistor 100A, the implantation width W between terminals is... i The background concentration in the region is substantially equal to the concentration of the well-planted vegetation.

[0088] Reference Figure 4AIn some embodiments of this disclosure, the planting width W N+ :W i :W P+ The ratio can be in the range of about 4:3:1 to about 6:2:1. In some embodiments of this disclosure, the region of the superlattice structure implanted with n-type dopant can be wider than the region of the superlattice structure implanted with p-type dopant. In some embodiments of this disclosure, the undoped width W between the terminals of the bipolar junction transistor is... i The region can be approximately half the width of the doped region corresponding to the emitter and collector terminals. (See reference...) Figure 4A , Figure 5B-1 and Figure 5B-2 In some embodiments of this disclosure, the width ratio of the emitter, base, and collector regions in the NPN bipolar junction transistor 100B can be approximately 5:1:5. (See also...) Figure 5A-1 and Figure 5A-2 In some embodiments of this disclosure, in the PNP bipolar junction transistor 100A, the width ratio of the emitter, base, and collector regions can be approximately 1:5:1. The emitter region's placement width W... N+ The emitter injection rate and recombination rate are determined, which in turn determine the charge carrier flow through the NPN bipolar junction transistor 100B. Therefore, the implantation width W of the emitter 106... N+ This directly affects the overall performance of the NPN bipolar junction transistor 100B. For example, when the NPN bipolar junction transistor 100B is used as an amplifier, the placement width ratio W... N+ :W i :W P+ It can determine the amplifier's gain.

[0089] Figure 4B It reproduced Figure 1B-2 A portion of the cross-sectional view of the NPN bipolar junction transistor 100B shown, and corresponding to Figure 4A The top view shown is shown in the diagram. Figure 4B This includes a superimposed map of the ion concentrations in the implanted emitter, base, and collector regions. The emitter 106 and collector 110, implanted with n-type dopant, can have an ion concentration of approximately 1.71 × 10⁻⁶. 17 cm -3 From approximately 1.0 × 10 20 cm -3 The negative ion concentration is within a certain range. The base 108, implanted with p-type dopant, can have a negative ion concentration of approximately 1.71 × 10⁻⁶. 17 cm-3 From approximately 1.0 × 10 20 cm -3 The positive ion concentration is within a certain range. The isolation region is formed as a nanostructure layer 121 (e.g., Si) on top between the base 108 and each of the emitter 106 and collector 110, and has a substantially zero ion concentration.

[0090] Figure 5A-1 , Figure 5A-2 , Figure 5B-1 and Figure 5B-2 The diagram shows a cross-sectional view of the superlattice structure 105 after ion implantation of the emitter 106, base 108, and collector 110 regions of both PNP bipolar junction transistor 100A and NPN bipolar junction transistor 100B. Figure 5B-1 and Figure 5B-2 It shows that it has been used as Figure 4A The emitter / base / collector implants are fabricated using the photoresist mask, N+ mask region 402, isolation mask region 404, and P+ mask region 406. The width of the photoresist mask (implementation width) W N+ W i W P+ Defined Figure 5B-1 and Figure 5B-2 The width of the planted area shown in both figures.

[0091] Reference Figure 2 According to some embodiments of this disclosure, in operation 208, the superlattice structure 105 may be further doped by ion implantation to form doped wells. An NPN device may be disposed in a p-type region or a p-well of the substrate 102. A PNP device may be disposed in an n-type region or an n-well of the substrate 102. In some embodiments of this disclosure, one or both of the PNP bipolar junction transistor 100A and the NPN bipolar junction transistor 100B include well implantation. For example, Figure 5A-1 and Figure 5A-2 The diagram shows an n-well 112 containing a PNP bipolar junction transistor 100A, while no well is embedded around the NPN bipolar junction transistor 100B. Annealing can be performed after the well embedding operation to repair damage to the surrounding lattice.

[0092] In some embodiments of this disclosure, well placement, such as n-well 112, can be performed first, followed by emitter / base / collector placement, such that operation 208 can be performed first, followed by operation 206. In some embodiments of this disclosure, well placement is performed in a manner similar to emitter / base / collector placement, using a photoresist mask as previously described. In some embodiments of this disclosure, the N and P ion concentrations of the well placement are lower than the N+ and P+ ion concentrations of the emitter / base / collector placement.

[0093] Figure 6A-1 , Figure 6A-2 , Figure 6B-1 and Figure 6B-2 Dual lateral bipolar junction transistors 600A and 600B are shown, respectively, in which the superlattice structure 105 has been doped with n-wells, p-wells, and emitter / base / collector implantations. A pair of PNP bipolar junction transistors 100A form the dual lateral bipolar junction transistor 600A, as shown. Figure 6A-1 and Figure 6A-2 As shown. Similarly, a pair of adjacent NPN bipolar junction transistors 100B form a dual lateral bipolar junction transistor 600B, as shown. Figure 6B-1 and Figure 6B-2 As shown. In some embodiments of this disclosure, the placement sequence for forming the dual lateral bipolar junction transistors 600A and 600B begins with a p-well placement, followed by an n-well placement, an N+ placement, and a P+ placement. This placement sequence requires four separate placement operations, each using a different photoresist mask. See also... Figure 6A-1 and Figure 6A-2 Each bipolar junction transistor 100A constituting a dual lateral bipolar junction transistor 600A is disposed in an n-well 112. This pair of bipolar junction transistors 100A is separated by a p-well 602. (Refer to...) Figure 6B-1 and Figure 6B-2 The bipolar junction transistors 100B constituting the dual lateral bipolar junction transistor 600B are not placed in the well, but the pair of bipolar junction transistors 100B are separated by n wells 604.

[0094] Reference Figure 2 According to some embodiments of this disclosure, in operation 210, regarding Figure 7In this embodiment, a multilayer metallization structure 700 is formed for use as a bipolar junction transistor (BJT). In some embodiments of this disclosure, the multilayer metallization structure 700 provides a connection to the BJT 100B via a front-side metal layer and a back-side metal layer. On the front side of the substrate 102, a contact layer 702, a via 704, a first metal layer 706, a second metal layer 708, a third metal layer 710, etc., may be present. In some embodiments, after device formation, the substrate 102 is removed, such that the superlattice structure 105 is positioned above the back-side dielectric.

[0095] In some embodiments of this disclosure, back-side metallization is used to connect the bipolar junction transistor 100B to a pad, for example, via a first back-side metal layer 720 and a second back-side metal layer 722 coupled through a via 704. The front and / or back-side metal lines may be made of materials such as aluminum, copper, or alloys thereof. The first metal layer 706, second metal layer 708, third metal layer 710, first back-side metal layer 720, and second back-side metal layer 722 may include liner materials, for example, made of titanium (Ti) and / or titanium nitride (TiN). The multilayer metallization structure 700 may be formed as a damascene structure or a patterned metal structure, wherein the metal lines are insulated from each other by an interlayer dielectric (ILD) 724. The first rear metal layer 720 and the second rear metal layer 722 on the rear side can be coupled to the first metal layer 706, the second metal layer 708 and the third metal layer 710 on the front side using one or both of a through-silicon via (TSV) 726 and a through-oxide via (TOV) 728.

[0096] Reference Figure 8 According to some embodiments of this disclosure, a Darlington circuit configuration 800 is formed. In some embodiments of this disclosure, dual lateral bipolar junction transistors 600A of PNP transistors can be coupled through a multilayer metallization structure 700 to form the Darlington circuit configuration 800. A circuit diagram of the Darlington circuit configuration 800 composed of two PNP bipolar junction transistors is shown below. Figure 8 As shown, the emitter, base, and collector of the Darlington circuit configuration 800 are represented by E, B, and C, respectively. The Darlington circuit configuration 800, formed using a PNP bipolar junction transistor, in... Figure 8The arrows pointing away from the emitter terminal are used to indicate this. In the Darlington circuit configuration 800, the base terminal B1 and collector terminal C1 of the first PNP bipolar junction transistor are coupled to the collector terminal C2 of the second PNP bipolar junction transistor, and the emitter terminal E1 of the first PNP bipolar junction transistor is coupled to the base terminal B2 of the second PNP bipolar junction transistor. Therefore, the entire Darlington circuit configuration can have an emitter current equal to the emitter current (emitter terminal E2) of the second PNP bipolar junction transistor, a base current equal to the base current of the first PNP bipolar junction transistor, and a collector current equal to the sum of the two collector currents. Figure 8 The base B of the Darlington circuit is coupled to the collector C.

[0097] The gain of the Darlington circuit configuration 800 is calculated as 2β + β. 2 Where β is the gain of a single bipolar junction transistor (BJT). Therefore, if β = 1 for a single BJT, the gain of a Darlington circuit configuration 800 is 3. That is, when coupled using a Darlington circuit configuration, the gain of two BJTs is three times that of a single BJT. The gain of a BJT is defined as the ratio of the collector current to the base current, or β = I... c / I b In the Darlington circuit configuration, I C For two collector currents I C1 with I C2 The sum of, and the base current is I b1 Therefore, when β1 = β2 = β:

[0098]

[0099] In some embodiments of this disclosure, the Darlington circuit configuration 800 is implemented as a temperature sensor with a temperature coefficient TC two to three times greater due to the 3x gain of the Darlington circuit configuration. Furthermore, the compact design of the ion-embedded dual lateral bipolar junction transistors 600A / 600B described above is particularly suitable for implementation as the Darlington circuit configuration 800.

[0100] Reference Figure 9 and Figure 10 According to some embodiments of this disclosure, a PNP dual lateral bipolar junction transistor 600A is connected in a Darlington circuit configuration 800. Figure 9 This diagram shows a cross-sectional view of how a PNP dual lateral bipolar junction transistor 600A can be wired to configure a Darlington circuit 800. Figure 9 This is a top plan view showing how a PNP dual lateral bipolar junction transistor 600A can be wired to configure a Darlington circuit 800. Figure 9 and Figure 10 Three types of connections are made: First, the collector terminals C1 and C2 of the two PNP bipolar junction transistors are connected together as the output collector; second, the base of the second PNP bipolar junction transistor is coupled to the emitter of the first PNP bipolar junction transistor; third, the base B of the Darlington circuit is coupled to the collector C.

[0101] Reference Figure 11 According to some embodiments of this disclosure, a Darlington circuit configuration 1100 is formed. In some embodiments of this disclosure, NPN dual lateral bipolar junction transistors 600B can be coupled through a multilayer metallization structure 700 to form the Darlington circuit configuration 1100. A circuit diagram of the Darlington circuit configuration 1100 composed of two NPN bipolar junction transistors is shown in [the diagram]. Figure 11 In the Darlington circuit configuration 1100, the emitter, base, and collector are represented by E, B, and C, respectively. The Darlington circuit configuration 1100, formed using an NPN bipolar junction transistor, in... Figure 11 The arrow pointing towards the emitter terminal is used to indicate this. In the Darlington circuit configuration 1100, the base terminal B1 and collector terminal C1 of the first NPN bipolar junction transistor are coupled to the collector terminal C2 of the second NPN bipolar junction transistor, and the emitter terminal E1 of the first NPN bipolar junction transistor is coupled to the base terminal B2 of the second NPN bipolar junction transistor. Therefore, the entire Darlington circuit configuration can have an emitter current equal to the emitter current of the second bipolar junction transistor, a base current equal to the base current of the first NPN bipolar junction transistor, and a collector current equal to the sum of the two collector currents. Figure 11 The base B of the Darlington circuit is not coupled to the collector C.

[0102] Reference Figure 12 and Figure 13 According to some embodiments of this disclosure, the NPN dual lateral bipolar junction transistor 600B is connected in a Darlington circuit configuration 1100. Figure 12 This diagram shows a cross-sectional view of how an NPN dual lateral bipolar junction transistor 600B can be wired to configure a Darlington circuit 1100. Figure 13 This is a top plan view showing how an NPN dual lateral bipolar junction transistor 600B can be wired to configure a Darlington circuit 1100. Figure 12 and Figure 13Two connections are made: First, the collector terminals C1 and C2 of the two NPN bipolar junction transistors are connected together as the output collector; second, the base of the second NPN bipolar junction transistor is coupled to the emitter of the first NPN bipolar junction transistor. In Darlington circuit configuration 1100, the base B of the Darlington circuit is not coupled to the collector C.

[0103] Bipolar junction transistors (BJTs) formed on a superlattice structure of stacked silicon and silicon-germanium layers can coexist with GAAFETs on the same substrate. The superlattice structure can be ion-planted to form wells, as well as the emitter, base, and collector regions of the BJT. Dual NPN and PNP configurations can be formed as wells with separated pairs of transistors. Changing the width ratio of the planted regions can adjust the device performance. The resulting BJT structure is compact and efficient. Dual BJTs formed on superlattice structures are particularly suitable for Darlington circuit configurations to enhance gain when the transistor is used as an amplifier or sensor.

[0104] In some embodiments of this disclosure, a method of manufacturing a semiconductor device includes: forming a dielectric layer on a substrate; forming a superlattice structure on the dielectric layer; implanting a plurality of selected regions of the superlattice structure with a plurality of dopants to form an emitter region, a base region, and a collector region of a bipolar junction transistor (BJT); and forming a metallization structure on the emitter region, base region, and collector region of the BJT.

[0105] In some embodiments, the formation of the superlattice structure includes forming a plurality of thin layers of silicon and silicon-germanium that are stacked alternately.

[0106] In some embodiments, the method of manufacturing the semiconductor device further includes implanting multiple other selected regions of a superlattice structure with multiple other dopants, wherein the dose of the multiple other dopants is lower than that of multiple dopants in the emitter region, base region, and collector region of the bipolar junction transistor.

[0107] In some embodiments, the placement of multiple other selected regions includes placing n wells around the bipolar junction transistor.

[0108] In some embodiments, the planting of multiple selected regions includes planting multiple selected regions of a superlattice structure with multiple dopants according to a width ratio of about 5:1:5 to form an emitter region, a base region, and a collector region.

[0109] In some embodiments, the planting of multiple selected regions includes planting multiple selected regions of a superlattice structure with multiple dopants according to a width ratio of about 1:5:1 to form an emitter region, a base region, and a collector region.

[0110] In some embodiments, the deployment of multiple selected regions includes forming multiple undoped regions between multiple terminals of a bipolar junction transistor, wherein the width of the multiple undoped regions is approximately half that of multiple doped regions corresponding to the emitter and collector regions.

[0111] In some embodiments, the planting of multiple selected regions includes planting a superlattice structure with multiple n-type dopants and multiple p-type dopants to form multiple n-type regions that are wider than the multiple p-type regions.

[0112] In some embodiments, forming a metallized structure includes forming at least one rear metal layer and at least one front metal layer.

[0113] In some embodiments of this disclosure, a method of manufacturing a semiconductor device includes: forming a dielectric layer on a substrate; forming a superlattice structure on the dielectric layer; depositing a plurality of first selected regions of the superlattice structure with a first dopant dose to form a plurality of wells; depositing a plurality of second selected regions of the superlattice structure with a second dopant dose to form a plurality of emitter terminals, a plurality of base terminals, and a plurality of collector terminals of a pair of bipolar junction transistors (BJTs), wherein the second dopant dose is higher than the first dopant dose; and forming a metallization structure on the plurality of emitter terminals, the plurality of base terminals, and the plurality of collector terminals of the pair of bipolar junction transistors.

[0114] In some embodiments, the placement of multiple first selected regions includes placing one or more wells that separate adjacent bipolar junction transistors.

[0115] In some embodiments, the placement of multiple second selected regions includes placing multiple emitter terminals and multiple collector terminals with multiple p-doped materials to form a pair of bipolar junction transistors as two PNP transistors.

[0116] In some embodiments, the placement of multiple second selected regions includes placing multiple emitter terminals and multiple collector terminals with multiple n-doped materials to form a pair of bipolar junction transistors as two NPN transistors.

[0117] In some embodiments, forming the metallized structure includes configuring a pair of bipolar junction transistors electrically connected in a Darlington circuit configuration.

[0118] In some embodiments of this disclosure, a circuit structure includes: a first bipolar junction transistor (BJT) formed on a superlattice structure, the first bipolar junction transistor having a first base, a first emitter, and a first collector; and a second bipolar junction transistor formed on a superlattice structure, the second bipolar junction transistor having a second base, a second emitter, and a second collector, wherein the first emitter is electrically coupled to the second base, and the first collector and the second collector are electrically coupled to each other.

[0119] In some embodiments, the superlattice structure is an alternating stack of multiple silicon layers and multiple silicon-germanium layers.

[0120] In some embodiments, the first bipolar junction transistor and the second bipolar junction transistor are dual PNP type bipolar junction transistors.

[0121] In some embodiments, the first bipolar junction transistor and the second bipolar junction transistor are dual NPN bipolar junction transistors.

[0122] In some embodiments, the first base is electrically coupled to the first collector and the second collector.

[0123] In some embodiments, the multiple emitter regions, multiple base regions, and multiple collector regions of the first bipolar junction transistor and the second bipolar junction transistor are located within a superlattice structure.

[0124] The foregoing disclosure outlines the features of various embodiments, thereby enabling those skilled in the art to preferably understand the implementation of this disclosure. Those skilled in the art should understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or attain the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the concept and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from the concept and scope of this disclosure.

Claims

1. A circuit structure, characterized in that, include: A first bipolar junction transistor is formed on a superlattice structure, the first bipolar junction transistor having a first base, a first emitter and a first collector; as well as A second bipolar junction transistor is formed on the superlattice structure, the second bipolar junction transistor having a second base, a second emitter, and a second collector. The first emitter is electrically coupled to the second base, and the first collector and the second collector are electrically coupled to each other.

2. The circuit structure as described in claim 1, characterized in that, The superlattice structure is an alternating stack of multiple silicon layers and multiple silicon-germanium layers.

3. The circuit structure as described in claim 1, characterized in that, The first bipolar junction transistor and the second bipolar junction transistor are dual PNP type bipolar junction transistors.

4. The circuit structure as described in claim 3, characterized in that, The width ratio of the plurality of emitter regions, plurality of base regions, and plurality of collector regions of the first bipolar junction transistor and the second bipolar junction transistor is 1:5:

1.

5. The circuit structure as described in claim 1, characterized in that, The first bipolar junction transistor and the second bipolar junction transistor are dual NPN bipolar junction transistors.

6. The circuit structure as described in claim 5, characterized in that, The width ratio of the plurality of emitter regions, plurality of base regions, and plurality of collector regions of the first bipolar junction transistor and the second bipolar junction transistor is 5:1:

5.

7. The circuit structure as described in claim 1, characterized in that, The first base is electrically coupled to the first collector and the second collector.

8. The circuit structure as described in claim 1, characterized in that, The first bipolar junction transistor and the second bipolar junction transistor have multiple emitter regions, multiple base regions and multiple collector regions located within the superlattice structure.

9. The circuit structure as described in claim 1, characterized in that, It also includes a metallization structure, which includes at least one rear metal layer and at least one front metal layer.

10. The circuit structure as described in claim 1, characterized in that, It also includes a well placement that separates the first bipolar junction transistor from the second bipolar junction transistor.

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