High-power H-bridge drive circuit layout and multi-channel H-bridge drive circuit layout

Abstract

The utility model provides a high-power H-bridge driving circuit layout and a multi-channel H-bridge driving circuit layout, in the high-power H-bridge driving circuit layout, a first NBL isolation layer connected with a first power supply voltage is arranged between a high-side driving unit and a low-side driving unit; therefore, when the power of the first high-side driving tube, the second high-side driving tube, the first low-side driving tube and the second low-side driving tube is relatively high, the first NBL isolation layer can isolate the high-side driving unit from the low-side driving unit, so that the situation of electric leakage or latch-up effect generated between the high-side driving unit and the low-side driving unit is reduced.

Description

Technical Field

[0001] This utility model relates to the field of circuit layout, and in particular to a high-power H-bridge drive circuit layout and a multi-channel H-bridge drive circuit layout. Background Technology

[0002] An H-bridge drive circuit is a circuit structure used to control DC motors or certain stepper motors. It controls the direction of the motor current through two high-side switching elements and two low-side switching elements (usually MOSFETs or bipolar junction transistors, BJTs), thereby realizing functions such as forward and reverse rotation, speed regulation, and braking of the motor.

[0003] However, as the power of the switching elements increases, latch-up effects can easily occur between the high-side and low-side switching elements, as well as between two low-side switching elements. Utility Model Content

[0004] This invention provides a high-power H-bridge drive circuit layout and a multi-channel H-bridge drive circuit layout to reduce leakage or latch-up effects between the high-side drive unit and the low-side drive unit.

[0005] To solve the above technical problems, this utility model provides a high-power H-bridge drive circuit layout, including:

[0006] A high-side driving unit, the high-side driving unit includes a first high-side driving tube and a second high-side driving tube, the second high-side driving tube and the first high-side driving tube are arranged along a first direction, and there is a distance between the first high-side driving tube and the second high-side driving tube;

[0007] A low-side driving unit includes a first low-side driving transistor and a second low-side driving transistor. The second low-side driving transistor and the first low-side driving transistor are arranged along a first direction, and there is a distance between the first low-side driving transistor and the second low-side driving transistor. The first low-side driving transistor and the first high-side driving transistor are arranged along a second direction, and the second low-side driving transistor and the second high-side driving transistor are arranged along a second direction. The first direction is perpendicular to the second direction.

[0008] The first NBL isolation layer is connected to a first power supply voltage. The first NBL isolation layer is located between the high-side driving unit and the low-side driving unit, and there is a distance between the first NBL isolation layer and the high-side driving unit as well as between the first NBL isolation layer and the low-side driving unit.

[0009] Optionally, it further includes: a second NBL isolation layer, the second NBL isolation layer being located between the first low-side driving transistor and the second low-side driving transistor, the first end of the second NBL isolation layer being connected to the first NBL isolation layer or extending through the first NBL isolation layer to the space between the first high-side driving transistor and the second high-side driving transistor, and the second end of the second NBL isolation layer not exceeding the boundary of the low-side driving unit away from the first NBL isolation layer, and there being a distance between the second NBL isolation layer and both the first low-side driving transistor and the second low-side driving transistor.

[0010] Optionally, it also includes: the first high-side driving transistor, the second high-side driving transistor, the first low-side driving transistor and the second low-side driving transistor are all N-type laterally diffused metal-oxide semiconductor devices.

[0011] Optionally, the first low-side driving transistor is surrounded by a first NBL isolation ring, and the first NBL isolation ring is located on the periphery of the first low-side driving transistor, and the first NBL isolation ring is connected to the drain terminal of the first low-side driving transistor; the second low-side driving transistor is surrounded by a second NBL isolation ring, and the second NBL isolation ring is located on the periphery of the second low-side driving transistor, and the second NBL isolation ring is connected to the drain terminal of the second low-side driving transistor.

[0012] The first high-side driving transistor is surrounded by a third NBL isolation ring, and the third NBL isolation ring is located on the periphery of the first high-side driving transistor. The third NBL isolation ring is connected to the drain terminal of the first high-side driving transistor and is connected to a first power supply voltage. The second high-side driving transistor is surrounded by a fourth NBL isolation ring, and the fourth NBL isolation ring is located on the periphery of the second high-side driving transistor. The fourth NBL isolation ring is connected to the drain terminal of the second high-side driving transistor and is connected to a first power supply voltage.

[0013] Optionally, it further includes: a gate driving module, wherein the high-side driving unit and the gate driving module are disposed along a second direction, the gate driving module includes a high-side gate driving unit and a low-side gate driving unit, the high-side driving unit, the high-side gate driving unit and the low-side gate driving unit are disposed along the second direction, and there is a distance between the gate driving module and the high-side driving unit and between the high-side gate driving unit and the low-side gate driving unit.

[0014] Optionally, the high-side gate driving unit includes a first high-side gate driving circuit and a second high-side gate driving circuit, the second high-side gate driving circuit and the first high-side gate driving circuit are disposed along a first direction, there is a distance between the first high-side gate driving circuit and the second high-side gate driving circuit, the first high-side gate driving circuit is surrounded by a fifth NBL isolation ring, and the fifth NBL isolation ring is located on the periphery of the first high-side gate driving circuit, the fifth NBL isolation ring is connected to a second power supply voltage; the second high-side gate driving circuit is surrounded by a sixth NBL isolation ring, and the sixth NBL isolation ring is located on the periphery of the second high-side gate driving circuit, the sixth NBL isolation ring is connected to a third power supply voltage;

[0015] The low-side gate driving unit includes a first low-side gate driving circuit and a second low-side gate driving circuit. The second low-side gate driving circuit and the first low-side gate driving circuit are disposed along a first direction, and there is a distance between the first low-side gate driving circuit and the second low-side gate driving circuit. The first low-side gate driving circuit is surrounded by a seventh NBL isolation ring, and the seventh NBL isolation ring is located on the periphery of the first low-side gate driving circuit. The seventh NBL isolation ring is connected to a fourth power supply voltage. The second low-side gate driving circuit is surrounded by an eighth NBL isolation ring, and the eighth NBL isolation ring is located on the periphery of the second low-side gate driving circuit. The eighth NBL isolation ring is connected to a fourth power supply voltage.

[0016] Optionally, both the second power supply voltage and the third power supply voltage are lower than the first power supply voltage, and both the second power supply voltage and the third power supply voltage are higher than the fourth power supply voltage.

[0017] Optionally, the high-side driving unit, the low-side driving unit, and the gate driving module are all located within the same chip, and the low-side driving unit is located at the edge of the chip.

[0018] Optionally, the high-power H-bridge drive circuit layout is implemented based on a 0.18BCD process platform; the area of ​​the first high-side drive transistor, the second high-side drive transistor, the first low-side drive transistor, and the second low-side drive transistor is all greater than or equal to 0.3 square millimeters.

[0019] This utility model also provides a multi-channel H-bridge drive circuit layout, including:

[0020] N H-bridge drive circuits, each H-bridge drive circuit adopts the above-mentioned high-power H-bridge drive circuit layout, the first NBL isolation layer in any two adjacent H-bridge drive circuits is connected, the N H-bridge drive circuits are arranged sequentially along the first direction, and there is a distance between each H-bridge drive circuit, where N is a positive integer greater than 1.

[0021] (N-1) third NBL isolation layers, wherein the third NBL isolation layers are located between the two H-bridge drive circuits and between the second low-side drive transistor of one and the first low-side drive transistor of the other, the first end of the third NBL isolation layer is connected to the first NBL isolation layer or extends through the first NBL isolation layer to the first high-side drive transistor and the second high-side drive transistor located in the two adjacent H-bridge drive circuits respectively, and the second end of the third NBL isolation layer does not exceed the boundary of the two adjacent low-side drive units that is farthest from the first NBL isolation layer.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] In the high-power H-bridge driver circuit layout provided by this utility model, a first NBL isolation layer connected to a first power supply voltage is provided between the high-side driver unit and the low-side driver unit. When the power of the first high-side driver transistor, the second high-side driver transistor, the first low-side driver transistor, and the second low-side driver transistor is large, the first NBL isolation layer can isolate the high-side driver unit and the low-side driver unit, thereby reducing the occurrence of leakage or latch-up effects between the high-side driver unit and the low-side driver unit.

[0024] Furthermore, a second NBL isolation layer is provided between the first low-side driving transistor and the second low-side driving transistor, which can isolate the drain negative voltage of the first low-side driving transistor from the drain negative voltage of the second low-side driving transistor, thereby reducing the occurrence of leakage current or latch-up effect between the first low-side driving transistor and the second low-side driving transistor. One end of the second NBL isolation layer is connected to the first NBL isolation layer or extends through the first NBL isolation layer to the first high-side driving transistor and the second high-side driving transistor, so that the first low-side driving transistor and the second low-side driving transistor can be better isolated.

[0025] Furthermore, the high-side driving unit and the gate driving module are arranged along the second direction, and the gate driving module includes a first high-side gate driving circuit surrounded by a fifth NBL isolation ring, a second high-side gate driving circuit surrounded by a sixth NBL isolation ring, a first low-side gate driving circuit surrounded by a seventh NBL isolation ring, and a second low-side gate driving circuit surrounded by an eighth NBL isolation ring, so that no additional isolation layer is required between the high-side driving unit and the gate driving module, thereby saving chip area. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of an H-bridge driver circuit layout;

[0027] Figure 2 This is a schematic diagram of the layout of a high-power H-bridge drive circuit according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the circuit structure of a high-power H-bridge drive circuit according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the layout of a high-power H-bridge drive circuit according to another embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the layout of a multi-channel H-bridge drive circuit according to an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the layout of a multi-channel H-bridge drive circuit according to another embodiment of the present invention. Detailed Implementation

[0032] As described in the background art, as the power of the switching elements increases, latch-up effects are more likely to occur between the high-side switching elements and the low-side switching elements, as well as between two low-side switching elements.

[0033] Figure 1 This is a schematic diagram of an H-bridge driver circuit layout.

[0034] For ease of understanding, Figure 1 The diagram schematically illustrates a high-side drive unit, a low-side drive unit, a first NBL protection layer 1, and a second NBL protection layer 2. The high-side drive unit includes a first high-side drive transistor and a second high-side drive transistor, and the low-side drive unit includes a first low-side drive transistor and a second low-side drive transistor. The high-side drive unit and the low-side drive unit are located on opposite sides of the first NBL protection layer 1, and the NBL protection rings of the first NBL protection layer 1, the first low-side drive transistor, and the second low-side drive transistor are all connected to ground. The high-side drive unit and the internal circuit are located on opposite sides of the second NBL protection layer 2, and the second NBL protection layer 2 is connected to the power supply voltage PVDD.

[0035] Please refer to Figure 1 When the power of the driving circuit is high, the first NBL protection layer 1 connected to ground cannot effectively isolate the high-side driving unit and the low-side driving unit, resulting in a latch-up effect between the first low-side driving transistor and the second low-side driving transistor, as well as between the high-side driving unit and the low-side driving unit. Furthermore, the internal circuit includes a gate driving module for driving the first high-side driving transistor, the second high-side driving transistor, the first low-side driving transistor, and the second low-side driving transistor. A latch-up effect also occurs between the gate driving module and the first and second high-side driving transistors. Therefore, a second NBL protection layer 2 needs to be placed between the first high-side driving transistor, the second high-side driving transistor, and the internal circuit. However, the second NBL protection layer 2 occupies a large amount of chip area, reducing the chip area utilization rate.

[0036] In view of this, the present invention proposes a high-power H-bridge driver circuit layout, comprising: a high-side driving unit, the high-side driving unit including a first high-side driving transistor and a second high-side driving transistor, the second high-side driving transistor and the first high-side driving transistor being arranged along a first direction, and a distance existing between the first high-side driving transistor and the second high-side driving transistor; a low-side driving unit, the low-side driving unit including a first low-side driving transistor and a second low-side driving transistor, the second low-side driving transistor and the first low-side driving transistor being arranged along a first direction, the first low-side driving transistor and the first high-side driving transistor being arranged along a second direction, the first direction being perpendicular to the second direction; and a first NBL isolation layer, the first NBL isolation layer being connected to a first power supply voltage, the first NBL isolation layer being located between the high-side driving unit and the low-side driving unit, and a distance existing between the first NBL isolation layer and the high-side driving unit as well as between the first NBL isolation layer and the low-side driving unit.

[0037] By setting a first NBL isolation layer connected to the first power supply voltage between the high-side drive unit and the low-side drive unit, when the power of the first high-side drive transistor, the second high-side drive transistor, the first low-side drive transistor, and the second low-side drive transistor are high, the first NBL isolation layer can isolate the high-side drive unit and the low-side drive unit, thereby reducing the occurrence of leakage or latch-up effects between the high-side drive unit and the low-side drive unit.

[0038] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0039] Figure 2 This is a schematic diagram of the layout of a high-power H-bridge drive circuit according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the circuit structure of a high-power H-bridge drive circuit according to an embodiment of the present invention.

[0040] Please refer to Figure 2 The layout of the high-power H-bridge drive circuit includes: a high-side drive unit, a low-side drive unit, and a first NBL isolation layer 11.

[0041] The high-side drive unit includes a first high-side drive transistor MPH and a second high-side drive transistor MNH. The second high-side drive transistor MNH and the first high-side drive transistor MPH are arranged along a first direction, and there is a distance between the first high-side drive transistor MPH and the second high-side drive transistor MNH.

[0042] The low-side drive unit includes a first low-side drive transistor MPL and a second low-side drive transistor MNL. The second low-side drive transistor MNL and the first low-side drive transistor MPL are arranged along a first direction, and there is a distance between the first low-side drive transistor MPL and the second low-side drive transistor MNL. The first low-side drive transistor MPL and the first high-side drive transistor MPH are arranged along a second direction, and the second low-side drive transistor MNL and the second high-side drive transistor MNH are arranged along a second direction. The first direction and the second direction are perpendicular.

[0043] The first NBL isolation layer 11 is connected to the first power supply voltage PVDD. The first NBL isolation layer 11 is located between the high-side driving unit and the low-side driving unit, and there is a distance between the first NBL isolation layer 11 and the high-side driving unit as well as between the first NBL isolation layer 11 and the low-side driving unit.

[0044] In this embodiment, please refer to Figure 3 The first high-side drive transistor MPH, the second high-side drive transistor MNH, the first low-side drive transistor MPL, and the second low-side drive transistor MNL are all N-type laterally diffused metal-oxide semiconductor devices.

[0045] In this embodiment, the high-power H-bridge drive circuit layout is implemented based on the 0.18BCD process platform, and the first high-side drive transistor MPH, the second high-side drive transistor MNH, the first low-side drive transistor MPL, and the second low-side drive transistor MNL are all high-power devices, for example, they may include devices with an area greater than or equal to 0.3 square millimeters.

[0046] Please refer to the following: Figure 3 The drain terminals of the first high-side driver transistor MPH and the second high-side driver transistor MNH are connected together and connected to the first power supply voltage PVDD. The source terminal of the first high-side driver transistor MPH is connected to the drain terminal of the first low-side driver transistor MPL and connected to one end of the load to serve as the first output terminal OUTP. The source terminal of the second high-side driver transistor MNH is connected to the drain terminal of the second low-side driver transistor MNL and connected to the other end of the load to serve as the second output terminal OUTN. The source terminals of the first low-side driver transistor MPL and the second low-side driver transistor MNL are connected together and connected to ground. The first power supply voltage PVDD is the highest voltage in the chip. In this H-bridge driver circuit, the four driver transistors operate alternately to drive the load; that is, the first high-side driver transistor MPH and the second low-side driver transistor MNL are simultaneously turned on as one group, and the second high-side driver transistor MNH and the first low-side driver transistor MPL are simultaneously turned on as another group, and the two groups of driver transistors are turned on alternately.

[0047] In one embodiment, please continue to refer to Figure 2The high-power H-bridge driver circuit layout also includes a second NBL isolation layer 22. The second NBL isolation layer 22 is located between the first low-side driver transistor MPL and the second low-side driver transistor MNL. The first end of the second NBL isolation layer 22 is connected to the first NBL isolation layer 11, and the second end of the second NBL isolation layer 22 does not exceed the boundary of the low-side driver unit away from the first NBL isolation layer 11. There is a distance between the second NBL isolation layer 22 and both the first low-side driver transistor MPL and the second low-side driver transistor MNL. Since the first end of the second NBL isolation layer 22 is connected to the first NBL isolation layer 11, the second NBL isolation layer 22 is also connected to the first power supply voltage PVDD. The placement of the second NBL isolation layer 22 between the first low-side driver transistor MPL and the second low-side driver transistor MNL isolates the negative voltage generated at the drain terminal of the first low-side driver transistor MPL from the negative voltage generated at the drain terminal of the second low-side driver transistor MNL, thereby reducing leakage or latch-up effects between the first low-side driver transistor MPL and the second low-side driver transistor MNL. Furthermore, since more charge tends to accumulate at the four corners of the four driving transistors near the center of the H-bridge driving circuit, making them more prone to leakage than other locations, connecting one end of the second NBL isolation layer 22 to the first NBL isolation layer 1111 enables better isolation between the first low-side driving transistor MPL and the second high-side driving transistor MNH, as well as between the second low-side driving transistor MNL and the first high-side driving transistor MPH. Here, the center of the H-bridge driving circuit can be understood as the geometric center between the first high-side driving transistor, the second high-side driving transistor, the first bottom-side driving transistor, and the second low-side driving transistor.

[0048] In another embodiment, please refer to Figure 4 , Figure 4This is a schematic diagram of a high-power H-bridge driver circuit layout according to another embodiment of the present invention. In this high-power H-bridge driver circuit layout, the second NBL isolation layer 22 is replaced by a second NBL isolation layer 23. In this embodiment, the second NBL isolation layer 23 is located between the first low-side driver transistor MPL and the second low-side driver transistor MNL. The first end of the second NBL isolation layer 23 extends through the first NBL isolation layer 11 to the space between the first high-side driver transistor MPH and the second high-side driver transistor MNH. The second end of the second NBL isolation layer 23 does not exceed the boundary of the low-side driver unit away from the first NBL isolation layer 11. There is a distance between the second NBL isolation layer 23 and both the first low-side driver transistor MPL and the second low-side driver transistor MNL. The first end of the second NBL isolation layer 23 extends through the first NBL isolation layer 11 between the first high-side driving transistor MPH and the second high-side driving transistor MNH. One end of the second NBL isolation layer 23 between the first low-side driving transistor MPL and the second low-side driving transistor MNL, and one end of the second NBL isolation layer 23 between the first high-side driving transistor MPH and the second high-side driving transistor MNH, are both connected to the first NBL isolation layer 11. Therefore, the second NBL isolation layer 23 is also connected to the first power supply voltage PVDD, which enables the second NBL isolation layer 23 to further capture the negative charges at the two corners of the first high-side driving transistor MPH and the second high-side driving transistor MNH near the center of the H-bridge driving circuit, thereby further improving the isolation between the first low-side driving transistor MPL and the second high-side driving transistor MNH, and between the second low-side driving transistor MNL and the first high-side driving transistor MPH.

[0049] Please continue to refer to this. Figure 2In this embodiment, the first low-side driving transistor MPL is surrounded by a first NBL isolation ring 100, and the first NBL isolation ring 100 is located on the periphery of the first low-side driving transistor MPL. The first NBL isolation ring 100 is connected to the drain terminal of the first low-side driving transistor MPL. The second low-side driving transistor MNL is surrounded by a second NBL isolation ring 200, and the second NBL isolation ring 200 is located on the periphery of the second low-side driving transistor MNL. The second NBL isolation ring 200 is connected to the drain terminal of the second low-side driving transistor MNL. The first NBL isolation ring 100 and the second NBL isolation ring 200 are built-in NBL protection rings of the first low-side driving transistor MPL and the second low-side driving transistor MNL, respectively, due to device limitations. In addition, there are distances between the first NBL isolation ring 100 and the second NBL isolation layer 22, and between the fourth NBL isolation ring 400 and the second NBL isolation layer 22, and there are also distances between the first NBL isolation ring 100 and the first NBL isolation layer 11, and between the second NBL isolation ring 200 and the first NBL isolation layer 11.

[0050] In this embodiment, the first high-side driver transistor MPH is surrounded by a third NBL isolation ring 300, which is located on the periphery of the first high-side driver transistor MPH. The third NBL isolation ring 300 is connected to the drain terminal of the first high-side driver transistor MPH and is connected to the first power supply voltage PVDD. The second high-side driver transistor MNH is surrounded by a fourth NBL isolation ring 400, which is located on the periphery of the second high-side driver transistor MNH. The fourth NBL isolation ring 400 is connected to the drain terminal of the second high-side driver transistor MNH and is connected to the first power supply voltage PVDD. The third NBL isolation ring 300 and the fourth NBL isolation ring 400 are built-in NBL protection rings for the first high-side driver transistor MPH and the second high-side driver transistor MNH, respectively, due to device limitations. In addition, there is a distance between the third NBL isolation ring 300 and the fourth NBL isolation ring 400, and there are also distances between the first NBL isolation layers 11 of the third isolation ring and between the fourth NBL isolation ring 400 and the first NBL isolation layer 11.

[0051] In this embodiment, the high-power H-bridge drive circuit layout further includes a gate drive module. The high-side drive unit and the gate drive module are arranged along the second direction. The gate drive module includes a high-side gate drive unit and a low-side gate drive unit. The high-side drive unit, the high-side gate drive unit and the low-side gate drive unit are arranged along the second direction, and there is a distance between the gate drive module and the high-side drive unit and between the high-side gate drive unit and the low-side gate drive unit.

[0052] In this embodiment, the high-side driving unit, the low-side driving unit, and the gate driving module are all located within the same chip, with the low-side driving unit situated at the chip's edge. Specifically, since the low-side driving unit generates a negative voltage during operation, it is prone to leakage current to surrounding N-type devices, potentially leading to malfunctions. Therefore, placing the low-side driving unit at the chip's edge aids in heat dissipation and prevents malfunctions, thereby improving circuit stability and reliability. The gate driving module is located between the high-side driving unit and the low-voltage circuitry on the chip, and is positioned as close as possible to the high-side driving unit. Therefore, the gate driving module serves to isolate the high-side driving unit from the low-voltage circuitry within the chip, which may include bias circuitry, control circuitry, and protection circuitry.

[0053] In this embodiment, the high-side gate driving unit includes a first high-side gate driving circuit HS_GP and a second high-side gate driving circuit HS_GN. The second high-side gate driving circuit HS_GN and the first high-side gate driving circuit HS_GP are arranged along a first direction, and there is a distance between the first high-side gate driving circuit HS_GP and the second high-side gate driving circuit HS_GN. The first high-side gate driving circuit HS_GP is surrounded by a fifth NBL isolation ring 500, and the fifth NBL isolation ring 500 is located on the periphery of the first high-side gate driving circuit HS_GP. The fifth NBL isolation ring 500 is connected to a second power supply voltage BSTP. The second high-side gate driving circuit HS_GN is surrounded by a sixth NBL isolation ring 600, and the sixth NBL isolation ring 600 is located on the periphery of the second high-side gate driving circuit HS_GN. The sixth NBL isolation ring 600 is connected to a third power supply voltage BSTN.

[0054] In this embodiment, the low-side gate driving unit includes a first low-side gate driving circuit LS_GP and a second low-side gate driving circuit LS_GN. The second low-side gate driving circuit LS_GN and the first low-side gate driving circuit LS_GP are arranged along a first direction, and there is a distance between the first low-side gate driving circuit LS_GP and the second low-side gate driving circuit LS_GN. The first low-side gate driving circuit LS_GP is surrounded by a seventh NBL isolation ring 700, and the seventh NBL isolation ring 700 is located on the periphery of the first low-side gate driving circuit LS_GP. The seventh NBL isolation ring 700 is connected to a fourth power supply voltage GVDD. The second low-side gate driving circuit LS_GN is surrounded by an eighth NBL isolation ring 800, and the eighth NBL isolation ring 800 is located on the periphery of the second low-side gate driving circuit LS_GN. The eighth NBL isolation ring 800 is connected to the fourth power supply voltage GVDD.

[0055] The first high-side gate drive circuit HS_GP is connected to the gate of the first high-side drive transistor MPH and is used to drive the first high-side drive transistor MPH. The second high-side gate drive circuit HS_GN is connected to the gate of the second high-side drive transistor MNH and is used to drive the second high-side drive transistor MNH. The first low-side gate drive circuit LS_GP is connected to the gate of the first low-side drive transistor MPL and is used to drive the first low-side drive transistor MPL. The second low-side gate drive circuit LS_GN is connected to the gate of the second low-side drive transistor MNL and is used to drive the second low-side drive transistor MNL.

[0056] In this embodiment, both the second power supply voltage BSTP and the third power supply voltage BSTN are less than the first power supply voltage PVDD, and both the second power supply voltage BSTP and the third power supply voltage BSTN are greater than the fourth power supply voltage GVDD.

[0057] In summary, by setting a first NBL isolation layer 11 connected to the first power supply voltage PVDD between the high-side drive unit and the low-side drive unit, when the power of the first high-side drive transistor MPH, the second high-side drive transistor MNH, the first low-side drive transistor MPL, and the second low-side drive transistor MNL are large, the first NBL isolation layer 11 can isolate the high-side drive unit and the low-side drive unit, thereby reducing the occurrence of leakage or latch-up effects between the high-side drive unit and the low-side drive unit.

[0058] Furthermore, a second NBL isolation layer 22 is provided between the first low-side drive transistor MPL and the second low-side drive transistor MNL, which can isolate the drain negative voltage of the first low-side drive transistor MPL from the drain negative voltage of the second low-side drive transistor MNL, thereby reducing the occurrence of leakage current or latch-up effect between the first low-side drive transistor MPL and the second low-side drive transistor MNL. One end of the second NBL isolation layer 22 is connected to the first NBL isolation layer 11 or extends through the first NBL isolation layer 11 between the first high-side drive transistor MPH and the second high-side drive transistor MNH, so that the first low-side drive transistor MPL and the second low-side drive transistor MNL can be better isolated.

[0059] Furthermore, the high-side driving unit and the gate driving module are arranged along the second direction, and the gate driving module includes a first high-side gate driving circuit HS_GP surrounded by a fifth NBL isolation ring 500, a second high-side gate driving circuit HS_GN surrounded by a sixth NBL isolation ring 600, a first low-side gate driving circuit LS_GP surrounded by a seventh NBL isolation ring 700, and a second low-side gate driving circuit LS_GN surrounded by an eighth NBL isolation ring 800. This eliminates the need for an additional isolation layer between the high-side driving unit and the gate driving module, thereby saving chip area.

[0060] Figure 5 This is a schematic diagram of the layout of a multi-channel H-bridge drive circuit according to an embodiment of the present invention.

[0061] Please refer to Figure 5 This utility model embodiment also provides a multi-channel H-bridge driving circuit layout, including N H-bridge driving circuits CHANNEL{…} and (N-1) third NBL isolation layers 33.

[0062] Each H-bridge driver circuit CHANNEL{…} adopts the high-power H-bridge driver circuit layout as described in the above embodiment. The first NBL isolation layer 11 in any two adjacent H-bridge driver circuit CHANNEL{…} is connected. N H-bridge driver circuits CHANNEL{…} are arranged sequentially along the first direction. There is a distance between each H-bridge driver circuit CHANNEL{…}, where N is a positive integer greater than 1.

[0063] (N-1) third NBL isolation layers 33, each third NBL isolation layer 33 is located between two H-bridge drive circuits CHANNEL{…}, and specifically between the second low-side drive transistor MNL of one and the first low-side drive transistor MPL of the other. Specifically, the third NBL isolation layer 33 is used to isolate two adjacent H-bridge drive circuits CHANNEL{…}, thereby reducing their mutual influence and making each H-bridge drive circuit CHANNEL{…} relatively independent.

[0064] In one embodiment, the first end of the third NBL isolation layer 33 is connected to the first NBL isolation layer 11, and the second end of the third NBL isolation layer 33 does not exceed the boundary of the two adjacent low-side driving units that is farthest from the first NBL isolation layer 11. Since the first end of the third NBL isolation layer 33 is connected to the first NBL isolation layer 11, the third NBL isolation layer 33 is also connected to the first power supply voltage PVDD.

[0065] In another embodiment, please refer to Figure 6 , Figure 6 This is a schematic diagram of the layout of a multi-channel H-bridge driver circuit according to another embodiment of the present invention. In this embodiment, the third NBL isolation layer 33 is replaced by a third NBL isolation layer 34. Specifically, the first end of the third NBL isolation layer 34 extends through the first NBL isolation layer 11 between the first high-side driver transistor MPH and the second high-side driver transistor MNH located in two adjacent H-bridge driver circuits CHANNEL{…}, and the second end of the third NBL isolation layer 34 does not exceed the boundary of the two adjacent low-side driver units that is farthest from the first NBL isolation layer 11. Therefore, the third NBL isolation layer 34 is also connected to the first power supply voltage PVDD. In addition, a fourth NBL isolation layer is provided on one side of the first NBL isolation layer 11 near the high-side driver unit of the first H-bridge driver circuit and the high-side driver unit of the Nth H-bridge driver circuit. One end of the fourth NBL isolation layer 44 is connected to the first NBL isolation layer 11, and therefore, the fourth NBL isolation layer 44 is connected to the first power supply voltage PVDD.

[0066] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A high-power H-bridge drive circuit layout, characterized in that, include: A high-side driving unit, the high-side driving unit includes a first high-side driving tube and a second high-side driving tube, the second high-side driving tube and the first high-side driving tube are arranged along a first direction, and there is a distance between the first high-side driving tube and the second high-side driving tube; A low-side driving unit includes a first low-side driving transistor and a second low-side driving transistor. The second low-side driving transistor and the first low-side driving transistor are arranged along a first direction, and there is a distance between the first low-side driving transistor and the second low-side driving transistor. The first low-side driving transistor and the first high-side driving transistor are arranged along a second direction, and the second low-side driving transistor and the second high-side driving transistor are arranged along a second direction. The first direction is perpendicular to the second direction. The first NBL isolation layer is connected to a first power supply voltage. The first NBL isolation layer is located between the high-side driving unit and the low-side driving unit, and there is a distance between the first NBL isolation layer and the high-side driving unit as well as between the first NBL isolation layer and the low-side driving unit.

2. The high-power H-bridge drive circuit layout according to claim 1, characterized in that, Also includes: The second NBL isolation layer is located between the first low-side drive transistor and the second low-side drive transistor. The first end of the second NBL isolation layer is connected to the first NBL isolation layer or extends through the first NBL isolation layer to the space between the first high-side drive transistor and the second high-side drive transistor. The second end of the second NBL isolation layer does not exceed the boundary of the low-side drive unit away from the first NBL isolation layer. There is a distance between the second NBL isolation layer and both the first and second low-side drive transistors.

3. The high-power H-bridge drive circuit layout according to claim 1, characterized in that, The first high-side driving transistor, the second high-side driving transistor, the first low-side driving transistor, and the second low-side driving transistor are all N-type laterally diffused metal-oxide semiconductor devices.

4. The high-power H-bridge drive circuit layout according to claim 1, characterized in that, The first low-side drive transistor is surrounded by a first NBL isolation ring, and the first NBL isolation ring is located on the periphery of the first low-side drive transistor. The first NBL isolation ring is connected to the drain terminal of the first low-side drive transistor. The second low-side drive transistor is surrounded by a second NBL isolation ring, and the second NBL isolation ring is located on the periphery of the second low-side drive transistor. The second NBL isolation ring is connected to the drain terminal of the second low-side drive transistor. The first high-side driving transistor is surrounded by a third NBL isolation ring, and the third NBL isolation ring is located on the periphery of the first high-side driving transistor. The third NBL isolation ring is connected to the drain terminal of the first high-side driving transistor and is connected to a first power supply voltage. The second high-side driving transistor is surrounded by a fourth NBL isolation ring, and the fourth NBL isolation ring is located on the periphery of the second high-side driving transistor. The fourth NBL isolation ring is connected to the drain terminal of the second high-side driving transistor and is connected to a first power supply voltage.

5. The high-power H-bridge drive circuit layout according to claim 1, characterized in that, It also includes: a gate driving module, wherein the high-side driving unit and the gate driving module are disposed along a second direction, the gate driving module includes a high-side gate driving unit and a low-side gate driving unit, the high-side driving unit, the high-side gate driving unit and the low-side gate driving unit are disposed along the second direction, and there is a distance between the gate driving module and the high-side driving unit and between the high-side gate driving unit and the low-side gate driving unit.

6. The high-power H-bridge drive circuit layout according to claim 5, characterized in that, The high-side gate driving unit includes a first high-side gate driving circuit and a second high-side gate driving circuit. The second high-side gate driving circuit and the first high-side gate driving circuit are arranged along a first direction, and there is a distance between the first high-side gate driving circuit and the second high-side gate driving circuit. The first high-side gate driving circuit is surrounded by a fifth NBL isolation ring, and the fifth NBL isolation ring is located on the periphery of the first high-side gate driving circuit. The fifth NBL isolation ring is connected to a second power supply voltage. The second high-side gate driving circuit is surrounded by a sixth NBL isolation ring, and the sixth NBL isolation ring is located on the periphery of the second high-side gate driving circuit. The sixth NBL isolation ring is connected to a third power supply voltage. The low-side gate driving unit includes a first low-side gate driving circuit and a second low-side gate driving circuit. The second low-side gate driving circuit and the first low-side gate driving circuit are disposed along a first direction, and there is a distance between the first low-side gate driving circuit and the second low-side gate driving circuit. The first low-side gate driving circuit is surrounded by a seventh NBL isolation ring, and the seventh NBL isolation ring is located on the periphery of the first low-side gate driving circuit. The seventh NBL isolation ring is connected to a fourth power supply voltage. The second low-side gate driving circuit is surrounded by an eighth NBL isolation ring, and the eighth NBL isolation ring is located on the periphery of the second low-side gate driving circuit. The eighth NBL isolation ring is connected to a fourth power supply voltage.

7. The high-power H-bridge drive circuit layout according to claim 6, characterized in that, The second power supply voltage and the third power supply voltage are both less than the first power supply voltage, and the second power supply voltage and the third power supply voltage are both greater than the fourth power supply voltage.

8. The high-power H-bridge drive circuit layout according to claim 5, characterized in that, The high-side driving unit, the low-side driving unit, and the gate driving module are all located within the same chip, and the low-side driving unit is located at the edge of the chip.

9. The high-power H-bridge drive circuit layout according to any one of claims 1 to 8, characterized in that, The high-power H-bridge drive circuit layout is implemented based on the 0.18BCD process platform; the area of ​​the first high-side drive transistor, the second high-side drive transistor, the first low-side drive transistor, and the second low-side drive transistor is greater than or equal to 0.3 square millimeters.

10. A layout for a multi-channel H-bridge driver circuit, characterized in that, include: N H-bridge drive circuits, each H-bridge drive circuit adopts the high-power H-bridge drive circuit layout as described in any one of claims 1 to 9, the first NBL isolation layer in any two adjacent H-bridge drive circuits is connected, the N H-bridge drive circuits are arranged sequentially along the first direction, and there is a distance between each H-bridge drive circuit, where N is a positive integer greater than 1. (N-1) third NBL isolation layers, wherein the third NBL isolation layers are located between the two H-bridge drive circuits and between the second low-side drive transistor of one and the first low-side drive transistor of the other, the first end of the third NBL isolation layer is connected to the first NBL isolation layer or extends through the first NBL isolation layer to the first high-side drive transistor and the second high-side drive transistor located in the two adjacent H-bridge drive circuits respectively, and the second end of the third NBL isolation layer does not exceed the boundary of the two adjacent low-side drive units that is farthest from the first NBL isolation layer.

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