Large-capacitance capacitive chip structure
By setting grooves on the first electrode plate of the MEMS capacitive sensor and forming a multi-layer electrode structure, the problem of small capacitance value is solved, enabling the manufacturing of large capacitance capacitors, reducing cost and area, and improving the accuracy and integration of the sensor.
Patent Information
- Application Number
- CN202520721864.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-04-16
AI Technical Summary
Existing MEMS capacitive sensors have relatively small capacitance values, which cannot meet the requirements for large capacitance values. Furthermore, producing large capacitance values involves high costs, large areas, and large thicknesses.
A groove is provided on the first electrode plate, and an insulating dielectric layer is provided on the sidewall and top of the groove to form a multi-layer electrode plate structure, including a second electrode plate and a pressure-sensitive electrode plate, forming a differential capacitor. The capacitance value is increased by increasing the electrode plate area.
This significantly increases the capacitance value, saves chip area, reduces chip height, improves integration, reduces manufacturing difficulty, and enhances the linearity and sensitivity of the capacitor output characteristics.
Smart Images
Figure CN223906541U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the micro electromechanical system (MEMS) technical field, especially relate to a big capacitance capacitance chip structure. BACKGROUND
[0002] With the development of MEMS technology, the capacitive sensor becomes the indispensable key device in various industries, and has been widely used in automotive electronics, petrochemical industry, biomedicine and national defense industry and other fields. Compared with other types of sensors, the capacitive sensor has the advantages of high sensitivity, low power consumption, good temperature characteristics, and is more suitable for developing high-precision sensors. Especially in the background of increasing requirements for acceleration, pressure measurement accuracy and reliability in modern aerospace technology and modern national defense equipment, the research of MEMS capacitive sensor is highly valued at home and abroad, and in the short-term energy storage, the demand for large-capacity capacitors is also increasing.
[0003] For ordinary MEMS capacitive sensor, generally adopts parallel plate capacitor structure, mainly composed of upper plate and lower plate, the middle is insulating dielectric layer, when there is pressure on the movable plate, the distance between the two plates changes, and the capacitance value changes. The capacitance value of such capacitor structure is generally small, which cannot meet the demand for large-capacity capacitor; if the production of large-capacity MEMS capacitor is high in cost, large in area and high in thickness. UTILITY MODEL CONTENTS
[0004] The utility model is just aimed at the above problem, provide a chip size small big capacitance capacitance chip structure.
[0005] In order to achieve the above object, the utility model adopts the following technical scheme, the utility model discloses a first plate (01), characterized in that the first plate (01) upper end face is provided with recess (61), the first plate (01) upper end face (including the bottom surface and side wall of recess (61)) is provided with first insulating dielectric layer (41), and the first insulating dielectric layer (41) upper end face is provided with second plate (02). As Figure 1 .
[0006] As a preferred scheme, the second insulating dielectric layer (42) is arranged on the second plate (02) outside the recess (61), the second insulating dielectric layer (42) covers the upper end of the recess (61), and the pressure sensing plate (31) is arranged on the second insulating dielectric layer (42); the cavity (71) is formed in the recess (61) below the second insulating dielectric layer (42), the pressure sensing plate (31) and the second plate (02) form a variable capacitor C1 that changes with pressure, the first plate (01) and the second plate (02) form an invariable capacitor C2, and C1, C2 constitute a differential capacitor. As Figure 2 .
[0007] As another preferred scheme, the recess (61) is circular or polygonal (such as triangular, quadrangular, pentagonal, hexagonal, etc.).
[0008] As another preferred scheme, the recess (61) is multiple. For example, Figure 3 .
[0009] As another preferred scheme, the recess (61) is provided with a first cylinder (55), the first cylinder (55) is integrated with the first polar plate (01), and the outer wall of the first cylinder (55) is sequentially provided with a first insulating medium layer (41) and a second polar plate (02) from inside to outside. For example, Figure 4 , 5 .
[0010] As another preferred scheme, the recess (61) is annular, including but not limited to a circular ring, a square ring, and a polygonal ring. For example, Figure 6 .
[0011] As another preferred scheme, the first polar plate (01) on the outer side of the recess (61) is provided with an annular recess (61). For example, Figure 6 . The recess (61) and the annular recess (61) are spaced apart, and the outer contour line of the recess (61) is the spacing, for example, Figure 6 .
[0012] As another preferred scheme, the annular recess (61) is provided with a first cylinder (55), for example, Figure 18 .
[0013] As another preferred solution, the annular groove (61) is provided with a first column (55), and the first column (55) in the annular groove (61) is integrated with the first polar plate (01). The front and rear sidewalls of the first column (55) in the annular groove (61) are connected with the sidewall of the annular groove (61) as a part of the first polar plate (01) (that is, the front and rear sidewalls of the first column (55) in the annular groove (61) do not cover the first insulating medium layer (41) and the second polar plate (02), and the sidewall of the annular groove (61) connected with the front and rear sidewalls of the first column (55) in the annular groove (61) does not cover the first insulating medium layer (41) and the second polar plate (02)), except that the bottom surface and the sidewall of the annular groove (61) of the sidewall of the annular groove (61) connected with the front and rear sidewalls of the first column (55) in the annular groove (61) are sequentially provided with the first insulating medium layer (41) and the second polar plate (02) from inside to outside, and the left and right sidewalls of the first column (55) in the annular groove (61) are sequentially provided with the first insulating medium layer (41) and the second polar plate (02) from inside to outside. When the front and rear sidewalls of the first column (55) in the annular groove (61) are connected with the sidewall of the annular groove (61), the annular groove (61) is equivalent to being divided into a plurality of grooves by the first column (55). For example Figure 7 .
[0014] The left and right sidewalls of the first column (55) in the annular groove (61) that are not connected with the sidewall of the annular groove (61) increase the area of the polar plate. Compared with the structure without the first column (55), the area of the polar plate is increased more, the capacitance value is proportional to the area of the polar plate, the capacitance value is increased, the structure is more firm, the process difficulty is reduced, and the manufacturing is easier to implement.
[0015] As another preferred solution, the upper opening of the sidewall (51) of the groove (61) is provided as a first circular arc (56), as shown in Figure 8 ; or the connecting part of the bottom of the groove (61) and the sidewall (51) is provided as a second circular arc (57), as shown in Figure 8 ; the first circular arc (56) can be an outward convex or inward concave circular arc, and the second circular arc (57) can be an outward convex or inward concave circular arc.
[0016] As another preferred solution, the upper opening of the sidewall (51) of the groove (61) is provided as a first slope (59), as shown in Figure 9 ; or the connecting part of the bottom of the groove (61) and the sidewall (51) is provided as a second slope (58), as shown in Figure 9 .
[0017] As another preferred solution, the groove (61) is provided in a shape of being wide at the top and narrow at the bottom, as shown in Figure 10 .
[0018] As another preferred solution, a second insulating medium layer (42) is arranged on the second electrode plate (02), a third electrode plate (03) is arranged on the second insulating medium layer (42), the first electrode plate (01) and the second electrode plate (02) form a capacitor C1, and the second electrode plate (02) and the third electrode plate (03) form a capacitor C2. Figure 11 .
[0019] As another preferred solution, a second insulating medium layer (42) is arranged on the second electrode plate (02), a third electrode plate (03) is arranged on the second insulating medium layer (42); a third insulating medium layer (43) is arranged on the third electrode plate (03), and a fourth electrode plate (04) is arranged on the third insulating medium layer (43); the first electrode plate (01) and the second electrode plate (02) form a capacitor C1, the second electrode plate (02) and the third electrode plate (03) form a capacitor C2, and the third electrode plate (03) and the fourth electrode plate (04) form a capacitor C3. Figure 12 .
[0020] As another preferred solution, the recess (61) is hexagonal, and adjacent recesses (61) share a side wall (51), as shown in Figure 13 .
[0021] As another preferred solution, the second column (52) fills the recess (61), and the second column (52) and the second electrode plate (02) are integrated, as shown in Figure 14 .
[0022] As another preferred solution, the second column (52) with a T-shaped cross section fills the recess (61), the lower end of the outer side of the upper portion of the second column (52) is connected to the upper end of the second electrode plate (02), and the second column (52) is an insulating medium layer or a semiconductor material layer. The insulating medium layer plays a protective role, and when the material of the second column (52) is a semiconductor material, it lays a foundation for the subsequent production of electronic devices, as shown in Figure 15 .
[0023] As another preferred solution, a second insulating medium layer (42) is arranged on the second electrode plate (02), a third electrode plate (03) is arranged on the second insulating medium layer (42); a third insulating medium layer (43) is arranged on the third electrode plate (03), and a fourth electrode plate (04) is arranged on the third insulating medium layer (43); the second column (52) fills all the empty parts of the recess (61), and the second column (52) and the fourth electrode plate (04) are integrated, as shown in Figure 16 .
[0024] As another preferred solution, the recess (61) is polygonal, and the included angle of adjacent sides is provided as an arc (53), as shown in the figure. Figure 17
[0025] Secondly, the side wall (51) of the recess (61) is provided with a wall groove (62). The side wall of the wall groove (62) increases the area of the plate, and the capacitance value is proportional to the area of the plate, which further increases the capacitance value, as shown in the figure. Figure 19
[0026] In addition, the wall groove (62) is provided with a plurality of wall grooves.
[0027] The utility model has the advantages that
[0028] Since the capacitance value is proportional to the area of the plate, the utility model adopts the mode of setting the recess (61) on the first plate (01) to complete the structure of the capacitor chip; the area of the first plate (01) and the second plate (02) is greatly increased, and the capacitance value can be greatly increased. Under the condition of the same area, when the depth-width ratio of the recess is 30:1, the capacitance value can be effectively increased by more than 50 times. When a plurality of recesses are set, the capacitance value can be increased by hundreds, thousands or ten thousands of times, the chip area is saved, the integration degree is improved, the chip area is saved, and the chip height is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0029] The utility model will be further described in combination with the drawings and specific embodiments. The protection scope of the utility model is not limited to the following content.
[0030] Figure 1 It is the first embodiment section structure schematic diagram of the utility model.
[0031] Figure 2 It is the second embodiment section structure schematic diagram of the utility model.
[0032] Figure 3 It is the third embodiment section structure schematic diagram of the utility model.
[0033] Figure 4 It is the fourth embodiment section structure schematic diagram of the utility model.
[0034] Figure 5 It is the fourth embodiment overhead structure schematic diagram of the utility model.
[0035] Figure 6 It is the fifth embodiment overhead structure schematic diagram of the utility model.
[0036] Figure 7 is a top view structure schematic diagram of the seventh embodiment of the utility model.
[0037] Figure 8 is a cross section structure schematic diagram of the eighth embodiment of the utility model.
[0038] Figure 9 is a cross section structure schematic diagram of the ninth embodiment of the utility model.
[0039] Figure 10 is a cross section structure schematic diagram of the tenth embodiment of the utility model.
[0040] Figure 11 is a cross section structure schematic diagram of the eleventh embodiment of the utility model.
[0041] Figure 12 is a cross section structure schematic diagram of the twelfth embodiment of the utility model.
[0042] Figure 13 is a cross section structure schematic diagram of the thirteenth embodiment of the utility model.
[0043] Figure 14 is a cross section structure schematic diagram of the fourteenth embodiment of the utility model.
[0044] Figure 15 is a cross section structure schematic diagram of the fifteenth embodiment of the utility model.
[0045] Figure 16 is a cross section structure schematic diagram of the sixteenth embodiment of the utility model.
[0046] Figure 17 is a cross section structure schematic diagram of the seventeenth embodiment of the utility model.
[0047] Figure 18 is a top view structure schematic diagram of the sixth embodiment of the utility model.
[0048] Figure 19 is a cross section structure schematic diagram of the eighteenth embodiment of the utility model
[0049] Figure 20 is an output characteristic curve diagram of the second embodiment of the utility model.
[0050] Mark explanation:
[0051] 01. first polar plate, 02. second polar plate, 03. third polar plate, 04. fourth polar plate, 41. first insulating layer, 42. second insulating layer, 43. third insulating layer, 51. side wall, 52. column, 53. circular arc, 55. column, 56. circular arc, 57. circular arc, 58. slope, 59. slope, 61. recess, 62. wall groove, 71. cavity. Specific implementation
[0052] like Figure 1 As shown, a groove (61) is provided on the first electrode plate (01), and the side wall of the groove (61) is a side wall (51). The side wall (51) is made of the same material as the first electrode plate (01) and is used as the first electrode plate (01). A first insulating dielectric layer (41) is provided on the inner side wall of the groove (61) and the top of the side wall. A second electrode plate (02) is provided on the insulating dielectric layer (41). The first electrode plate (01), the insulating dielectric layer (41) and the second electrode plate (02) constitute a large capacitance capacitor. For example, for ease of calculation, let's assume a square first electrode plate (01) with a side length of 15 μm has a groove depth-to-width ratio of 30:1. The groove (61) is a square with a side length of 10 μm, and the sidewall height of the groove is 300 μm. The total area of the four sidewalls is 12000 μm². Before the groove is set, the area of the first electrode plate (01) is 225 μm². After the groove (61) is set, the total area of the first electrode plate (01) is 12225 μm², which increases by 12000 μm². This is 54.3 times the area of the electrode plate without the groove. The capacitance value is proportional to the electrode plate area, that is, the capacitance value is 54.3 times that of the electrode plate without the groove (61). Similarly, if the depth-to-width ratio of the groove (61) is 50:1, which is 89.8 times the area of the electrode plate without the groove, the capacitance value is 89.8 times that of the electrode plate without the groove (61). This embodiment greatly increases the capacitance value.
[0053] like Figure 2 As shown, a groove (61) is provided on the first electrode plate (01). The sidewall of the groove (61) is a sidewall (51). The sidewall (51) is made of the same material as the first electrode plate (01) and is used as the first electrode plate (01). A first insulating dielectric layer (41) is provided on the inner sidewall and the top of the sidewall of the groove (61). A second electrode plate (02) is provided on the insulating dielectric layer (41). A second insulating dielectric layer (42) is provided on the second electrode plate (02). A pressure-sensitive electrode plate (31) is provided on the second insulating dielectric layer (42) and the groove (61). At this time, the groove (61) and the pressure-sensitive electrode plate (31) form a cavity (71). The pressure-sensitive plate (31) and the second plate (02) form a variable capacitor C1 whose capacitance changes with pressure, while the first plate (01) and the second plate (02) form a constant capacitor C2. C1 and C2 form a differential capacitor. At this time, the sidewall (51) and the first plate (01) are made of the same material, and the second insulating dielectric layer is made of a high dielectric constant insulating material. The pressure-sensitive plate (31) deforms towards the first plate (01) as the pressure increases, reducing the distance between the two plates and increasing the capacitance value, thereby measuring the pressure value to be measured. Since a high relative dielectric constant material is selected, the change in capacitance C1 is increased, and the output characteristics are as follows: Figure 18As shown, the linearity of the capacitance output characteristics can be significantly improved, the sensitivity and precision can be improved, and the difficulty of back-end data processing can be reduced. Because C1 and C2 form a differential capacitor, common-mode interference can be well shielded, and the chip area can be saved and the integration can be improved.
[0054] As shown in Figure 3 As shown, a plurality of grooves (61) are arranged on the first plate (01), and the side wall (51) is made of the same material as the first plate (01) and is used for the first plate (01), which greatly increases the capacitance value. For example, in order to facilitate calculation, 9 grooves (61) are arranged on a square first plate (01) with a side length of 45um, the groove (61) has a depth-width ratio of 30:1, the groove (61) is a square with a side length of 10um, the groove side wall is 300um high, and the total area of the four side walls of each groove (61) is 12000um². The side wall area of the 9 grooves is 108000um², that is, the plate area is increased by 108000um². The area of the first plate (01) before the groove is set is 2025um², and the total area of the first plate (01) after the 9 grooves (61) are set is 110025um². The plate area is increased by 108000um², which is 54.3 times the area of the plate without the groove. The capacitance value is proportional to the plate area, that is, the capacitance value is 54.3 times that of the groove (61) without the groove. Similarly, if the depth-width ratio of the groove (61) is 50:1, it is 89.8 times the area of the plate without the groove, and the capacitance value is 89.8 times that of the groove (61) without the groove. This embodiment greatly increases the capacitance value.
[0055] For example, in order to facilitate calculation, 4 grooves (61) are arranged on a square first plate (01) with a side length of 15um, the groove (61) has a depth-width ratio of 30:1, the groove (61) is a square with a side length of 6um, the groove side wall is 180um high, and the total area of the four side walls of each groove (61) is 4320um². The side wall area of the 9 grooves is 17280um², that is, the plate area is increased by 17280um². The area of the first plate (01) before the groove is set is 225um², and the total area of the first plate (01) after the 9 grooves (61) are set is 17505um². The plate area is increased by 17280um², which is 77.8 times the area of the plate without the groove. The capacitance value is proportional to the plate area, that is, the capacitance value is 77.8 times that of the groove (61) without the groove. Similarly, if the depth-width ratio of the groove (61) is 50:1, it is 129 times the area of the plate without the groove, and the capacitance value is 129 times that of the groove (61) without the groove. This embodiment greatly increases the capacitance value.
[0056] As shown in Figure 4 , Figure 5As shown, a groove (61) is arranged on the first plate (01), the side wall of the groove (61) is the side wall (51), the side wall (51) is the same material as the first plate (01) and is used as the first plate (01), the inner side wall of the groove (61) and the top of the side wall are provided with a first insulating medium layer (41), the second plate (02) is arranged on the insulating medium layer (41), the first column (55) is arranged in the groove (61), the bottom of the column is the same material as the first plate (01) and is connected, the first column (55) is used as the first plate (01), the first insulating medium layer (41) and the second plate (02) completely cover the first column (55), and a large-capacitance capacitor is formed by the first plate (01), the insulating medium layer (41) and the second plate (02). For example, in order to facilitate calculation, it is assumed that a square first plate (01) with a side length of 15 um is arranged, the groove depth-width ratio is 30:1, the groove (61) is a square with a side length of 10 um, the groove side wall is 300 um high, the total area of the four side walls is 12000 um², the first column (55) is a cube with a height of 300 um and a width of 5 um, the area of the four sides of the column is 6000 um², and the area of the first plate (01) before the groove is arranged is 225 um². After the groove (61) and the first column (55) are arranged, the total area of the first plate (01) is 18225 um², and the area increases by 18000 um², which is 81 times the area of the plate without the groove. The capacitance value is proportional to the plate area, that is, the capacitance value is 81 times that of the plate without the groove (61). Similarly, if the groove depth-width ratio of the groove (61) is 50:1, the first column (55) is a cube with a height of 300 um and a width of 5 um, the plate area is 116.5 times the area of the plate without the groove, and the capacitance value is 116.5 times that of the plate without the groove (61). This embodiment greatly increases the capacitance value. If the groove depth-width ratio of the groove (61) is 50:1, the first column (55) is a cube with a height of 500 um and a width of 5 um, the plate area is 134.3 times the area of the plate without the groove, and the capacitance value is 134.3 times that of the plate without the groove (61). This embodiment greatly increases the capacitance value.
[0057] As shown in the figure, Figure 6 As shown, an annular groove (61) is arranged outside the groove (61), the first column (55) is arranged in the groove (61), the first column (55) is not connected with the side wall (51) of the groove (61), the side wall (51) is the same material as the first plate (01) and is used as the first plate (01), which greatly increases the plate area, the bottom of the column is the same material as the first plate (01) and is connected, and the first column (55) is used as the first plate (01). The first insulating medium layer (41) and the second plate (02) completely cover the first column (55), and a large-capacitance capacitor is formed by the first plate (01), the insulating medium layer (41) and the second plate (02).
[0058] For example, for ease of calculation, on a square first pole plate (01) with a side length of 30 μm, the groove depth-to-width ratio is chosen to be 30:1. The outer annular groove (61) is a square ring with a width of 10 μm, the inner groove (61) is a square with a width of 8 μm, and the first column (55) is a cube with a width of 8 μm and a height of 300 μm. The sidewall of the outer annular groove (61) is 300 μm high and 26 μm wide, with an area of 31200 μm². The sidewall of the inner square groove (61) opposite to the outer annular groove is 300 μm high and 16 μm wide, with an area of 19200 μm². The sidewall of the inner groove (61) opposite to the first column (55) is 300 μm high. m, 14um wide, with an area of 16800um², the side surface of the first column (55) is 300um high, 8um wide, with an area of 9600um², the total area of the side wall is 67200um², the total area of the first electrode plate (01) is 68100um², the area of the first electrode plate (01) before the groove (61) is set is 900um², after setting the inner square groove (61), the outer annular groove (61), and the first column (55), the area increases by 67200um², which is 75.6 times the area of the electrode plate without the groove, the capacitance value is proportional to the electrode plate area, that is, the capacitance value is 75.6 times that of the electrode plate without the groove (61).
[0059] like Figure 7 As shown, a groove (61) is provided on the first electrode plate (01). A first column (55) is provided in both the inner square groove (61) and the outer annular groove. The first column (55) in the outer annular groove is connected to the side wall (51) of the annular groove (61). The side wall (51) is made of the same material as the first electrode plate (01) and is used as the first electrode plate (01), which greatly increases the electrode plate area. The bottom of the column is made of the same material as the first electrode plate (01) and is connected. The first column (55) is used as the first electrode plate (01). The side wall area of multiple first columns (55) is increased, which further increases the electrode plate area and increases the capacitance value. The first insulating dielectric layer (41) and the second electrode plate (02) completely cover the first column (55). The first electrode plate (01), the insulating dielectric layer (41) and the second electrode plate (02) constitute a large capacitance capacitor, which greatly increases the capacitance value.
[0060] like Figure 8 As shown, the upper opening of the sidewall (51) of the groove (61) of the present invention is set as a first arc (56); the connection between the bottom of the groove (61) and the sidewall (51) of the present invention is set as a second arc (57). The setting of the first arc (56) and the second arc (57) can greatly reduce the difficulty of the process, reduce the risk of the process, reduce the risk of circuit breakage, reduce the difficulty of subsequent processes, improve the uniformity of the film, improve the consistency of capacitance, improve the yield, and realize the diversity of processes.
[0061] As Figure 9 The upper opening of the side wall (51) of the groove (61) is provided with a first slope (59), and the connecting part of the bottom of the groove (61) and the side wall (51) is provided with a second slope (58). The arrangement of the second slope (58) and the first slope (59) can greatly reduce the process difficulty, reduce the process risk, reduce the risk of disconnection, reduce the subsequent process difficulty, improve the uniformity of the film, improve the consistency of the capacitor, improve the yield, realize the diversity of the process.
[0062] As Figure 10 The groove (61) is provided in a shape of wide at the top and narrow at the bottom. The arrangement of the groove (61) in this shape can greatly reduce the process difficulty, reduce the process risk, reduce the risk of disconnection, reduce the subsequent process difficulty, improve the uniformity of the film, improve the consistency of the capacitor, improve the yield, and realize the diversity of the process.
[0063] As Figure 11As shown, a recess (61) is arranged on the first plate (01), the side wall of the recess (61) is the side wall (51), the side wall (51) is the same material as the first plate (01), and is used as the first plate (01), the inner side wall of the recess (61) and the top of the side wall are provided with a first insulating medium layer (41), the second plate (02) is arranged on the insulating medium layer (41), the second insulating medium layer (42) is arranged on the second plate (02), and the third plate (03) is arranged on the second insulating medium layer (42). The first plate (01) and the second plate (02) form a capacitor C1, the second plate (02) and the third plate (03) form a capacitor C2, and when the capacitors C1 and C2 are connected in parallel, a capacitor with a larger capacitance value is formed. For example, in order to facilitate calculation, a square first plate (01) with a side length of 15um is arranged, the recess depth-width ratio is 30:1, the recess (61) is a square with a side length of 10um, the recess side wall is 300um high, the total area of the four side walls is 12000um², the area of the first plate (01) before the recess is arranged is 225um², and after the recess (61) is arranged, the total area of the first plate (01) is 12225um², and the total area of the second plate (02) is also close to 12225um². The total area of the third plate (03) is also close to 12225um²; the plate area of the capacitor C1 formed by the first plate (01) and the second plate (02) and the plate area of the capacitor C2 formed by the second plate (02) and the third plate (03) are about 54 times the plate area without the recess, and the capacitance value is proportional to the plate area, that is, the capacitance values of the capacitors C1 and C2 are about 54 times the capacitance value without the recess (61). When the capacitors C1 and C2 are connected in parallel, the capacitance value is about 108 times the capacitance value without the recess (61). Similarly, if the depth-width ratio of the recess (61) is 50:1, the plate area is about 178 times the plate area without the recess, and the capacitance value is about 178 times the capacitance value without the recess (61). This embodiment greatly increases the capacitance value.
[0064] By connecting the capacitors C1 and C2 in series and parallel, it can also be used for voltage rise and fall, rectification, and filtering circuit.
[0065] As Figure 12As shown in the drawings, the recess (61) is arranged on the first electrode plate (01), the side wall of the recess (61) is the side wall (51), the side wall (51) is the same material as the first electrode plate (01), and the first electrode plate (01) is used, the inner side wall of the recess (61) and the top of the side wall are provided with the first insulating medium layer (41), the second electrode plate (02) is arranged on the insulating medium layer (41), the second insulating medium layer (42) is arranged on the second electrode plate (02), and the third electrode plate (03) is arranged on the second insulating medium layer (42); the third insulating medium layer (43) is arranged on the third electrode plate (03), and the fourth electrode plate (04) is arranged on the third insulating medium layer (43); the first electrode plate (01) and the second electrode plate (02) form a capacitor C1, the second electrode plate (02) and the third electrode plate (03) form a capacitor C2, and the third electrode plate (03) and the fourth electrode plate (04) form a capacitor C3; when the capacitors C1, C2 and C3 are connected in parallel, a capacitor with a larger capacitance value is formed. For example, in order to facilitate calculation, a square first electrode plate (01) with a side length of 15um is arranged, a recess (61) with a square shape with a side length of 10um is selected, the depth-width ratio of the recess (61) is 30:1, the height of the recess side wall is 300um, the total area of the four side walls is 12000um², the area of the first electrode plate (01) before the recess is arranged is 225um², after the recess (61) is arranged, the total area of the first electrode plate (01) is 12225um², the total area of the second electrode plate (02) is also close to 12225um², the total area of the third electrode plate (03) is also close to 12225um², and the total area of the fourth electrode plate (04) is also close to 12225um²; the plate area of the capacitor C1 formed by the first electrode plate (01) and the second electrode plate (02), the plate area of the capacitor C2 formed by the second electrode plate (02) and the third electrode plate (03), and the plate area of the capacitor C3 formed by the third electrode plate (03) and the fourth electrode plate (04) are about 54 times the plate area of the electrode plate without the recess, respectively; the capacitance value is proportional to the plate area, that is, the capacitance values of the capacitors C1, C2 and C3 are about 54 times the capacitance value of the electrode plate without the recess (61), respectively; when the capacitors C1, C2 and C3 are connected in parallel, the capacitance value is about 162 times the capacitance value of the electrode plate without the recess (61). Similarly, if the depth-width ratio of the recess (61) is 50:1, the area of the electrode plate without the recess is about 267 times, and the capacitance value is about 267 times the capacitance value of the electrode plate without the recess (61). This embodiment greatly increases the capacitance value.
[0066] By connecting the capacitors C1, C2 and C3 in series and parallel, the voltage can also be raised and lowered, and the rectification and filtering circuit can be used.
[0067] As shown in the drawings, Figure 13 The recess (61) is hexagonal, a plurality of recesses (61) are arranged, adjacent recesses share the side wall (51), the side wall area is larger, the electrode plate area is greatly improved, the capacitance value is greatly increased, the chip area is saved, and the chip height is reduced.
[0068] As Figure 14 shown, the second column (52) fills the free part of the groove (61), the second column (52) is made of the same material as the plate and is used as a plate, the vibration resistance is increased, the top layer is planarized, the semiconductor device can be continuously manufactured on the top layer, integrated circuits are manufactured, and the difficulty of the next step of integrated process is reduced.
[0069] As Figure 15 shown, the second column (52) fills the free part of the groove (61), the second column (52) is made of the same material as the plate and is used as a plate, the vibration resistance is increased, the top layer is planarized, the semiconductor device can be continuously manufactured on the top layer, integrated circuits are manufactured, and the difficulty of the next step of integrated process is reduced.
[0070] As Figure 16 shown, the second column (52) fills the free part of the groove (61), the second column (52) is made of the same material as the plate and is used as a plate, the vibration resistance is increased, the top layer is planarized, the semiconductor device can be continuously manufactured on the top layer, integrated circuits are manufactured, and the difficulty of the next step of integrated process is reduced.
[0071] As Figure 17 shown, when the groove (61) is a polygon, the included angle of adjacent sides is set as a circular arc (53), the setting of the circular arc (53) can greatly reduce the process difficulty, reduce the process risk, reduce the risk of breaking, reduce the subsequent process difficulty, improve the uniformity of the thin film, improve the consistency of the capacitor, improve the yield, realize the diversity of the process.
[0072] As Figure 18As shown, an inner square groove (61) and an outer annular groove (61) are provided on the first electrode plate (01). A first column (55) is provided in both the inner square groove (61) and the outer annular groove (61). The first column (55) is not connected to the side wall (51) of the groove (61). The side wall (51) is made of the same material as the first electrode plate (01) and is used as the first electrode plate (01), which greatly increases the electrode plate area. The bottom of the first column (55) is made of the same material as the first electrode plate (01) and is connected. The first column (55) is used as the first electrode plate (01). The first insulating dielectric layer (41) and the second electrode plate (02) completely cover the first column (55). The side wall area of multiple first columns (55) further increases the electrode plate area. The first electrode plate (01), the insulating dielectric layer (41) and the second electrode plate (02) constitute a large capacitance capacitor, which greatly increases the capacitance value.
[0073] like Figure 19 As shown, as another preferred embodiment, one or more wall grooves (62) are provided on the side wall (51) of the groove (61) of this utility model. When the side wall of the wall groove (62) is made of the same material as the first electrode plate (01), the side wall area of the wall groove (62) increases the electrode plate area, and the capacitance value is proportional to the electrode plate area, thus further increasing the capacitance value.
[0074] like Figure 20 As shown, according to Figure 2 The structure shown has a second electrode (02) that is a square with dimensions of 280µm x 280µm and a film thickness of 5µm. The results obtained using finite element simulation software are as follows: Figure 20 The graph shows the capacitor pressure output characteristic. The horizontal axis represents the pressure value, and the vertical axis represents the output capacitance value. As can be seen from the graph, the linearity of the output characteristic curve is excellent.
[0075] Multiple capacitors can be formed by alternating capacitor plates and insulating dielectric layers. The insulating dielectric layers include, but are not limited to, silicon dioxide, silicon nitride, titanium dioxide, and titanium pentoxide. The dielectric layers can be the same or different. The upper plate (1) and the lower plate (2) can be connected to the external circuit through solder joints and metal leads or solder joints.
[0076] This utility model Figure 1 The structure can be manufactured using the following processes:
[0077] a. Select a silicon wafer with appropriate resistivity and clean it according to the design parameters;
[0078] b. Apply photolithography, homogenize the resist, apply photolithography again, and develop the pattern;
[0079] c. Etching of silicon wafers;
[0080] When the etching process is selected as a wet etching process, a hydrogen fluoride (HF) solution with a proportioning solution is selected, a catalyst is added in the solution, etching speed is ensured and drilling etching is reduced; when the etching process is selected as a dry etching process, a suitable plasma is selected to etch, and a bias voltage of a deep reactive ion etching machine is adjusted, and a flow rate of a gas is input to achieve a better etching effect.
[0081] d. removing glue;
[0082] e. repeating the step c;
[0083] f. etching the silicon wafer;
[0084] According to the design parameter requirement, a suitable aspect ratio is selected, and a silicon dioxide can be used as an etching barrier layer; when the etching process is selected as a wet etching process, a hydrogen fluoride (HF) solution with a proportioning solution is selected, a catalyst is added in the solution, etching speed is ensured and drilling etching is reduced; when the etching process is selected as a dry etching process, a suitable plasma is selected to etch, and a bias voltage of a deep reactive ion etching machine is adjusted, and a flow rate of a gas is input to achieve a better etching effect.
[0085] g. cleaning the silicon wafer;
[0086] h. a first insulating medium layer can be realized by oxidation, CVD, ALD, PVD and the like;
[0087] i. photoetching a pattern;
[0088] j. a metal can be realized by electron beam evaporation, plating, PVD, CVD, ALD;
[0089] k. photoetching a pattern and etching a PAD;
[0090] l. testing;
[0091] m. cutting a wafer.
[0092] The cavity can be provided with a substance with a dielectric constant changing with temperature, and the substance is connected with the outside and can be used as a detection component of a thermometer.
[0093] The utility model can be applied to pressure detection, self-control switch, self-control rectification, silicon microphone, hygrometer, accelerometer, flowmeter and the like.
[0094] It can be understood that the above specific description of the utility model is only used for illustrating the utility model and is not limited to the technical scheme described in the utility model embodiment, and the person skilled in the art should understand that the utility model can still be modified or replaced equivalently to achieve the same technical effect, as long as the use needs are met, which is within the protection scope of the utility model.
Claims
1. A high-capacitance chip structure comprising a first plate (01), characterized in that The first polar plate (01) is provided with a groove (61) on the upper end surface, and the first polar plate (01) is provided with a first insulating medium layer (41) on the upper end surface, and the first insulating medium layer (41) is provided with a second polar plate (02) on the upper end surface; The second polar plate (02) outside the groove (61) is provided with a second insulating medium layer (42), the second insulating medium layer (42) covers the upper end of the groove (61), and a pressure sensing polar plate (31) is arranged on the second insulating medium layer (42); a cavity (71) is formed in the groove (61) below the second insulating medium layer (42), the pressure sensing polar plate (31) and the second polar plate (02) form a variable capacitor C1 whose capacitance value changes with pressure, the first polar plate (01) and the second polar plate (02) form an invariable capacitor C2, and C1 and C2 form a differential capacitor.
2. A high-capacitance chip structure according to claim 1, wherein The groove (61) is provided with a first column (55); the first column (55) is integrated with the first polar plate (01), and the outer wall of the first column (55) is sequentially provided with the first insulating medium layer (41) and the second polar plate (02) from the inside to the outside. Or the groove (61) is provided with an annular groove outside, and the groove (61) and / or the annular groove is provided with a first column (55); the first column (55) is integrated with the first polar plate (01), and the outer wall of the first column (55) is sequentially provided with the first insulating medium layer (41) and the second polar plate (02) from the inside to the outside.
3. A high-capacitance chip structure according to claim 2, wherein The front and rear side walls of the first column (55) in the annular groove (61) are connected with the side walls of the annular groove (61) as part of the first polar plate (01); except that the bottom surface and the side wall of the annular groove (61) of the side wall of the annular groove (61) connected with the front and rear side walls of the first column (55) in the annular groove (61) are sequentially provided with the first insulating medium layer (41) and the second polar plate (02) from the inside to the outside, the left and right side walls of the first column (55) in the annular groove (61) are sequentially provided with the first insulating medium layer (41) and the second polar plate (02) from the inside to the outside.
4. The high-capacitance chip structure according to claim 1, wherein The upper opening of the side wall (51) of the groove (61) is provided with a first circular arc (56) or a first slope (59); And / or the connecting part of the bottom of the groove (61) and the side wall (51) is provided with a second circular arc (57) or a second slope (58).
5. The high-capacitance chip structure according to claim 1, wherein The groove (61) is provided in a shape of being wide at the top and narrow at the bottom, or the groove (61) is provided in a ring shape.
6. A high-capacitance chip structure according to claim 1, wherein The second polar plate (02) is provided with a second insulating medium layer (42), and the third polar plate (03) is arranged on the second insulating medium layer (42), the first polar plate (01) and the second polar plate (02) form a capacitor C1, and the second polar plate (02) and the third polar plate (03) form a capacitor C2. Or a second insulating medium layer (42) is arranged on the second electrode plate (02), and a third electrode plate (03) is arranged on the second insulating medium layer (42); a third insulating medium layer (43) is arranged on the third electrode plate (03), and a fourth electrode plate (04) is arranged on the third insulating medium layer (43); the first electrode plate (01) and the second electrode plate (02) form a capacitor C1, the second electrode plate (02) and the third electrode plate (03) form a capacitor C2, and the third electrode plate (03) and the fourth electrode plate (04) form a capacitor C3.
7. A high-capacitance chip capacitor structure as claimed in claim 1, characterized in that The recess (61) is hexagonal, and adjacent recesses (61) share a side wall (51).
8. A high-capacitance chip capacitor structure as claimed in claim 1, characterized in that The second column (52) fills the recess (61), and the second column (52) is integrated with the second electrode plate (02); Or a second column (52) with a T-shaped cross section fills the recess (61), the lower end of the outer side of the upper part of the second column (52) is connected to the upper end of the second electrode plate (02), and the second column (52) is an insulating medium layer or a semiconductor material layer; Or a second insulating medium layer (42) is arranged on the second electrode plate (02), and a third electrode plate (03) is arranged on the second insulating medium layer (42); a third insulating medium layer (43) is arranged on the third electrode plate (03), and a fourth electrode plate (04) is arranged on the third insulating medium layer (43); the second column (52) fills all the empty parts of the recess (61), and the second column (52) is integrated with the fourth electrode plate (04).
9. A high-capacitance chip capacitor structure as claimed in claim 1, characterized in that The side wall (51) of the recess (61) is provided with a wall groove (62).