Reset control circuit and master control display screen

Abstract

The utility model discloses a reset control circuit and a master control display screen. The reset control circuit comprises a display control chip, a watchdog chip, a monitoring chip and an automatic power-off recovery circuit. A dog feeding input end of the watchdog chip is connected with a dog feeding output end of the display control chip, and a reset output end of the watchdog chip is connected with a reset input end of the display control chip; the monitoring input end of the monitoring chip is connected with the reset output end of the watchdog chip, and the alarm output end of the monitoring chip is connected with the alarm circuit; the self-power-off recovery circuit comprises a switching circuit and an OR gate circuit; one end of a switching path of the switching circuit is connected with a power supply, the other end is connected with a power input end of the display control chip, a control end of the switching circuit is connected with an output end of the OR gate circuit, a first input end of the OR gate circuit is connected with a power control output end of the monitoring chip, and a second input end is connected with a power control output end of the display control chip. According to the utility model, the technical problem of poor reset reliability is solved, and the reset reliability is improved.

Description

Technical Field

[0001] This utility model belongs to the field of circuit technology, specifically, it relates to a reset control circuit and a main control display screen. Background Technology

[0002] Industrial control displays play a crucial role in industrial automation systems. They are used to display production process data, monitor equipment status, and operate industrial robots. They can present real-time data in the form of graphics, charts, and dashboards, helping operators better understand and analyze the data, monitor machine operation in real time, and make corresponding control decisions.

[0003] Industrial control displays have significant application value and broad market prospects in various fields. With the continuous development of technologies such as industrial automation and intelligent manufacturing, the market demand for industrial control displays will continue to grow. However, with the increase in functionality and prolonged uninterrupted operation and use, program freezes and system crashes are inevitable during operation, leading to equipment downtime, reduced production efficiency, and increased equipment maintenance costs.

[0004] When existing industrial main control displays freeze, they generally cannot recover on their own and can only be manually reset using a manual reset button. This results in low automation, poor timeliness, and poor reliability. Summary of the Invention

[0005] This invention provides a reset control circuit, which solves the technical problem of poor reset reliability in the prior art.

[0006] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0007] The reset control circuit includes:

[0008] The display control chip has a dog feed output terminal, a reset input terminal, a power input terminal, and a power control output terminal;

[0009] The watchdog chip has a watchdog input terminal and a reset output terminal; its watchdog input terminal is connected to the watchdog output terminal of the display control chip, and its reset output terminal is connected to the reset input terminal of the display control chip.

[0010] The monitoring chip has a monitoring input terminal, an alarm output terminal, and a power control output terminal; its monitoring input terminal is connected to the reset output terminal of the watchdog chip, and its alarm output terminal is connected to the alarm circuit.

[0011] The self-power-off recovery circuit includes a switching circuit and an OR gate circuit; one end of the switching path of the switching circuit is connected to the power supply, the other end of the switching path of the switching circuit is connected to the power input terminal of the display control chip, the control terminal of the switching circuit is connected to the output terminal of the OR gate circuit, the first input terminal of the OR gate circuit is connected to the power control output terminal of the monitoring chip, and the second input terminal of the OR gate circuit is connected to the power control output terminal of the display control chip.

[0012] In some embodiments of this application, the watchdog chip includes a dog-feeding signal detection circuit, a watchdog timer, a reset signal generation circuit, and a voltage comparator;

[0013] The input terminal of the watchdog signal detection circuit is connected to the watchdog input terminal of the watchdog chip, the output terminal of the watchdog signal detection circuit is connected to the input terminal of the watchdog timer, the output terminal of the watchdog timer is connected to the input terminal of the reset signal generation circuit, and the output terminal of the reset signal generation circuit is connected to the reset output terminal of the watchdog chip.

[0014] One input of the voltage comparator is connected to the power input of the watchdog chip, the other input of the voltage comparator is connected to the reference power supply, and the output of the voltage comparator is connected to the input of the reset signal generation circuit.

[0015] In some embodiments of this application, the monitoring chip includes a reset signal detection circuit, a counter, a digital comparator, and a controller;

[0016] The input terminal of the reset signal detection circuit is connected to the monitoring input terminal of the monitoring chip, the output terminal of the reset signal detection circuit is connected to the input terminal of the counter, the output terminal of the counter is connected to one input terminal of the digital comparator, the other input terminal of the digital comparator is connected to the reference threshold, the output terminal of the digital comparator is connected to the input terminal of the controller, the first output terminal of the controller is connected to the alarm output terminal of the monitoring chip, and the second output terminal of the controller is connected to the power control output terminal of the monitoring chip.

[0017] In some embodiments of this application, the alarm circuit includes a switching transistor, a buzzer, a first resistor, and a second resistor;

[0018] The control terminal of the switching transistor is connected to the alarm output terminal of the monitoring chip;

[0019] One end of the switching path of the switching transistor is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the DC power supply.

[0020] The other end of the switching path of the switching transistor is grounded;

[0021] The buzzer is connected in parallel with the first resistor.

[0022] In some embodiments of this application, the watchdog chip has a manual reset input terminal, which is connected to the input terminal of the reset signal generation circuit;

[0023] The manual reset input terminal is grounded via a TVS diode;

[0024] The manual reset input terminal is grounded through the first filter capacitor.

[0025] In some embodiments of this application, the serial port input terminal of the display control chip is connected to the serial port output terminal of the monitoring chip;

[0026] The serial port output of the display control chip is connected to the serial port input of the monitoring chip.

[0027] In some embodiments of this application, the reset input terminal of the display control chip is connected to a DC power supply via a pull-up resistor;

[0028] The reset input terminal of the display control chip is grounded through the second filter capacitor.

[0029] In some embodiments of this application, the switching circuit includes a PMOS transistor, the source of which is connected to the power supply, the drain of which is connected to the power input terminal of the display control chip, and the gate of which is connected to the output terminal of the OR gate circuit.

[0030] In some embodiments of this application, the switching circuit includes a PNP transistor, the emitter of which is connected to the power supply, the collector of which is connected to the power input terminal of the display control chip, and the base of which is connected to the output terminal of the OR gate circuit.

[0031] Based on the design of the above-mentioned reset control circuit, this utility model also proposes a main control display screen, including the aforementioned reset control circuit.

[0032] Compared with the prior art, the advantages and positive effects of this utility model are as follows: The reset control circuit and main control display screen of this utility model utilize the watchdog chip IC2's feed input terminal WDI to connect to the display control chip IC1's feed output terminal PD15, and the watchdog chip IC2's reset output terminal... Connect the reset input terminal NSET of the display control chip IC1. When the watchdog chip IC2 does not receive a feed signal, its reset output terminal... Output a reset signal to the reset input terminal NSET of the display control chip IC1 to control the reset of the display control chip IC1; use the monitoring input terminal P06 of the monitoring chip IC3 to monitor the reset output terminal of the watchdog chip IC2. When the number of reset signals detected exceeds a set number, the monitoring chip IC3 outputs a shutdown signal to the OR gate circuit OR1, controlling the switch circuit to turn off and cutting off the power supply to the display control chip IC1. Then, the monitoring chip IC3 outputs a conduction signal to the OR gate circuit OR1 again, restoring the power supply to the display control chip IC1, causing it to power on and restart. Furthermore, the monitoring chip IC3 outputs an alarm signal to the alarm circuit, controlling it to sound an alarm to alert the user. Therefore, the reset control circuit of this invention monitors the watchdog signal of the display control chip IC1 through the watchdog chip IC2. When an abnormality is detected in the watchdog signal, it controls the display control chip IC1 to reset via a reset signal. The monitoring chip IC3 monitors the reset signal output by the watchdog chip IC2. When an abnormality is detected, it controls the display control chip IC1 to power off and then power on again. This dual monitoring by the watchdog chip IC2 and the monitoring chip IC3 solves the technical problem of poor reset reliability in existing technologies and improves reset reliability.

[0033] Other features and advantages of this utility model will become clearer after reading the detailed description of the embodiments of this utility model in conjunction with the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a circuit structure block diagram of one embodiment of the reset control circuit proposed in this utility model;

[0036] Figure 2 This is a circuit diagram of one embodiment of the reset control circuit proposed in this utility model;

[0037] Figure 3 This is a circuit block diagram of one embodiment of a watchdog chip;

[0038] Figure 4 This is a circuit structure block diagram of one embodiment of a monitoring chip. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.

[0040] It should be noted that in the description of this utility model, the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," which indicate directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. These are used merely for ease of description and do not indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] Furthermore, it should be noted that, in the description of this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0042] Example 1

[0043] The reset control circuit in this embodiment includes a display control chip IC1, a watchdog chip IC2, a monitoring chip IC3, a power-off recovery circuit, an alarm circuit, etc. (See also...) Figure 1 , Figure 2 As shown.

[0044] The display control chip IC1 is the core component of the main control display screen, controlling the operation of the entire main control display screen.

[0045] The display control chip IC1 has a dog feed output terminal PD15, a reset input terminal NSET, a power input terminal, and a power control output terminal PD12.

[0046] The watchdog chip IC2 has a feed input (WDI) and a reset output. The watchdog chip IC2's feed input terminal WDI is connected to the display control chip IC1's feed output terminal PD15, and the watchdog chip IC2's reset output terminal. Connect the reset input terminal NSET of the display control chip IC1.

[0047] The monitoring chip IC3 has a monitoring input terminal P06, an alarm output terminal P10, and a power control output terminal P01. The monitoring input terminal P06 of monitoring chip IC3 is connected to the reset output terminal of watchdog chip IC2. The alarm output terminal P10 of the monitoring chip IC3 is connected to the alarm circuit.

[0048] The self-power-off recovery circuit includes a switching circuit and an OR gate circuit OR1. One end of the switching path of the switching circuit is connected to the power supply, and the other end of the switching path of the switching circuit is connected to the power input terminal of the display control chip IC1. The control terminal of the switching circuit is connected to the output terminal of the OR gate circuit OR1. The first input terminal of the OR gate circuit OR1 is connected to the power control output terminal P01 of the monitoring chip IC3, and the second input terminal of the OR gate circuit OR1 is connected to the power control output terminal PD12 of the display control chip IC1.

[0049] The power supply provides power to the display control chip IC1 through the switching path of the switching circuit.

[0050] When both the power control output terminal PD12 of the display control chip IC1 and the power control output terminal P01 of the monitoring chip IC3 output a conduction signal (such as a low level) to the OR gate circuit OR1, the output terminal of the OR gate circuit OR1 outputs a conduction signal (such as a low level).

[0051] When the power control output terminal PD12 of the display control chip IC1 or the power control output terminal P01 of the monitoring chip IC3 outputs a shutdown signal (such as a high level) to the OR gate circuit OR1, the output terminal of the OR gate circuit OR1 outputs a shutdown signal (such as a high level).

[0052] The power control output terminal PD12 of the display control chip IC1 typically outputs a turn-on signal (such as a low level) to the second input terminal of the OR gate circuit OR1.

[0053] When the display control chip IC1 is operating normally, its watchdog output terminal PD15 sends a watchdog signal to the watchdog input terminal WDI of the watchdog chip IC2 every first set interval (e.g., every 1 second). If the watchdog chip IC2 does not receive a watchdog signal after a second set interval (the second set interval is longer than the first set interval, e.g., 1.6 seconds), it indicates that the display control chip IC1 is malfunctioning, and the reset output terminal of the watchdog chip IC2 will then be activated. The reset signal is output to the reset input terminal NSET of the display control chip IC1. The display control chip IC1 will reset after receiving the reset signal.

[0054] The monitoring input terminal P06 of the monitoring chip IC3 listens to the reset output terminal of the watchdog chip IC2. The monitoring chip IC3 records the number of times the reset signal is detected (using an internal counter). When the number of detected reset signals exceeds a set number (achieved via an internal digital comparator), it indicates a malfunction in the reset function of the display control chip IC1. In this case, the power control output P01 of the monitoring chip IC3 outputs a high-level shutdown signal to the first input of the OR gate OR1, and the output of the OR gate OR1 outputs a high-level shutdown signal to the control terminal of the switching circuit, controlling the switching circuit to turn off and thus disconnecting the power supply to the display control chip IC1. Furthermore, the alarm output P10 of the monitoring chip IC3 outputs an alarm signal to the alarm circuit, triggering an alarm to alert the user.

[0055] After a period of time, the power control output terminal P01 of the monitoring chip IC3 outputs a low-level conduction signal to the first input terminal of the OR gate circuit OR1. Since the display control chip IC1 is powered off, its power control output terminal PD12 is at a low level, which pulls the second input terminal of the OR gate circuit OR1 low as well. Therefore, the output terminal of the OR gate circuit OR1 outputs a low-level conduction signal to the control terminal of the switching circuit, controlling the switching circuit to conduct, thereby restoring the power supply to the display control chip IC1, so that the display control chip IC1 is powered on and restarted.

[0056] In this embodiment, the reset control circuit utilizes the watchdog chip IC2's feed input terminal WDI to connect to the display control chip IC1's feed output terminal PD15, and the watchdog chip IC2's reset output terminal... Connect the reset input terminal NSET of the display control chip IC1. When the watchdog chip IC2 does not receive a feed signal, its reset output terminal... Output a reset signal to the reset input terminal NSET of the display control chip IC1 to control the reset of the display control chip IC1; use the monitoring input terminal P06 of the monitoring chip IC3 to monitor the reset output terminal of the watchdog chip IC2. When the number of reset signals detected exceeds a set number, the monitoring chip IC3 outputs a shutdown signal to the OR gate circuit OR1, controlling the switch circuit to turn off and cutting off the power supply to the display control chip IC1. Then, the monitoring chip IC3 outputs a conduction signal to the OR gate circuit OR1 again, restoring the power supply to the display control chip IC1, causing it to power on and restart. Furthermore, the monitoring chip IC3 outputs an alarm signal to the alarm circuit, controlling it to sound an alarm to alert the user. Therefore, the reset control circuit in this embodiment monitors the watchdog signal of the display control chip IC1 through the watchdog chip IC2. When an abnormality is detected in the watchdog signal, it controls the display control chip IC1 to reset via a reset signal. The monitoring chip IC3 monitors the reset signal output by the watchdog chip IC2. When an abnormality is detected, it controls the display control chip IC1 to power off and then power on again. This dual monitoring by the watchdog chip IC2 and the monitoring chip IC3 solves the technical problem of poor reset reliability in the prior art and improves reset reliability.

[0057] In this embodiment, the reset control circuit uses watchdog chip IC2 to monitor display control chip IC1. When display control chip IC1 experiences a crash or other problems, the watchdog signal will be abnormal. When watchdog chip IC2 detects the abnormal watchdog signal, it controls display control chip IC1 to reset. Monitoring chip IC3 monitors watchdog chip IC2 in real time. When the reset module function of display control chip IC1 fails, the number of reset signals output by watchdog chip IC2 will be abnormal. Therefore, when monitoring chip IC3 detects the abnormal reset signal, it controls display control chip IC1 to power off and then power on to restart.

[0058] In this embodiment, the reset control circuit uses a watchdog chip IC2 that receives a feed signal from the display control chip IC1. When an abnormal feed signal is detected, the watchdog chip IC2 sends a reset signal to the display control chip IC1 to reset it. The monitoring chip IC3 monitors both the watchdog chip IC2 and the display control chip IC1. If the reset module of the display control chip IC1 fails, it sends a shutdown signal to the self-power-off recovery circuit and controls the alarm circuit to sound an alarm.

[0059] In this embodiment, the reset control circuit monitors the reset module function of the display control chip IC1 through the monitoring chip IC3, ensuring the reliability of the reset function, preventing the reset function from failing, and improving the reliability of the entire circuit.

[0060] In some embodiments of this application, the watchdog chip IC2 includes a watchdog signal detection circuit, a watchdog timer, a reset signal generation circuit, a voltage comparator, etc. See [link to relevant documentation]. Figure 3 As shown.

[0061] The input of the watchdog signal detection circuit is connected to the WDI input of the watchdog chip IC2. The output of the watchdog signal detection circuit is connected to the input of the watchdog timer. The output of the watchdog timer is connected to the input of the reset signal generation circuit. The output of the reset signal generation circuit is connected to the reset output of the watchdog chip IC2. The reset signal generation circuit is used to generate a reset signal.

[0062] The dog-feed signal detection circuit is used to detect the dog-feed signal, that is, to detect the level of the dog-feed input terminal WDI. For example, when the dog-feed signal detection circuit detects that the dog-feed input terminal WDI is high, it means that a valid dog-feed signal has been detected.

[0063] One input of the voltage comparator (e.g., the non-inverting input) is connected to the power input VCC of the watchdog chip IC2, and the other input (e.g., the inverting input) is connected to a reference power supply. The output of the voltage comparator is connected to the input of the reset signal generation circuit. The power input VCC is connected to a DC power supply (e.g., a 3.3V DC power supply).

[0064] When the display control chip IC1 is operating normally, its watchdog output terminal PD15 sends a high-level watchdog signal to the watchdog input terminal WDI of the watchdog chip IC2 every first set time interval (e.g., every 1 second).

[0065] When the watchdog signal detection circuit detects a high level at the watchdog input WDI, it indicates that a watchdog signal has been detected. When the watchdog signal detection circuit detects a low level at the watchdog input WDI, it indicates that no watchdog signal has been detected. In this case, a timing signal is sent to the watchdog timer, and the watchdog timer starts timing. When the timing exceeds a certain duration (e.g., 1.6 seconds), the watchdog timer overflows, and its output terminal outputs a low-level control signal to the input terminal of the reset signal generation circuit. Upon receiving the low-level control signal, the reset signal generation circuit generates a low-level valid reset signal and sends it to the reset output terminal. Reset output terminal The signal is sent to the reset input terminal NSET of the display control chip IC1 to control the display control chip IC1 to reset.

[0066] The voltage comparator compares the voltage at the power input terminal VCC of the watchdog chip IC2 with the voltage of a reference power supply (e.g., 1.2V). The power input terminal VCC is connected to a DC power supply (e.g., 3.3V DC power supply). When the voltage at the power input terminal VCC is lower than the voltage of the reference power supply, the voltage comparator outputs a low-level control signal to the input terminal of the reset signal generation circuit, controlling the reset signal generation circuit to generate a low-level active reset signal to control the display control chip IC1 to reset.

[0067] Therefore, by designing a voltage comparator, the watchdog chip IC2 can still generate a reset signal when the voltage at the power input terminal VCC is lower than the voltage at the reference power supply.

[0068] By designing the watchdog chip with the above structure, the function of monitoring and resetting the display control chip IC1 is realized. Moreover, the circuit structure is simple, easy to build, and low in cost.

[0069] In some embodiments of this application, the watchdog chip IC2's feed input terminal WDI is grounded through a pull-down resistor R3.

[0070] The display control chip IC1 sends a high-level valid feed signal to the feed input WDI of the watchdog chip IC2 via its feed output terminal PD15. When the feed signal is high, the watchdog chip IC2 indicates that a valid feed signal has been detected at its feed input WDI.

[0071] Therefore, when the watchdog chip IC2's feed input terminal WDI does not receive a feed signal from the display control chip IC1, it is grounded through pull-down resistor R3 to maintain a low level and prevent misinterpretation as receiving a feed signal. When the watchdog chip IC2's feed input terminal WDI receives a high-level valid feed signal from the display control chip IC1, it is determined that a feed signal has been received.

[0072] In some embodiments of this application, to further improve the reset reliability of the display control chip IC1, the watchdog chip IC2 has a manual reset terminal. Manual reset input terminal Connect to the input terminal of the reset signal generation circuit.

[0073] When the manual reset input terminal of watchdog chip IC2 When the signal is low, the reset signal generation circuit generates a low-level active reset signal.

[0074] The manual reset input is grounded via a TVS diode, which can prevent the watchdog chip IC2 from being damaged by voltage spikes.

[0075] The manual reset input is grounded through the first filter capacitor C1 to prevent interference from high-frequency waves.

[0076] The manual reset input is connected to a DC power supply (e.g., 3.3V) via a pull-up resistor R1. When the manual reset input is low, the reset signal generation circuit generates a reset signal.

[0077] In some embodiments of this application, the monitoring chip IC3 includes a reset signal detection circuit, a counter, a digital comparator, a controller, etc., see [link to relevant documentation]. Figure 4 As shown.

[0078] The input terminal of the reset signal detection circuit is connected to the monitoring input terminal P06 of the monitoring chip IC3. The output terminal of the reset signal detection circuit is connected to the input terminal of the counter. The output terminal of the counter is connected to one input terminal of the digital comparator (such as the non-inverting input terminal). The other input terminal of the digital comparator (such as the inverting input terminal) is connected to the reference threshold (set number of times). The output terminal of the digital comparator is connected to the input terminal of the controller. The first output terminal of the controller is connected to the alarm output terminal P10 of the monitoring chip IC3. The second output terminal of the controller is connected to the power control output terminal P01 of the monitoring chip IC3.

[0079] The reset signal detection circuit is used to detect the reset signal, that is, to detect the high or low level of the monitoring input terminal P06.

[0080] The monitoring input terminal P06 of the monitoring chip IC3 listens for the reset signal. When the reset signal detection circuit detects that the monitoring input terminal P06 is low, it indicates that a valid reset signal has been detected, and sends a counting signal to the counter. The counter counts the number of times the reset signal is detected. The counter outputs the recorded number to the digital comparator. When the number output by the counter is greater than the reference threshold (set number), the digital comparator outputs a control signal (such as a high level) to the controller. The second output terminal of the controller outputs a shutdown signal to the power control output terminal P01 to control the switching circuit to turn off. The first output terminal of the controller outputs an alarm signal to the alarm output terminal P10 to control the alarm circuit to sound.

[0081] When the controller receives a control signal (such as a high level) from the digital comparator, it resets the counter to zero.

[0082] By designing the monitoring chip IC3 with the above structure, the functions of monitoring watchdog chip IC2 and display control chip IC1 are realized. Moreover, the circuit structure is simple, easy to build, and low in cost.

[0083] In some embodiments of this application, in order to improve the operational reliability of the reset control circuit, the serial port input terminal PD13 of the display control chip IC1 is connected to the serial port output terminal P03 of the monitoring chip IC3; the serial port output terminal PD14 of the display control chip IC1 is connected to the serial port input terminal P05 of the monitoring chip IC3.

[0084] The serial output terminal PD14 of the display control chip IC1 sends a communication signal to the serial input terminal P05 of the monitoring chip IC3. If the monitoring chip IC3 is operating normally, after receiving the communication signal, its serial output terminal P03 will send a feedback signal to the serial input terminal PD13 of the display control chip IC1. The display control chip IC1 and the monitoring chip IC3 communicate in real time via the serial port to achieve mutual real-time monitoring. If communication fails, it indicates that the monitoring chip IC3 may be damaged. In this case, the display control chip IC1 sends an alarm signal to the alarm circuit, which then activates the alarm to promptly alert the user.

[0085] The serial port output P03 of the monitoring chip IC3 sends a communication signal to the serial port input PD13 of the display control chip IC1. If the display control chip IC1 is operating normally, upon receiving the communication signal, its serial port output PD14 will send a feedback signal to the serial port input P05 of the monitoring chip IC3. The monitoring chip IC3 and the display control chip IC1 communicate in real time via the serial port, enabling mutual real-time monitoring. If communication fails, it indicates that the display control chip IC1 may be damaged. In this case, the monitoring chip IC3 sends an alarm signal to the alarm circuit, which then activates the alarm to promptly alert the user.

[0086] In some embodiments of this application, to prevent the display control chip IC1 from being falsely triggered for reset, the reset input terminal NSET of the display control chip IC1 is connected to a DC power supply (such as a 3.3V DC power supply) through a pull-up resistor R7. The reset input terminal NSET of the display control chip IC1 is grounded through a second filter capacitor C3, which serves as a filter to prevent false triggering for reset.

[0087] The display control chip IC1 resets when its reset input NSET is low. The reset input NSET is connected to a DC power supply via pull-up resistor R7 to maintain a high level and prevent false resets. The watchdog chip IC2's reset output... When a low-level reset signal is output to the reset input terminal NSET of the display control chip IC1, the reset input terminal NSET is pulled low, and the display control chip IC1 is reset.

[0088] In some embodiments of this application, the alarm circuit includes a switching transistor N1, a buzzer BUZZ1, a first resistor R5, and a second resistor R6. See [link to relevant documentation]. Figure 2 As shown.

[0089] The control terminal of the switching transistor N1 is connected to the alarm output terminal P10 of the monitoring chip IC3; one end of the switching path of the switching transistor N1 is connected to one end of the first resistor R5, the other end of the first resistor R5 is connected to one end of the second resistor R6, and the other end of the second resistor R6 is connected to a DC power supply (such as a 5V DC power supply); the other end of the switching path of the switching transistor N1 is grounded; the buzzer BUZZ1 is connected in parallel with the first resistor R5.

[0090] Switch N1 is a high on-state voltage drop switch. For example, switch N1 is an NPN transistor.

[0091] The alarm output terminal P10 of the monitoring chip IC3 outputs an alarm signal (such as a high level) to the control terminal of the switching transistor N1, which controls the switching transistor N1 to conduct. The DC power supply then powers the buzzer BUZZ1, and the buzzer BUZZ1 emits an alarm sound to remind the user.

[0092] The alarm circuit designed with the above structure is simple, easy to implement, and low in cost.

[0093] In some embodiments of this application, the switching circuit includes a PMOS transistor, the source of which is connected to the power supply, the drain of which is connected to the power input terminal of the display control chip IC1, and the gate of which is connected to the output terminal of the OR gate circuit OR1.

[0094] When the output of OR gate circuit OR1 outputs a low-level conduction signal to the gate of PMOS transistor, PMOS transistor conducts, and power supply is supplied to display control chip IC1 through the switching path of PMOS transistor.

[0095] When the output of OR gate circuit OR1 outputs a high-level turn-off signal to the gate of PMOS transistor, PMOS transistor is turned off, and the power supply cannot supply power to display control chip IC1.

[0096] PMOS transistors offer stable performance, low cost, and easy on / off control.

[0097] In some embodiments of this application, the switching circuit includes a PNP transistor, the emitter of which is connected to the power supply, the collector of which is connected to the power input terminal of the display control chip IC1, and the base of which is connected to the output terminal of the OR gate circuit OR1.

[0098] When the output of OR gate OR1 outputs a low-level conduction signal to the base of the PNP transistor, the PNP transistor conducts, and the power supply supplies power to the display control chip IC1 through the switching path of the PNP transistor.

[0099] When the output of OR gate OR1 outputs a high-level turn-off signal to the base of the PNP transistor, the PNP transistor is turned off, and the power supply cannot supply power to the display control chip IC1.

[0100] PNP transistors offer stable performance, low cost, and easy on / off control.

[0101] The reset control circuit in this embodiment, by adding an external hardware watchdog chip, monitoring chip, alarm circuit, and self-power-off recovery circuit, monitors the operating status of the display control chip IC1 in real time and monitors whether the reset module of the display control chip IC1 is functioning properly. It will promptly issue an alarm when a reset module failure is detected. When problems such as program freezes or screen crashes occur, it can proactively monitor, respond proactively, and handle them in real time. Even if multiple resets fail to restore functionality, the alarm circuit will promptly notify personnel, ensuring high reliability and timeliness.

[0102] In this embodiment, the reset control circuit monitors the display control chip IC1 in real time through the watchdog chip IC2 and the monitoring chip IC3. In case of system crashes or other problems, it can restart via either a reset or a power outage. The monitoring chip IC3 and the display control chip IC1 can detect each other, providing early warning when the monitoring chip IC3 fails.

[0103] When the display control chip IC1 is operating normally, it sends a "feed" signal to the external watchdog chip IC2 every second. The display control chip IC1 counts the "feed" signals sent to the watchdog chip IC2. If five consecutive "feed" signals are sent, the display control chip IC1 first resets the count, and then communicates with the monitoring chip IC3. This allows the monitoring chip IC3 and the display control chip IC1 to monitor each other in real time, forming a closed loop. If communication fails, it indicates that the monitoring chip IC3 may be faulty, and the display control chip IC1 will control the alarm circuit to issue a warning. If communication is successful, it means that both the display control chip IC1 and the monitoring chip IC3 are operating normally.

[0104] When monitoring chip IC3 detects a reset signal, it first checks whether watchdog chip IC2 has sent three consecutive reset signals within 30 seconds. If not, the reset module of display control chip IC1 is functioning correctly. If so, monitoring chip IC3 will actively communicate with display control chip IC1. If communication fails, a simple reset is deemed ineffective. If display control chip IC1 experiences no more than two power outages within 120 seconds, the monitoring chip controls the self-power-off recovery circuit to power off for 5 seconds and then resume operation. If power outages occur more than twice within 120 seconds, display control chip IC1 is considered to have completely failed, and the monitoring chip activates the alarm circuit to notify personnel.

[0105] The watchdog chip IC2 maintains normal operation via a watchdog signal. When the display control chip IC1 malfunctions, the reset output of the watchdog chip IC2 sends a reset signal to reset the display control chip IC1. Simultaneously, the reset signal is also monitored by the monitoring chip IC3. During normal operation, the monitoring chip IC3 communicates with the display control chip IC1, checking their respective statuses. When the reset module of the display control chip IC1 malfunctions, the monitoring chip IC3 sends a shutdown signal to the self-power-off recovery circuit, controlling the display control chip IC1 to power off and then power on again for restart, and also controlling the alarm circuit to sound an alarm.

[0106] Example 2

[0107] Based on the design of the reset control circuit in Embodiment 1, Embodiment 2 proposes a main control display screen, including the aforementioned reset control circuit.

[0108] By designing a reset control circuit in the main control display screen, the technical problem of poor reset reliability of the main control display screen in the prior art is solved, and the reset reliability of the main control display screen is improved.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A reset control circuit, characterized by: It comprises: a display control chip with a watchdog output end, a reset input end, a power supply input end, and a power supply control output end; a watchdog chip with a watchdog input end and a reset output end; the watchdog input end of which is connected to the watchdog output end of the display control chip, and the reset output end of which is connected to the reset input end of the display control chip; a monitoring chip with a monitoring input end, an alarm output end, and a power supply control output end; the monitoring input end of which is connected to the reset output end of the watchdog chip, and the alarm output end of which is connected to an alarm circuit; a self-power-off recovery circuit comprising a switch circuit and an OR gate circuit; one end of the switch path of the switch circuit is connected to a power supply, the other end of the switch path of the switch circuit is connected to the power supply input end of the display control chip, the control end of the switch circuit is connected to the output end of the OR gate circuit, the first input end of the OR gate circuit is connected to the power supply control output end of the monitoring chip, and the second input end of the OR gate circuit is connected to the power supply control output end of the display control chip.

2. The reset control circuit according to claim 1, characterized in that: the watchdog chip comprises a watchdog signal detection circuit, a watchdog timer, a reset signal generation circuit, and a voltage comparator; the input end of the watchdog signal detection circuit is connected to the watchdog input end of the watchdog chip, the output end of the watchdog signal detection circuit is connected to the input end of the watchdog timer, the output end of the watchdog timer is connected to the input end of the reset signal generation circuit, and the output end of the reset signal generation circuit is connected to the reset output end of the watchdog chip; one input end of the voltage comparator is connected to the power supply input end of the watchdog chip, the other input end of the voltage comparator is connected to a reference power supply, and the output end of the voltage comparator is connected to the input end of the reset signal generation circuit.

3. The reset control circuit according to claim 1, characterized in that: the monitoring chip comprises a reset signal detection circuit, a counter, a digital comparator, and a controller; the input end of the reset signal detection circuit is connected to the monitoring input end of the monitoring chip, the output end of the reset signal detection circuit is connected to the input end of the counter, the output end of the counter is connected to one input end of the digital comparator, the other input end of the digital comparator is connected to a reference threshold, the output end of the digital comparator is connected to the input end of the controller, the first output end of the controller is connected to the alarm output end of the monitoring chip, and the second output end of the controller is connected to the power supply control output end of the monitoring chip.

4. The reset control circuit according to claim 1, characterized in that: the alarm circuit comprises a switch tube, a buzzer, a first resistor, and a second resistor; the control end of the switch tube is connected to the alarm output end of the monitoring chip; one end of the switch path of the switch tube is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is connected to a direct current power supply; the other end of the switch path of the switch tube is grounded; the buzzer is connected in parallel with the first resistor.

5. The reset control circuit according to claim 2, characterized in that: the watchdog chip has a manual reset input connected to the input of the reset signal generation circuit; the manual reset input is grounded through a TVS diode; the manual reset input is grounded through a first filter capacitor.

6. The reset control circuit according to claim 1, characterized in that: the serial input of the display control chip is connected to the serial output of the monitoring chip; the serial output of the display control chip is connected to the serial input of the monitoring chip.

7. The reset control circuit according to claim 1, characterized in that: the reset input of the display control chip is connected to the DC power supply through a pull-up resistor; the reset input of the display control chip is grounded through a second filter capacitor.

8. The reset control circuit according to any one of claims 1 to 7, characterized in that: the switch circuit includes a PMOS transistor, the source of the PMOS transistor is connected to the power supply, the drain of the PMOS transistor is connected to the power input of the display control chip, and the gate of the PMOS transistor is connected to the output of the OR gate circuit.

9. The reset control circuit according to any one of claims 1 to 7, characterized in that: the switch circuit includes a PNP transistor, the emitter of the PNP transistor is connected to the power supply, the collector of the PNP transistor is connected to the power input of the display control chip, and the base of the PNP transistor is connected to the output of the OR gate circuit.

10. A master control display, characterized by: The reset control circuit as claimed in any one of claims 1 to 9 is included.

Images