Dead time adjusting circuit and active clamping forward power supply chip
By designing a dead-time adjustment circuit, the problem of the inability to adjust the dead time in traditional active clamp forward power supplies is solved, enabling flexible adjustment of the dead time and improving power conversion efficiency and circuit adaptability.
Patent Information
- Application Number
- CN202520347837.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2035-02-28
AI Technical Summary
In traditional active clamped forward power supplies, the control of dead time relies on fixed circuit parameters, which cannot be adjusted according to actual needs, thus affecting control performance and conversion efficiency.
A dead-time adjustment circuit was designed, including a current detection module, a digital control output module, a variable current output module, and a dead-time selection module. The dead-time is adjustable through synergistic action, and different delay paths are selected by current detection and digital control logic signals.
It enables flexible adjustment of dead time, improves power conversion efficiency, reduces switching losses, enhances circuit adaptability and stability, and is suitable for various active clamp forward power supply architectures.
Smart Images
Figure CN223928228U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to switch power control technical field especially relates to a dead time regulation circuit and active clamp forward power supply chip. BACKGROUND
[0002] As a common power conversion circuit, active clamp forward power supply is widely used in small and medium scale power converters due to its simple structure, reliable operation and low cost.
[0003] However, the traditional active clamp forward power supply has an inherent defect: during the off period of the main switch tube, a reset circuit must be added to realize the magnetic reset of the high-frequency transformer in order to prevent the transformer core from saturating. In the active clamp topology, a buffer time, i.e. dead time or overlap time, needs to be set between the gate drive signal of the main power switch tube and the gate drive signal of the clamp switch tube to avoid simultaneous conduction. In the traditional design, the control of the dead time depends on fixed circuit parameters such as the preset values of resistance and capacitance. This fixed dead time design cannot be adjusted according to actual needs, thereby affecting the control performance and reducing the conversion efficiency. SUMMARY
[0004] The utility model provides a dead time regulation circuit and active clamp forward power supply chip to solve the technical problem that the dead time cannot be adjusted in the prior art.
[0005] On the one hand, the utility model provides a dead time regulation circuit, comprising:
[0006] A current detection module is used to detect the current flowing through the pin OVLP through the resistance of the pin OVLP to ground and output a digital control logic signal and a mirror current source;
[0007] A digital control output module is connected with the current detection module, used to receive the digital control logic signal and convert it into a control selection signal to determine the selected dead time;
[0008] A variable current output module is connected with the current detection module, used to output a variable current according to the mirror current source to provide the current required for the delay of the dead time selection module;
[0009] A dead time selection module is connected with the digital control output module, used to select the dead time path according to the control selection signal and realize the delay function by using the current of the variable current output module to output the dead time control signal.
[0010] According to the dead time regulation circuit provided by the utility model, the current detection module comprises:
[0011] A current sampling unit is used to detect the current flowing through the pin OVLP through the resistance of the pin OVLP to ground;
[0012] A signal conversion unit is connected with the current sampling unit and is used to convert the sampled current signal into a digital control logic signal;
[0013] A current mirror unit is connected with the signal conversion unit and is used to generate a mirror current source according to the sampling current.
[0014] According to the dead time adjusting circuit, the current sampling unit comprises:
[0015] The source electrode of the switch tube M13 is connected with the source electrode of the switch tube M14, the gate electrode of the switch tube M13 is connected with the pin OVLP, and the drain electrode of the switch tube M13 is connected with the drain electrode of the switch tube M15;
[0016] The gate electrode of the switch tube M14 is connected with the reference voltage vref, and the drain electrode of the switch tube M14 is connected with the drain electrode of the switch tube M16;
[0017] The source electrodes of the switch tube M15 and the switch tube M16 are connected.
[0018] According to the dead time adjusting circuit, the current mirror unit comprises:
[0019] The switch tube M1, the switch tube M2, the switch tube M3, the switch tube M4, the switch tube M5, the switch tube M6 and the switch tube M7 are connected with each other.
[0020] The source electrodes of the switch tube M1, the switch tube M2, the switch tube M3, the switch tube M4, the switch tube M5, the switch tube M6 and the switch tube M7 are connected with each other.
[0021] The gate electrode of the switch tube M1 is connected with the drain electrode, and is connected with the bias current source ibias;
[0022] The drain electrode of the switch tube M2 is connected with the source electrode of the switch tube M13 and the source electrode of the switch tube M14;
[0023] The gate electrode of the switch tube M7 is connected with the drain electrode.
[0024] The gate electrode of the switch tube M7 is connected with the drain electrode.
[0025] According to the dead time adjusting circuit, the signal conversion unit comprises:
[0026] The switch tube M17, the switch tube M18, the switch tube M19, the switch tube M20, the switch tube M21 and the switch tube M23;
[0027] The source of the switch tube M17 is connected with the drain of the switch tube M13 and the drain of the switch tube M15.
[0028] The source of the switch tube M18 is connected with the drain of the switch tube M14 and the drain of the switch tube M16.
[0029] The drain of the switch tube M17 is connected with the drain of the switch tube M3, and the gate of the switch tube M17 is connected with the gate of the switch tube M18 after the gate and the drain of the switch tube M17 are short-circuited.
[0030] The drain of the switch tube M4 is connected with the gate of the switch tube M19 and the drain of the switch tube M18 respectively.
[0031] The drain of the switch tube M5 is connected with the drain of the switch tube M19 and the gate of the switch tube M23 respectively.
[0032] The source of the switch tube M19, the source of the switch tube M21 and the source of the switch tube M22 are connected, and the source is further connected with the source of the switch tube M15.
[0033] The drain of the switch tube M6 is connected with the drain of the switch tube M20.
[0034] The gate and the drain of the switch tube M20 are short-circuited.
[0035] The drain of the switch tube M7 is connected with the drain of the switch tube M23.
[0036] The source of the switch tube M23 is connected with the drain of the switch tube M21.
[0037] According to the dead time adjusting circuit, the digital control output module comprises:
[0038] The switch tube M8, the switch tube M22, the NOT gate U1, the flip-flop U2, the NOR gate U3 and the NOT gate U4.
[0039] The source of the switch tube M8 is connected with the source of the switch tube M7 respectively, and the gate of the switch tube M8 is connected with the gate of the switch tube M7 respectively; the drain of the switch tube M8 is connected with the drain of the switch tube M22; the drain of the switch tube M8 is connected with the NOT gate U1, and the NOT gate U1 is connected with the excitation input end D of the flip-flop U2.
[0040] The source of the switch tube M22 is connected with the source of the switch tube M21, and the gate of the switch tube M22 is connected with the gate of the switch tube M21.
[0041] The NOR gate U3 is connected to the NOT gate U4; the NOT gate U4 is connected to the CLK pin of the flip-flop U2.
[0042] According to the dead-time adjustment circuit provided by this utility model, the variable current output module includes:
[0043] Switch M9, switch M10, switch M11 and switch M12;
[0044] In this configuration, the sources of each of the switching transistors M9, M10, M11, M12, and M8 are connected, and their gates are connected; the drain of the switching transistor M9 generates a current source ip1.
[0045] The drain of the switching transistor M10 generates current source ip2, the drain of the switching transistor M11 generates current source ip3, and the drain of the switching transistor M12 generates current source ip4.
[0046] According to the dead time adjustment circuit provided by this utility model, the dead time selection module includes:
[0047] NOT gate U5, NOT gate U6, switch M24, switch M25, comparator U7, capacitor C1, NOT gate U8, NOT gate U9, NOT gate U10, NOT gate U11, selector U12, NOT gate U13, NOT gate U14, NAND gate U15, NOT gate U16, selector U17;
[0048] Wherein, the output terminal of the NOT gate U5 is connected to the input terminal of the NOT gate U6, and the output terminal of the NOT gate U6 is connected to the gates of the switching transistors M24 and M25;
[0049] The source of the switching transistor M24 is connected to the negative terminal of the current source ip1, the drain of the switching transistor M24 is connected to the drain of the switching transistor M25, the source of the switching transistor M25 is grounded, and the drain of the switching transistor M25 is connected to the inverting input terminal of the comparator U7.
[0050] The positive terminal of capacitor C1 is connected to the inverting input terminal of comparator U7, the negative terminal of capacitor C1 is grounded, and the non-inverting input terminal of comparator U7 is connected to the first reference voltage vref1.
[0051] The output of the comparator U7 is connected in sequence to the NOT gate U8, the NOT gate U9, the NOT gate U10, and the NOT gate U11, wherein the NOT gate U11 is connected to the input of the selector U12;
[0052] The output end of the selector U12 is connected with the first input end of the NAND gate U15 through the non-gate U13 and the non-gate U14.
[0053] The output end of the NAND gate U15 is connected with the input end of the non-gate U16.
[0054] The output end of the selector U17 is connected with the input end of the non-gate U13.
[0055] According to the dead time adjusting circuit, the dead time selection module further comprises:
[0056] The non-gate U18, the switch tube M26, the switch tube M27, the comparator U19, the capacitor C2, the non-gate U20, the non-gate U21, the non-gate U22, the non-gate U23, the selector U24, the non-gate U25, the non-gate U26, the NAND gate U27, the non-gate U28 and the selector U29 are connected in sequence.
[0057] The output end of the non-gate U18 is connected with the gate of the switch tube M26 and the gate of the switch tube M27.
[0058] The source of the switch tube M26 is connected with the negative electrode of the current source ip2, the drain of the switch tube M26 is connected with the drain of the switch tube M27, the source of the switch tube M27 is grounded, and the drain of the switch tube M27 is connected with the inverting input end of the comparator U19.
[0059] The positive electrode of the capacitor C2 is connected with the inverting input end of the comparator U19, the negative electrode of the capacitor C2 is grounded, and the non-inverting input end of the comparator U19 is connected with the second reference voltage vref2.
[0060] The output end of the comparator U19 is connected with the input end of the selector U24 through the non-gate U20, the non-gate U21, the non-gate U22 and the non-gate U23 in sequence.
[0061] The output end of the selector U24 is connected with the second input end of the NAND gate U27 through the non-gate U25 and the non-gate U26 in sequence.
[0062] The first input end of the NAND gate U27 is connected with the second input end of the NAND gate U15, and the output end of the NAND gate U27 is connected with the input end of the non-gate U28.
[0063] The output end of the selector U29 is connected with the input end of the non-gate U25.
[0064] In addition, the utility model further provides an active clamp forward power supply chip, it includes the dead time adjusting circuit of any one in above.
[0065] The dead time adjusting circuit and the active clamp forward power supply chip have the advantages that the adjustability of the dead time is realized through the cooperative action of the current detection module, the digital control output module, the variable current output module and the dead time selection module, the dead time can be flexibly adjusted according to actual application requirements, the limitation of the traditional fixed dead time design is avoided, the power supply conversion efficiency is improved, the switching loss is reduced, the adaptability and stability of the circuit are enhanced, and the circuit design is suitable for various active clamp forward power supply frames and has good adaptability. BRIEF DESCRIPTION OF DRAWINGS
[0066] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.
[0067] Figure 1 is a structure schematic view of a dead time adjusting circuit provided by an embodiment of the present application;
[0068] Figure 2 is a structure schematic view of a current detection module, a digital control output module and a variable current output module provided by an embodiment of the present application;
[0069] Figure 3 is a structure schematic view of a dead time selection module provided by an embodiment of the present application;
[0070] Figure 4 is a schematic view of a PWM output driving signal and its dead time adjustment provided by an embodiment of the present application;
[0071] Figure 5 is a structure schematic view of an active clamp forward power supply chip provided by an embodiment of the present application. DETAILED DESCRIPTION
[0072] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the present application will be described clearly and completely in combination with the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the present application.
[0073] Figure 1 is a structure schematic view of a dead time adjusting circuit provided by an embodiment of the present application;Figure 2 is a structural schematic view of a current detection module, a digital control output module and a variable current output module provided by the embodiment of the utility model; Figure 3 is a structural schematic view of a dead time selection module provided by the embodiment of the utility model; Figure 4 is a schematic view of PWM output drive signal and its dead time adjustment provided by the embodiment of the utility model; Figure 5 is a structural schematic view of an active clamp forward power supply chip provided by the embodiment of the utility model.
[0074] Referring to Figures 1 to 5 , the dead time adjustment circuit 20 can include a current detection module 201, a digital control output module 202, a variable current output module 203 and a dead time selection module 204.
[0075] The current detection module 201 is used for detecting the current flowing through the pin OVLP through the resistance of the pin OVLP to ground, and outputting a digital control logic signal and a mirror current source;
[0076] The digital control output module 202 is connected with the current detection module 201, and is used for receiving the digital control logic signal, and converting it into a control selection signal to determine the selected dead time;
[0077] The variable current output module 203 is connected with the current detection module 201, and is used for outputting a variable current according to the mirror current source to provide the current required by the dead time selection module 204 for delay;
[0078] The dead time selection module 204 is connected with the digital control output module 202, and is used for selecting a dead time path according to the control selection signal, and realizing a delay function by using the current of the variable current output module 203, and outputting a dead time control signal.
[0079] In the embodiment, through the cooperative action of the current detection module 201, the digital control output module 202, the variable current output module 203 and the dead time selection module 204, the adjustability of the dead time is realized, the dead time can be flexibly adjusted according to the actual application requirement, the limitation of the traditional fixed dead time design is avoided, the power conversion efficiency is improved, the switching loss is reduced, the adaptability and stability of the circuit are enhanced, and the circuit design is suitable for various active clamp forward power supply architectures and has good adaptability.
[0080] In an embodiment of the present application, the current detection module includes a current sampling unit 2011, a signal conversion unit 2012 and a current mirror unit 2013.
[0081] The current sampling unit 2011 is used for detecting the current flowing through the pin OVLP through the resistance of the pin OVLP to ground;
[0082] The signal conversion unit 2012 is connected with the current sampling unit 2011, and is configured to convert the sampled current signal into a digital control logic signal.
[0083] The current mirror unit 2013 is connected with the signal conversion unit 2012, and is configured to generate a mirror current source according to the sampling current.
[0084] In the embodiment, by dividing the current detection module into the current sampling unit 2011, the signal conversion unit 2012 and the current mirror unit 2013, the function of each module is more clear, and the design, debugging and optimization are facilitated. The current sampling unit 2011 can accurately detect the current flowing through the pin OVLP, and provide accurate current information for subsequent signal processing. The modular design enables the current detection module to be adjusted and optimized according to different application scenarios, improving the adaptability of the circuit.
[0085] In an embodiment of the present specification, the current sampling unit 2011 comprises:
[0086] The switch tube M13, the switch tube M14, the switch tube M15 and the switch tube M16;
[0087] The source of the switch tube M13 and the source of the switch tube M14 are connected, the gate of the switch tube M13 is connected with the pin OVLP, and the drain of the switch tube M13 is connected with the drain of the switch tube M15;
[0088] The gate of the switch tube M14 is connected with the reference voltage vref, and the drain of the switch tube M14 is connected with the drain of the switch tube M16;
[0089] The source of the switch tube M15 and the source of the switch tube M16 are connected.
[0090] In the embodiment, by the specific connection mode of the switch tube M13, the switch tube M14, the switch tube M15 and the switch tube M16, the current flowing through the pin OVLP can be accurately detected, and a reliable input signal is provided for subsequent signal conversion. The reasonable connection mode of the switch tube simplifies the structure of the current sampling circuit, reduces the circuit complexity and cost. Through the reasonable configuration of the switch tube, the stability and reliability of the current sampling unit 2011 are enhanced, and the misoperation caused by external interference is reduced.
[0091] In an embodiment of the present specification, the current mirror unit 2013 comprises:
[0092] The switch tube M1, the switch tube M2, the switch tube M3, the switch tube M4, the switch tube M5, the switch tube M6 and the switch tube M7;
[0093] The source of each of the switch tubes M1, M2, M3, M4, M5, M6 and M7 is connected, and the gate of each is connected;
[0094] The gate and the drain of the switch tube M1 are connected, and are connected with the bias current source ibias;
[0095] The drain of the switch tube M2 is connected with the source of the switch tube M13 and the source of the switch tube M14;
[0096] The gate and the drain of the switch tube M7 are short-circuited.
[0097] In the embodiment, through the specific connection mode of the switch tubes M1 to M7, a stable mirror current source can be generated according to the sampling current. Such a mirror current source can provide an accurate current reference for subsequent circuit modules, ensuring the stability and accuracy of the circuit. Since the current of the current mirror unit 2013 is in a proportional relationship with the sampling current, when the resistance of the pin OVLP to ground changes and causes the sampling current to change, the current of the mirror current source will also change accordingly, thereby providing a variable delay current for the dead time selection module to meet the needs of different dead time adjustments. The design of the current mirror unit enables the circuit to flexibly adjust the current according to the change of the external resistance, thereby realizing the adjustable function of the dead time and improving the adaptability of the circuit in different application scenarios.
[0098] In an embodiment of the present specification, the signal conversion unit 2012 comprises:
[0099] The switch tubes M17, M18, M19, M20, M21 and M23;
[0100] The source of the switch tube M17 is connected with the drain of the switch tube M13 and the drain of the switch tube M15;
[0101] The source of the switch tube M18 is connected with the drain of the switch tube M14 and the drain of the switch tube M16;
[0102] The drain of the switch tube M17 is connected with the drain of the switch tube M3, and the gate of the switch tube M17 is short-circuited with the gate of the switch tube M18;
[0103] The drain of the switch tube M4 is connected with the gate of the switch tube M19 and the drain of the switch tube M18, respectively;
[0104] The drain of the switch tube M5 is connected with the drain of the switch tube M19 and the gate of the switch tube M23, respectively;
[0105] The sources of the switch tubes M19, M21 and M22 are connected, and are also connected with the source of the switch tube M15;
[0106] The drain of the switch tube M6 is connected with the drain of the switch tube M20;
[0107] The gate and the drain of the switch tube M20 are short-circuited;
[0108] The drain of the switch tube M7 is connected with the drain of the switch tube M23;
[0109] The source of the switch tube M23 is connected with the drain of the switch tube M21.
[0110] In the embodiment, the signal conversion unit 2012 converts the sampled current signal into a digital control logic signal, realizes the conversion from the analog domain to the digital domain, and facilitates the subsequent digital control and logic judgment.
[0111] In an embodiment of the present application, the current detection module 201 comprises:
[0112] The switch tube M1, the switch tube M2, the switch tube M3, the switch tube M4, the switch tube M5, the switch tube M6, the switch tube M7, the switch tube M13, the switch tube M14, the switch tube M15, the switch tube M16, the switch tube M17, the switch tube M18, the switch tube M19, the switch tube M20, the switch tube M21 and the switch tube M23;
[0113] The source of each of the switch tube M1, the switch tube M2, the switch tube M3, the switch tube M4, the switch tube M5, the switch tube M6 and the switch tube M7 is connected with the power supply end of the chip, and the gate of each is connected with the pin;
[0114] The gate and the drain of the switch tube M1 are connected, and connected with the bias current source ibias;
[0115] The drain of the switch tube M2 is connected with the source of the switch tube M13 and the switch tube M14;
[0116] The gate of the switch tube M13 is connected with the pin OVLP, the drain of the switch tube M13 is connected with the drain of the switch tube M15 and the source of the switch tube M17;
[0117] The gate of the switch tube M14 is connected with the reference voltage vref, and the drain of the switch tube M14 is connected with the drain of the switch tube M16 and the source of the switch tube M18 respectively;
[0118] The drain of the switch tube M3 is connected with the drain of the switch tube M17;
[0119] The gate and the drain of the switch tube M17 are short-circuited, and connected with the gate of the switch tube M18;
[0120] The drain of the switch tube M4 is connected with the gate of the switch tube M19 and the drain of the switch tube M18 respectively;
[0121] The drain of the switch tube M5 is connected with the drain of the switch tube M19 and the gate of the switch tube M23 respectively;
[0122] The sources of the switch tube M15, the switch tube M16, the switch tube M19, the switch tube M21 and the switch tube M22 are connected with the ground;
[0123] The drain of the switch tube M6 is connected with the drain of the switch tube M20;
[0124] The gate and the drain of the switch tube M20 are short-circuited and connected with the gate of the switch tube M21;
[0125] The drain of the switch tube M7 is connected with the drain of the switch tube M23, and the gate and the drain of the switch tube M7 are short-circuited;
[0126] The source of the switch tube M23 is connected with the drain of the switch tube M21.
[0127] In the embodiment, the current detection module 201 composed of multiple switch tubes can accurately detect the current flowing through the pin OVLP, and provide accurate current information for subsequent dead time adjustment. The detected current signal is converted into a digital control logic signal and a mirror current source, which provides a basis for digital control and variable current output, and realizes efficient conversion from analog signal to digital signal. The switch tube connection mode is reasonably and ingeniously designed, which simplifies the structure of the current detection circuit and reduces the circuit complexity and cost. The bias current source ibias can be provided by the internal circuit, and the specific value can be selected as needed, which is not limited here.
[0128] In an embodiment of the present application, the digital control output module 202 includes:
[0129] The switch tube M8, the switch tube M22, the NOT gate U1, the flip-flop U2, the NOR gate U3 and the NOT gate U4;
[0130] The source of the switch tube M8 is connected with the source of the switch tube M7, and the gate of the switch tube M8 is connected with the gate of the switch tube M7; the drain of the switch tube M8 is connected with the drain of the switch tube M22; the drain of the switch tube M8 is connected with the NOT gate U1, and the NOT gate U1 is connected with the excitation input end D of the flip-flop U2;
[0131] The source of the switch tube M22 is connected with the source of the switch tube M21, and the gate of the switch tube M22 is connected with the gate of the switch tube M21;
[0132] The NOR gate U3 is connected with the NOT gate U4; the NOT gate U4 is connected with the pin CLK of the flip-flop U2.
[0133] In this embodiment, the digital control output module 202 composed of switching tubes and logic gates converts the analog signal of the current detection module 201 into a digital control signal, realizing accurate control of the dead time selection. Moreover, different control selection signals can be output according to whether the pin OVLP is externally connected with a resistor, thereby determining the path selection of the dead time and enhancing the logical judgment ability of the circuit. Through the design of the digital logic circuit, the stability and reliability of the control signal are improved, and the misoperation caused by the interference of the analog signal is reduced.
[0134] In an embodiment of the present specification, the variable current output module 203 includes:
[0135] a switching tube M9, a switching tube M10, a switching tube M11 and a switching tube M12;
[0136] Among them, the source of the switching tube M9, the switching tube M10, the switching tube M11, the switching tube M12 and the switching tube M8 are connected respectively, and the gate is connected respectively; the drain of the switching tube M9 generates a current source ip1;
[0137] The drain of the switching tube M10 generates a current source ip2, the drain of the switching tube M11 generates a current source ip3, and the drain of the switching tube M12 generates a current source ip4.
[0138] In this embodiment, the variable current output module 203 composed of switching tubes can output variable current according to the mirror current source, provide the current required for the delay of the dead time selection module 204, realize the dynamic adjustment of the current. Different current values correspond to different delay times, and by adjusting the current size, the precise adjustment of the dead time can be realized, meeting the delay requirements in different application scenarios. The design of this unit provides a basis for subsequent function expansion, such as adding more current sources or adjusting the precision, further improving the flexibility and adaptability of the circuit.
[0139] For the convenience of understanding, the functions of some devices in the circuit are introduced as follows. The switch tube M1 can be used as a current source bias tube, which functions to provide an internal current reference source. The switch tubes M2, M3 and M4 can be used as tail current sources of a differential pair. The switch tubes M13 and M14 can be used as differential pair tubes of an amplifier. The switch tubes M15, M16, M17 and M18 can be used as load current mirrors of a differential pair. The switch tubes M5 and M19 are first-stage drivers, the switch tube M19 is a driver tube, and the switch tube M5 provides a current source. The switch tubes M23, M21 and M7 are second-stage drivers. The switch tubes M6 and M20 provide current bias for the switch tube M21, and the switch tube M7 provides different currents generated by different resistances connected to the pin OVLP. The switch tube M8 is an upper pull current tube, and the switch tube M22 is a lower pull current tube. When working, the output control signal is obtained by comparing the upper pull current with the lower pull current. The switch tubes M9, M10, M11 and M12 mirror the current generated by the resistance of the pin OVLP to output four current biases ip1, ip2, ip3 and ip4. The NOT gate U1, the flip-flop U2, the NOT gate U3 and the NOT gate U4 cooperate to function as a digital control output module 202. The upper pull current of the switch tube M8 and the lower pull current of the switch tube M22 are compared, y1 is the comparison output result, and D1 and D2 are two control signals of the system PWM. No matter D1 or D2, as long as there is a trigger, the current state can be outputted to determine the subsequent selection control. When the pin OVLP is left hanging and no resistance is connected, the lower pull current of the switch tube M22 is greater than the upper pull current of the switch tube M8, and the digital control output module 202 outputs a low potential. When the pin OVLP is externally connected with a resistance, the lower pull current of the switch tube M22 is smaller than the upper pull current of the switch tube M8, and the digital control output module 202 outputs a high potential.
[0140] The current detection module 201 is used to detect the current flowing through the pin OVLP through the resistance of the pin OVLP to ground, and outputs digital control logic and a mirror current source. The digital control output module 202 converts the analog signal of the current comparison into a digital signal, and outputs a control selection. The variable current output module 203 outputs the current of the mirror pin OVLP, which will change when the resistance connected to the pin OVLP changes. The pin OVLP can be externally connected with a resistance, and when the external resistance is connected, a pull-down current is needed. Since the switch tube M21 is biased internally to give a maximum value, when the resistance changes, the current needed is supplied by the switch tube M7. The supplied current is different when the resistance is different, so the bias current obtained is different. The digital control output module 202 detects whether there is a pull-down resistance of the pin OVLP, and outputs a control signal to the back-end circuit for selection control; the variable current output module 203 outputs four-way current source bias, which changes with the resistance connected to the pin OVLP. The Q output end of the flip-flop U2 outputs the control signal y2.
[0141] The above-mentioned switch tubes are MOS tubes, and the specific type of the MOS tube can be selected according to actual needs. For example, the switch tubes M1 to M14 are P-type MOS tubes, and the switch tubes M15 to M23 are N-type MOS tubes. The reference voltage vref is an internal reference voltage of the circuit, and the specific value can be selected according to actual conditions, which is not specifically limited here. The pin OVLP can be externally connected with a resistance, or can be suspended. When it is suspended, the output through the current detection module 201 determines that the output y1 is low, and the digital control output module 202 outputs the control signal y2 to the system circuit.
[0142] The specific principle is as follows: whether the pin OVLP is externally connected with a resistance, according to the different currents, selection is performed, and digital control logic is output. This control logic is whether to select to use a dead time. As described above, when the pin OVLP is suspended, the digital control output module 202 outputs a low level, which is output to the subsequent circuit selection path two. When the pin OVLP is externally connected with a resistance, the digital control output module 202 outputs a high level, which is output to the subsequent circuit selection path one. Whether to select the adjustable dead time control is selected. When the pin OVLP is externally connected with a resistance to ground, the output signal y1 is high, and y2 is output to the dead time selection module for control. At the same time, when the resistance value of the pin OVLP to ground is different, different currents can be realized, and variable current output can be realized. The DC1 / DC2 in the digital control output module 202 is a PWM control logic. The above-mentioned control logic is a double channel, and either DC1 or DC2 can realize control.
[0143] In an embodiment of the present specification, the dead time selection module 204 can include:
[0144] NAND gate U5, NAND gate U6, switch tube M24, switch tube M25, comparator U7, capacitor C1, NAND gate U8, NAND gate U9, NAND gate U10, NAND gate U11, selector U12, NAND gate U13, NAND gate U14, NAND gate U15, NAND gate U16, selector U17;
[0145] The input end of the NAND gate U5 inputs the DC1 signal or the DC2 signal, the output end of the NAND gate U5 is connected with the input end of the NAND gate U6, and the output end of the NAND gate U6 is connected with the gate of the switch tube M24 and the switch tube M25.
[0146] The source of the switch tube M24 is connected with the negative electrode of the current source ip1, the drain of the switch tube M24 is connected with the drain of the switch tube M25, the source of the switch tube M25 is grounded, and the drain of the switch tube M25 is connected with the inverting input end of the comparator U7.
[0147] The positive electrode of the capacitor C1 is connected with the inverting input end of the comparator U7, the negative electrode of the capacitor C1 is grounded, and the non-inverting input end of the comparator U7 is connected with the first reference voltage vref1.
[0148] The output end of the comparator U7 is connected with the input end of the selector U12 in sequence through the NAND gate U8, the NAND gate U9, the NAND gate U10, and the NAND gate U11.
[0149] The control end of the selector U12 inputs the y2 signal, and the output end of the selector U12 is connected with the first input end of the NAND gate U13, the NAND gate U14, and the NAND gate U15 in sequence, the second input end of the NAND gate U15 inputs the enable control signal.
[0150] The output end of the NAND gate U15 and the input end of the NAND gate U16 are connected, and the NAND gate U16 outputs the DC1_Ldelay signal or the DC2_Ldelay signal.
[0151] The input end of the selector U17 inputs the DC1 signal or the DC2 signal, the output end of the selector U17 is connected with the input end of the NAND gate U13, the control end of the selector U17 inputs the Y2_signal, and the Y2_signal is the y2 signal inverted by the NAND gate.
[0152] In the embodiment, the delay function is realized by detecting the change of the resistance of the pin OVLP to ground and charging the capacitor by the current source, so as to select different dead time paths, realize the rising edge and falling edge delay control of the PWM signal (such as DC1 or DC2), and output the dead time control signal (such as DC1_Ldelay and DC1_Hdelay) with delay, thereby dynamically adjusting the dead time. Through the selector and the digital control logic, the fixed dead time and the adjustable dead time can be switched, and the flexibility and applicability of the circuit are increased.
[0153] In the embodiment, the dead time selection module 204 can further include:
[0154] the non-gate U18, the switch tube M26, the switch tube M27, the comparator U19, the capacitor C2, the non-gate U20, the non-gate U21, the non-gate U22, the non-gate U23, the selector U24, the non-gate U25, the non-gate U26, the NAND gate U27, the non-gate U28, and the selector U29;
[0155] The input end of the non-gate U18 inputs the DC1 signal or the DC2 signal, and the output end of the non-gate U18 is connected with the gate of the switch tube M26 and the switch tube M27.
[0156] The source of the switch tube M26 is connected with the negative pole of the current source ip2, the drain of the switch tube M26 is connected with the drain of the switch tube M27, the source of the switch tube M27 is grounded, and the drain of the switch tube M27 is connected with the inverting input end of the comparator U19.
[0157] The positive pole of the capacitor C2 is connected with the inverting input end of the comparator U19, the negative pole of the capacitor C2 is grounded, and the non-inverting input end of the comparator U19 is connected with the second reference voltage vref2.
[0158] The output end of the comparator U19 is connected with the input end of the non-gate U20, the non-gate U21, the non-gate U22, the non-gate U23, and the selector U24 in sequence.
[0159] The control end of the selector U24 inputs the y2 signal, the output end of the selector U24 is connected with the second input end of the non-gate U25, the non-gate U26, and the NAND gate U27 in sequence, the second input end of the non-gate U27 inputs the enable control signal.
[0160] The first input end of the NAND gate U27 and the second input end of the non-gate U15 are connected with the enable control signal, the output end of the NAND gate U27 and the input end of the non-gate U28 are connected, and the non-gate U28 outputs the DC1_Hdelay signal or the DC2_Hdelay signal.
[0161] The input end of the selector U29 inputs the DC1 signal or the DC2 signal, the output end of the selector U29 is connected with the input end of the non-gate U25, the control end of the selector U29 inputs the Y2_signal, and the Y2_signal is the y2 signal inverted by the non-gate.
[0162] In this embodiment, another delay path (path two) is added to process the delay control of another PWM signal (such as DC2). Through the combination of comparators, capacitors and multiple NAND gates, the phase delay function of the PWM signal is realized, ensuring that the driving signals of the main switch tube and the clamping switch tube have precise dead time control. Through the selector of the enable control signal and digital logic, flexible switching and control of the delay signal are realized, so that the circuit can adapt to different system architecture requirements, improving the versatility and adjustment ability of the circuit. Overall, the above two embodiments can jointly dynamically adjust the dead time, so that the circuit can select fixed or adjustable dead time according to system requirements, thereby optimizing the control performance and conversion efficiency of the active clamping circuit.
[0163] The output selection control y2 signal first confirms whether path 1 or path 2 is selected. When path 1 is selected, different currents will charge the capacitor for different times, and finally different time delays are obtained.
[0164] DC1 / DC2 is the PWM output control signal, which is the control signal of the main channel control tube and the clamping tube of the active clamping circuit. Path one and path two represent two cases respectively. Path one performs different phase delays on the DC1 signal, and outputs different DC1_Ldelay and DC1_Hdelay signals. Path two directly outputs the DC1 signal to the driving end, that is, DC1_Ldelay and DC1_Hdelay are synchronized with the DC1 signal in path two. The y2 signal is Figure 2 The control signal output by the digital control output module 202, which outputs the selection of path one or path two; when path 2 is selected, it is used for circuit architecture systems that do not require dead time; when the active clamping circuit system is used, path one needs to be selected. In path one, the current source ip1 charges the capacitor C1 to obtain a level signal, which is compared with the first reference voltage vref1 to output the comparison result. Similarly, the current source ip2 charges the capacitor C2 to obtain a corresponding level signal, which is compared with the second reference voltage vref2 to output the comparison result. After digital signal delay, DC1_Ldelay and DC1_Hdelay signals are output. The DC1_Ldelay signal has a delay at the falling edge of the DC1 signal, and the DC1_Hdelay signal has a delay at the rising edge of the DC1 signal. For details, see Figure 4 t1 represents the delay of the rising edge, and t2 represents the delay of the falling edge. The enable control signal is the system enable end, which mainly sets the initial state of each digital logic and is high after starting, without affecting the system control logic.
[0165] Figure 4In the middle, DC1 and DC2 are PWM output control signals, DC1_Ldelay / DC2_Ldelay is the gate drive signal of the clamping switch tube, DC1_Hdelay / DC2_Hdelay is the gate drive signal of the main power switch tube, DC1 is the original PWM output control, when the pin OVLP increases the resistance, the rising edge and the falling edge of the DC1 signal can be realized, the DC1_Hdelay signal and the DC1_Ldelay signal are output, the two signals finally output the active clamping main power tube and the clamping tube, when the resistance value of the OVLP pin changes, the time of t1 and t2 will change, and finally the dead time adjustment is realized; when the dead time can be adjusted, the system architect can set according to the system, the system control can realize better adjustment, and the conversion efficiency can be obviously improved. The fixed selection mode of the utility model will save a resistance in the system.
[0166] Based on the same concept, the utility model also provides an active clamp forward power supply chip 30. Figure 5 It is the structure schematic view of the active clamp forward power supply chip provided by the utility model embodiment. The active clamp forward power supply chip 30 can include the dead time adjustment circuit 20 described in any one of the above.
[0167] The active clamp forward power supply chip 30 can usually include the following main parts:
[0168] Main power switch tube: for controlling the energy transmission from the input end to the output end;
[0169] Clamping switch tube: for releasing the energy in the transformer when the main power switch tube is closed, preventing the transformer magnetic core from being saturated;
[0170] PWM controller: for generating the drive signal of the main power switch tube and the clamping switch tube;
[0171] Drive circuit: amplifying the output signal of the PWM controller, driving the main power switch tube and the clamping switch tube;
[0172] Feedback circuit: for stabilizing the output voltage or current.
[0173] The integration of the dead time adjustment circuit 20 into the active clamp forward power supply chip can be as follows:
[0174] Integration position: embedding the dead time adjustment circuit between the PWM controller and the drive circuit.
[0175] Connection mode:
[0176] Input end: the input end of the dead time adjustment circuit is connected to the output of the PWM controller, and receives the original PWM signal (such as DC1 and DC2).
[0177] Output: The output of the adjustment circuit is connected to the input of the drive circuit, providing PWM signals (such as DC1_Ldelay and DC1_Hdelay) after delay processing.
[0178] Adjustment mode:
[0179] When the OVLP pin is externally connected with resistors of different resistance values, the dead time adjustment circuit dynamically adjusts the delay of the PWM signal according to the detected current change, thereby realizing the adjustable function of the dead time. Figure 3 Path 1 and path 2 correspond to the dotted arrow.
[0180] The device embodiments described above are only illustrative, wherein the units illustrated as separate components can or can not be physically separated, and the components illustrated as units can or can not be physical units, i.e., can be located in one place or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.
[0181] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and the necessary general hardware platform, and of course, it can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including a plurality of instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the method described in each embodiment or some part of the embodiment.
[0182] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A dead-time adjustment circuit, characterized by, The application relates to a dead time control circuit, which comprises the following parts: a current detection module for detecting the current flowing through the pin OVLP through the resistance between the pin OVLP and the ground and outputting a digital control logic signal and a mirror current source; a digital control output module connected with the current detection module for receiving the digital control logic signal and converting it into a control selection signal to determine the selected dead time; a variable current output module connected with the current detection module for outputting a variable current according to the mirror current source to provide the current required by the dead time selection module for time delay; a dead time selection module connected with the digital control output module for selecting a dead time path according to the control selection signal and realizing the time delay function by using the current of the variable current output module to output a dead time control signal.
2. The dead time adjustment circuit of claim 1, wherein, The current detection module comprises: a current sampling unit for detecting the current flowing through the pin OVLP through the resistance between the pin OVLP and the ground; a signal conversion unit connected with the current sampling unit for converting the sampled current signal into a digital control logic signal; a current mirror unit connected with the signal conversion unit for generating a mirror current source according to the sampling current.
3. The dead time adjustment circuit of claim 2, wherein, The current sampling unit comprises: switching tubes M13, M14, M15 and M16; wherein the source of the switching tube M13 is connected with the source of the switching tube M14, the gate of the switching tube M13 is connected with the pin OVLP, and the drain of the switching tube M13 is connected with the drain of the switching tube M15; the gate of the switching tube M14 is connected with a reference voltage vref, and the drain of the switching tube M14 is connected with the drain of the switching tube M16; the sources of the switching tubes M15 and M16 are connected.
4. The dead time adjustment circuit of claim 3, wherein, The current mirror unit comprises: switching tubes M1, M2, M3, M4, M5, M6 and M7; wherein the sources of the switching tubes M1, M2, M3, M4, M5, M6 and M7 are connected, and the gates are connected; the gate and the drain of the switching tube M1 are connected, and are connected with a bias current source ibias; the drain of the switching tube M2 is connected with the source of the switching tube M13 and the source of the switching tube M14; the gate and the drain of the switching tube M7 are short-circuited.
5. The dead time adjustment circuit of claim 4, wherein, The signal conversion unit comprises: switching tubes M17, M18, M19, M20, M21 and M23; wherein the source of the switching tube M17 is connected with the drain of the switching tube M13 and the drain of the switching tube M15; the source of the switching tube M18 is connected with the drain of the switching tube M14 and the drain of the switching tube M16; the drain of the switching tube M17 is connected with the drain of the switching tube M3, and the gate and the drain of the switching tube M17 are connected with the gate of the switching tube M18 after being short-circuited. The drain of the switch tube M4 is connected with the gate of the switch tube M19 and the drain of the switch tube M18 respectively; The drain of the switch tube M5 is connected with the drain of the switch tube M19 and the gate of the switch tube M23 respectively; The source of the switch tube M19, the switch tube M21 and the switch tube M22 are connected, and also connected with the source of the switch tube M15; The drain of the switch tube M6 is connected with the drain of the switch tube M20; The gate and the drain of the switch tube M20 are short-circuited; The drain of the switch tube M7 is connected with the drain of the switch tube M23; The source of the switch tube M23 is connected with the drain of the switch tube M21.
6. The dead time adjustment circuit of claim 5, wherein, The digital control output module comprises: The switch tube M8, the switch tube M22, the NOT gate U1, the flip-flop U2, the NOR gate U3 and the NOT gate U4; Wherein, the source and the gate of the switch tube M8 are connected with the source and the gate of the switch tube M7 respectively; the drain of the switch tube M8 is connected with the drain of the switch tube M22; the drain of the switch tube M8 is connected with the NOT gate U1, and the NOT gate U1 is connected with the excitation input end D of the flip-flop U2; The source of the switch tube M22 is connected with the source of the switch tube M21, and the gate of the switch tube M22 is connected with the gate of the switch tube M21; The NOR gate U3 is connected with the NOT gate U4, and the NOT gate U4 is connected with the pin CLK of the flip-flop U2.
7. The dead time adjustment circuit of claim 6, wherein, The variable current output module comprises: The switch tube M9, the switch tube M10, the switch tube M11 and the switch tube M12; Wherein, the source and the gate of the switch tube M9, the switch tube M10, the switch tube M11, the switch tube M12 and the switch tube M8 are connected respectively; the drain of the switch tube M9 generates the current source ip1; The drain of the switch tube M10 generates the current source ip2, the drain of the switch tube M11 generates the current source ip3, and the drain of the switch tube M12 generates the current source ip4.
8. The dead time adjustment circuit of claim 7, wherein, The dead time selection module comprises: The NOT gate U5, the NOT gate U6, the switch tube M24, the switch tube M25, the comparator U7, the capacitor C1, the NOT gate U8, the NOT gate U9, the NOT gate U10, the NOT gate U11, the selector U12, the NOT gate U13, the NOT gate U14, the NAND gate U15, the NOT gate U16, the selector U17; Wherein, the output end of the NOT gate U5 is connected with the input end of the NOT gate U6, and the output end of the NOT gate U6 is connected with the gate of the switch tube M24 and the gate of the switch tube M25; The source of the switch tube M24 is connected with the negative electrode of the current source ip1, the drain of the switch tube M24 is connected with the drain of the switch tube M25, the source of the switch tube M25 is grounded, and the drain of the switch tube M25 is connected with the inverting input end of the comparator U7; The positive electrode of the capacitor C1 is connected with the inverting input end of the comparator U7, the negative electrode of the capacitor C1 is grounded, and the non-inverting input end of the comparator U7 is connected with the first reference voltage vref1; The output of the comparator U7 is connected to the non-gate U8, the non-gate U9, the non-gate U10, the non-gate U11 in turn, wherein the non-gate U11 is connected to the input of the selector U12; The output of the selector U12 is connected to the first input of the non-gate U13, the non-gate U14 in turn, and the non-gate U15; The output of the non-gate U15 is connected to the input of the non-gate U16; The output of the selector U17 is connected to the input of the non-gate U13.
9. The dead-time adjustment circuit of claim 8, wherein, The dead time selection module further comprises: The non-gate U18, the switch tube M26, the switch tube M27, the comparator U19, the capacitor C2, the non-gate U20, the non-gate U21, the non-gate U22, the non-gate U23, the selector U24, the non-gate U25, the non-gate U26, the non-gate U27, the non-gate U28, the selector U29; The output of the non-gate U18 is connected to the gate of the switch tube M26 and the switch tube M27; The source of the switch tube M26 is connected to the negative electrode of the current source ip2, the drain of the switch tube M26 is connected to the drain of the switch tube M27, the source of the switch tube M27 is grounded, and the drain of the switch tube M27 is connected to the inverting input of the comparator U19; The positive electrode of the capacitor C2 is connected to the inverting input of the comparator U19, the negative electrode of the capacitor C2 is grounded, and the non-inverting input of the comparator U19 is connected to the second reference voltage vref2; The output of the comparator U19 is connected to the non-gate U20, the non-gate U21, the non-gate U22, the non-gate U23 in turn, and the input of the selector U24; The output of the selector U24 is connected to the second input of the non-gate U27 through the non-gate U25, the non-gate U26 in turn; The first input of the non-gate U27 is connected to the second input of the non-gate U15, and the output of the non-gate U27 is connected to the input of the non-gate U28; The output of the selector U29 is connected to the input of the non-gate U25.
10. An active clamp forward power supply chip, characterized in that, The dead time selection module further comprises: The dead time selection module further comprises: