Active clamp circuit

Abstract

The purpose of the present invention is to provide an active clamp circuit of a power amplifier including a bias circuit. A first diode circuit includes a plurality of diodes connected in multiple stages, and an anode-side end thereof is connected to an output node of the power amplifier. A base or a gate of a clamp transistor is connected to a cathode-side end of the first diode circuit, and a collector or a drain is connected to a bias circuit, such that a bias current of the power amplifier is suppressed. A control circuit generates a reference voltage having a variable voltage value. A voltage regulator is connected to an emitter or a source of the clamp transistor and maintains the voltage of the emitter or the source of the clamp transistor at a voltage based on the reference voltage.

Description

Active clamp circuit

[0001] The present invention relates to an active clamp circuit.

[0002] When the output voltage of a power amplifier exceeds a certain level, an active clamp circuit that protects the power amplifier by suppressing the bias current of the power amplifier is known (see Patent Document 1). In the active clamp circuit described in Patent Document 1, the on / off of a clamp transistor is controlled by a current branched from the middle of a first diode circuit connected between the output node of the power amplifier and the reference potential. By controlling the on / off of the clamp transistor, the current flowing through the bias circuit is suppressed.

[0003] U.S. Patent No. 6,580,321

[0004] There may be a case where it is desired to change the output voltage level at which the suppression of the bias current starts due to various factors such as the ambient temperature, variations in the manufacturing process, and the operating mode of the power amplifier. In a conventional active clamp circuit, the output voltage level at which the bias current is suppressed cannot be changed. An object of the present invention is to provide an active clamp circuit capable of changing the output voltage level at which the suppression of the bias current starts.

[0005] According to one aspect of the present invention, there is provided an active clamp circuit for a power amplifier including a bias circuit, the active clamp circuit including: a first diode circuit including a plurality of diodes connected in multiple stages, with the anode-side end connected to the output node of the power amplifier; a clamp transistor having a base or gate connected to the cathode-side end of the first diode circuit and a collector or drain connected to the bias circuit, configured to suppress the bias current of the power amplifier; a control circuit for generating a reference voltage with a variable voltage value; and a voltage regulator connected to the emitter or source of the clamp transistor, configured to maintain the voltage of the emitter or source of the clamp transistor at a voltage based on the reference voltage.

[0006] When the reference voltage changes, the base or gate voltage at which the clamp transistor turns on also changes, and the voltage at the cathode end of the first diode circuit also changes. As a result, the voltage level at the output node of the power amplifier at which the clamp transistor turns on also changes. In this way, the output voltage level at which bias current suppression begins can be changed.

[0007] Figure 1 is an equivalent circuit diagram of the active clamp circuit and the power amplifier 10 to be protected according to the first embodiment. Figure 2 is an equivalent circuit diagram of the temperature characteristic correction circuit 52. Figure 3 is a graph showing the temperature characteristics of the output currents Iptat, Iztat, Isum, and control current Iout. Figure 4 is a graph showing an example of the voltage waveform of the high-frequency output signal RFout, and an on / off timing chart of the clamp transistor 30. Figure 5 is an equivalent circuit diagram of the active clamp circuit and the power amplifier 10 to be protected according to the second embodiment. Figure 6 is an equivalent circuit diagram of the active clamp circuit and the power amplifier 10 to be protected according to the third embodiment. Figure 7 is an equivalent circuit diagram of the active clamp circuit and the power amplifier 10 to be protected according to the fourth embodiment. Figure 8 is an equivalent circuit diagram of the active clamp circuit and the power amplifier 10 to be protected according to the fifth embodiment.

[0008] [First Embodiment] An active clamp circuit according to the first embodiment will be described with reference to the drawings from Figures 1 to 4.

[0009] Figure 1 is an equivalent circuit diagram of the active clamp circuit and the power amplifier 10 to be protected according to the first embodiment. The power amplifier 10 includes an amplifying transistor 11 and a bias circuit 12. For example, a heterojunction bipolar transistor (HBT) is used as the amplifying transistor 11. A high-frequency input signal RFin is input to the base of the amplifying transistor 11 via an impedance matching circuit 18. A power supply voltage Vcc is applied to the collector of the amplifying transistor 11 via a choke coil 14. The emitter of the amplifying transistor 11 is connected to a reference potential (ground potential).

[0010] The bias circuit 12 includes an emitter follower transistor 12A, a diode circuit 12B, and a resistor element 12C. The battery power supply voltage Vbat is applied to the collector of the emitter follower transistor 12A, and its emitter is connected to the base of the amplifier transistor 11 via the resistor element 13. A bias control current IB is input from the control circuit 50 to the base of the emitter follower transistor 12A via the resistor element 12C. A base bias current corresponding to the bias control current IB is supplied from the emitter follower transistor 12A to the amplifier transistor 11.

[0011] The base of the emitter follower transistor 12A is connected to a reference potential via a diode circuit 12B. The diode circuit 12B consists of multiple diodes connected in multiple stages, and is connected so that a forward current flows from the base of the emitter follower transistor 12A toward the reference potential. The diode circuit 12B limits the upper limit of the voltage applied to the base of the emitter follower transistor 12A.

[0012] A high-frequency output signal RFout is output from the output node Nout of the power amplifier 10, i.e., from the collector of the amplification transistor 11. The anode end of the first diode circuit 20, which includes multiple diodes connected in multiple stages, is connected to the output node Nout of the power amplifier 10. The cathode end of the first diode circuit 20 is connected to a reference potential via the second diode circuit 21. The second diode circuit 21 includes one or multiple diodes connected in multiple stages, and is connected such that a forward current flows from the cathode end of the first diode circuit 20 toward the reference potential.

[0013] The cathode end of the first diode circuit 20 is connected to the base of the clamp transistor 30 via a resistor 22. For example, an HBT is used as the clamp transistor 30. The collector of the clamp transistor 30 is connected to the bias circuit 12. More specifically, the collector of the clamp transistor 30 is connected to the base of the emitter follower transistor 12A via a resistor 12C. When the clamp transistor 30 is turned on, at least a portion of the bias control current IB output from the control circuit 50 is drawn out to the clamp transistor 30, and the remaining current is input to the bias circuit 12.

[0014] The emitter of the clamp transistor 30 is connected to the voltage regulator 40. The voltage regulator 40 maintains the voltage at the emitter of the clamp transistor 30 at a voltage Vreg based on a variable reference voltage Vref supplied by the control circuit 50. Next, the configuration of the voltage regulator 40 will be described.

[0015] The voltage regulator 40 includes a driver transistor 41, an operational amplifier 42, a resistor voltage divider circuit 43, and a capacitor 44. For example, an NMOSFET is used as the driver transistor 41. The drain of the driver transistor 41 is connected to the emitter of the clamp transistor 30, and its source is connected to a reference potential. The capacitor 44 is connected in parallel with the driver transistor 41. The capacitor 44 has the function of bypassing high-frequency signals.

[0016] The drain power supply voltage Vdd is applied to the drain of the driver transistor 41 via the resistor voltage divider circuit 43. The voltage difference between the drain power supply voltage Vdd and the voltage Vreg is divided by the resistor voltage divider circuit 43 and input as a feedback voltage Vfb to the non-inverting input node of the operational amplifier 42. The reference voltage Vref generated by the control circuit 50 is input to the inverting input node of the operational amplifier 42. The output voltage of the operational amplifier 42 is input to the gate of the driver transistor 41.

[0017] The resistance value of the resistor element on the drain power supply voltage Vdd side of the resistor voltage divider circuit 43 is denoted as R1, and the resistance value of the resistor element on the drain side of the driver transistor 41 is denoted as R2. In this case, the voltage Vreg is expressed by the following formula: Vreg = ((R1 + R2) / R1)Vref - (R2 / R1)Vdd ... (1) When the reference voltage Vref is changed, the voltage Vreg at the emitter of the clamp transistor 30 also changes.

[0018] Next, the configuration of the control circuit 50 will be described. The control circuit 50 includes a reference voltage generation circuit 51, a temperature characteristic correction circuit 52, a digital circuit 53, and a bias control current generation circuit 54. The temperature characteristic correction circuit 52 outputs a control current Iout based on the ambient temperature.

[0019] For example, the power amplifier 10, the first diode circuit 20, the second diode circuit 21, and the clamp transistor 30 are formed on a substrate made of compound semiconductor, while the control circuit 50 and the voltage regulator 40 are formed on a silicon substrate. "Ambient temperature" refers to the temperature of the silicon substrate on which the temperature characteristic correction circuit 52 is formed. Since the substrate on which the power amplifier 10 etc. is formed and the substrate on which the control circuit 50 etc. is formed are mounted on a common module substrate and are thermally coupled, the temperatures of the power amplifier 10 and the first diode circuit 20 etc. are also reflected in the ambient temperature.

[0020] The temperature characteristic correction circuit 52 changes the relationship between temperature and control current Iout in response to command Com1 from the digital circuit 53. The reference voltage generation circuit 51 generates a reference voltage Vref based on the control current Iout from the temperature characteristic correction circuit 52 and command Com2 from the digital circuit 53. That is, the reference voltage Vref changes according to the ambient temperature and command Com2 from the digital circuit 53.

[0021] Furthermore, the digital circuit 53 supplies a predetermined bias control current IB to the bias circuit 12 by controlling the bias control current generation circuit 54.

[0022] Next, the temperature characteristic correction circuit 52 will be described with reference to Figure 2. Figure 2 is an equivalent circuit diagram of the temperature characteristic correction circuit 52.

[0023] The temperature characteristic correction circuit 52 includes PMOS current mirror circuits 52B, 52E, 52G, and an NMOS current mirror circuit 52A. The drain of the PMOS transistor on the reference current side of the PMOS current mirror circuit 52B is connected to a reference potential via a series circuit of a variable resistor element 52C and a diode 52D. The anode of the diode 52D is connected to the variable resistor element 52C, and its cathode is connected to the reference potential.

[0024] The difference voltage between the drain voltage of the PMOS transistor through which the reference current flows and the silicon bandgap voltage VBG is applied to the gates of the two PMOS transistors in the PMOS current mirror circuit 52B. The forward voltage of the diode 52D is temperature-dependent. Therefore, the current level of the output current Iptat of the PMOS current mirror circuit 52B also changes with temperature.

[0025] The drain of the PMOS transistor on the reference current side of the PMOS current mirror circuit 52E is connected to a reference potential via a variable resistor element 52F. The difference voltage between the drain voltage of the PMOS transistor through which the reference current flows and the silicon bandgap voltage VBG is applied to the gates of the two PMOS transistors of the PMOS current mirror circuit 52E. The output current Iztat of the PMOS current mirror circuit 52E is independent of temperature and depends on the resistance value of the variable resistor element 52F.

[0026] The resistance values ​​of the variable resistor elements 52C and 52F are changed by the command Com1 from the digital circuit 53.

[0027] The sum of the output currents Iptat and Iztat becomes the reference current of the NMOS current mirror circuit 52A. Therefore, the output current Isum of the NMOS current mirror circuit 52A is equal to the sum of the output currents Iptat and Iztat. The output current Isum of the NMOS current mirror circuit 52A becomes the reference current of the PMOS current mirror circuit 52G. The output current (control current Iout) of the PMOS current mirror circuit 52G is equal to the sum of the output currents Iptat and Iztat. The control current Iout is input to the reference voltage generation circuit 51. The reference voltage generation circuit 51 generates a reference voltage Vref (Figure 1) based on the control current Iout.

[0028] Figure 3 is a graph showing the temperature characteristics of the output currents Iptat, Iztat, Isum, and control current Iout. The horizontal axis represents temperature, and the vertical axis represents current level. The output current Iztat is constant and independent of temperature. The output current Iptat increases with increasing temperature.

[0029] The output current Isum and the control current Iout are equal to the sum of the output current Iptat and the output current Iztat. Therefore, the control current Iout increases with increasing temperature.

[0030] When the digital circuit 53 changes the resistance value of the variable resistor element 52F (Figure 2), the current level of the output current Iztat changes. When the digital circuit 53 changes the resistance value of the variable resistor element 52C (Figure 2), the slope of the output current Iptat with respect to temperature changes. Therefore, when the digital circuit 53 changes the resistance values ​​of the variable resistor elements 52C and 52F, the current level and temperature dependence of the control current Iout change.

[0031] Next, the operation of the active clamp circuit according to the first embodiment will be described with reference to Figure 4. Figure 4 is a graph showing an example of the voltage waveform of the high-frequency output signal RFout, and an on / off timing chart of the clamp transistor 30. As shown in Figure 1, the voltage at the cathode end of the first diode circuit 20 is denoted as Vdk, the on voltage between the base and emitter of the clamp transistor 30 is denoted as Vth_on, the voltage corresponding to the voltage drop across the resistor element 22 is denoted as Vdrop, and the rising voltage of the forward current of the first diode circuit 20 is denoted as Vth_d. The voltage at the output node Nout when current begins to flow through the first diode circuit 20 is called the clipping voltage Vclp.

[0032] The voltage Vdk when the clamp transistor 30 turns on is expressed by the following equation: Vdk = Vreg + Vth_on + Vdrop ... (2) The clipping voltage Vclp is expressed by the following equation: Vclp = Vdk + Vth_d ... (3)

[0033] As shown in Figure 4, when the voltage level of the high-frequency output signal RFout exceeds the clipping voltage Vclp, base current flows from the output node Nout of the power amplifier 10 through the first diode circuit 20 and the resistor element 22 to the clamp transistor 30. As a result, the clamp transistor 30 turns on, and at least a portion of the bias control current IB output from the control circuit 50 is branched and flows through the clamp transistor 30. Consequently, the bias control current supplied to the bias circuit 12 (Figure 1) decreases.

[0034] When the bias control current decreases, the base bias current supplied to the amplification transistor 11 also decreases. In this way, the clamp transistor 30 is configured to suppress the bias current of the power amplifier 10 when turned on. By suppressing the bias current, the gain of the amplification transistor 11 decreases. The power amplifier 10 is protected by suppressing the voltage level of the high-frequency output signal RFout due to the decrease in gain.

[0035] Next, the excellent effects of the first embodiment will be described. In the first embodiment, the control circuit 50 can change the clipping voltage Vclp by adjusting the reference voltage Vref (Figure 1).

[0036] In a power amplifier 10 using a heterojunction bipolar transistor, the clipping voltage Vclp is required to be high at high temperatures and low at low temperatures in order to protect the power amplifier. However, the forward rise voltage of the first diode circuit 20 is low at high temperatures and high at low temperatures due to the characteristics of the diode. In other words, it is the opposite of the temperature characteristics required for the clipping voltage Vclp.

[0037] In the first embodiment, as explained with reference to Figure 3, the control current Iout increases with increasing temperature. The reference voltage generation circuit 51 increases the reference voltage Vref when the control current Iout increases. When the reference voltage Vref increases, the voltage Vreg also increases from equation (1). When the voltage Vreg increases, the clipping voltage Vclp also increases from equations (2) and (3). In this way, the active clamp circuit according to the first embodiment can impart a desirable temperature characteristic to the clipping voltage Vclp. Furthermore, the digital circuit 53 gives a command Com1 (Figure 1) to the temperature characteristic correction circuit 52, which changes the resistance values ​​of the variable resistor elements 52C and 52F, thereby fine-tuning the temperature characteristic of the clipping voltage Vclp.

[0038] Furthermore, the digital circuit 53 can also adjust the reference voltage Vref by giving a command Com2 to the reference voltage generation circuit 51. For example, due to variations in the manufacturing process, the preferred clipping voltage Vclp of the power amplifier 10 may differ from lot to lot. By giving a command Com2 to the reference voltage generation circuit 51, the appropriate clipping voltage Vclp can be set for each lot. For example, an electronic fuse can be provided in the digital circuit 53, and the command Com2 can be sent by setting the conduction state of the electronic fuse.

[0039] Furthermore, the appropriate clipping voltage Vclp may differ depending on the operating mode of the power amplifier 10, for example, between normal mode and low-power mode. Alternatively, the appropriate clipping voltage Vclp may differ depending on the operating frequency band of the power amplifier 10. The digital circuit 53 can set the clipping voltage Vclp to an appropriate value by giving a command Com2 to the reference voltage generation circuit 51 according to the operating mode and operating frequency band.

[0040] When the voltage level of the high-frequency output signal RFout increases, the base current of the clamp transistor 30 may exceed the upper limit of the allowable range. As the base current of the clamp transistor 30 approaches the upper limit of the allowable range, the voltage drop across the resistive element 22 (voltage Vdrop) increases, and the voltage Vdk at the cathode end of the first diode circuit 20 rises. When the voltage Vdk exceeds the forward rise voltage of the second diode circuit 21, a forward current flows through the second diode circuit 21. In this way, the clamp transistor 30 can be protected by branching a portion of the current flowing through the first diode circuit 20 to the second diode circuit 21.

[0041] Next, a modified version of the first embodiment will be described. In the first embodiment, a resistor voltage divider circuit 43 is inserted between the drain of the driver transistor 41 of the voltage regulator 40 and the drain power supply voltage Vdd, but the resistor element on the drain side of the driver transistor 41 may be omitted. That is, the resistance value R2 of the resistor element on the drain side of the driver transistor 41 may be set to zero. In this case, as can be seen from equation (1), the voltage Vreg becomes equal to the reference voltage Vref.

[0042] In the first embodiment, a temperature characteristic correction circuit 52 is provided in the control circuit 50 (Figure 1), but the temperature characteristic correction circuit 52 may be omitted. In this case, the reference voltage Vref is adjusted based only on the command Com2 from the digital circuit 53. Conversely, the function of the digital circuit 53 providing the command Com2 to the reference voltage generation circuit 51 may be omitted, and the reference voltage Vref may be adjusted solely by the temperature characteristic correction circuit 52.

[0043] [Second Embodiment] Next, an active clamp circuit according to the second embodiment will be described with reference to FIG. 5. Hereinafter, descriptions of configurations common to the active clamp circuit according to the first embodiment described with reference to FIGS. 1 to 4 will be omitted.

[0044] FIG. 5 is an equivalent circuit diagram of an active clamp circuit according to the second embodiment and a power amplifier 10 to be protected. In the active clamp circuit according to the first embodiment, a second diode circuit 21 (FIG. 1) is connected between the cathode-side end of the first diode circuit 20 and the reference potential, but in the second embodiment, the second diode circuit 21 is not connected. Also, in the first embodiment, the cathode-side end of the first diode circuit 20 is connected to the base of the clamp transistor 30 via a resistor element 22 (FIG. 1), but in the second embodiment, the cathode-side end of the first diode circuit 20 is directly connected to the base of the clamp transistor 30.

[0045] Instead of omitting the second diode circuit 21 (FIG. 1), an overcurrent bypass circuit 25 is connected between the anode-side end of the first diode circuit 20 and the reference potential. The overcurrent bypass circuit 25 is composed of a plurality of diodes connected in multiple stages and is connected in a direction in which a reverse current flows from the end connected to the anode of the first diode circuit 20 toward the reference potential.

[0046] Next, the excellent effects of the second embodiment will be described. Also in the second embodiment, similarly to the first embodiment, the control circuit 50 can change the clip voltage Vclp by adjusting the reference voltage Vref. Further, in the second embodiment, when the voltage level of the high-frequency output signal RFout becomes high and the base current of the clamp transistor 30 approaches the upper limit value of the allowable range, the current output from the output node Nout of the power amplifier 10 branches and flows through the first diode circuit 20 and the overcurrent bypass circuit 25. Therefore, the base current of the clamp transistor 30 can be maintained below the upper limit value of the allowable range.

[0047] [Third Embodiment] Next, an active clamp circuit according to the third embodiment will be described with reference to FIG. 6. Hereinafter, descriptions of the configurations common to the active clamp circuit according to the first embodiment described with reference to FIGS. 1 to 4 will be omitted.

[0048] FIG. 6 is an equivalent circuit diagram of an active clamp circuit according to the third embodiment and a power amplifier 10 to be protected. In the active clamp circuit (FIG. 1) according to the first embodiment, the voltage division ratio of the resistor voltage division circuit 43 of the voltage regulator 40 is a fixed value. In contrast, in the third embodiment, the voltage division ratio of the resistor voltage division circuit 43 is variable. By changing the resistance value of one resistor element of the resistor voltage division circuit 43, the voltage division ratio can be changed. The resistor element with variable resistance value is realized, for example, by connecting a plurality of unit circuits in which a unit resistor element and a switch element are connected in series in parallel. By controlling the on / off of the switch element, the resistance value of the resistor element can be changed.

[0049] According to a command from the digital circuit 53, the voltage division ratio adjustment circuit 55 changes the voltage division ratio of the resistor voltage division circuit 43. As can be seen from Equation (1), when the voltage division ratio of the resistor voltage division circuit 43 changes, the relationship between the voltage Vreg generated by the voltage regulator 40 and the reference voltage Vref changes.

[0050] Next, the excellent effects of the third embodiment will be described. Also in the third embodiment, similar to the first embodiment, the clip voltage Vclp can be changed by adjusting the reference voltage Vref according to the temperature change. Furthermore, in the third embodiment, even if the reference voltage Vref at a specific temperature, for example, room temperature, is a fixed value, the clip voltage Vclp can be adjusted by changing the voltage division ratio of the resistor voltage division circuit 43.

[0051] For example, due to variations in the manufacturing process, the appropriate clip voltage Vclp may vary between lots. In such a case, by changing the voltage division ratio of the resistor voltage division circuit 43, the clip voltage Vclp can be set to an appropriate value. For example, it is advisable to command the voltage division ratio to the voltage division ratio adjustment circuit 55 by setting the conduction state of the electronic fuse provided in the digital circuit 53.

[0052] The power amplifier 10 has the function of operating in two operating modes, normal mode and low power mode, and the appropriate clipping voltage Vclp may differ depending on the operating mode. Also, the power amplifier 10 can operate in multiple frequency bands, and the appropriate clipping voltage Vclp may differ depending on the operating frequency band. In such cases, the control circuit 50 can change the voltage division ratio of the resistive voltage divider circuit 43 according to the operating mode and operating frequency band of the power amplifier 10, and set the clipping voltage Vclp to an appropriate value.

[0053] [Fourth Embodiment] Next, an active clamp circuit according to the fourth embodiment will be described with reference to Figure 7. The following description will omit the explanation of components common to the active clamp circuit according to the first embodiment, which was described with reference to Figures 1 to 4.

[0054] Figure 7 is an equivalent circuit diagram of the active clamp circuit according to the fourth embodiment and the power amplifier 10 to be protected. In the active clamp circuit according to the first embodiment (Figure 1), an HBT is used for the clamp transistor 30, but in the fourth embodiment, an NMOSFET is used. The gate of the clamp transistor 30 is connected to the cathode end of the first diode circuit 20 via a resistor 22. The drain of the clamp transistor 30 is connected to the bias circuit 12, and the source is connected to the voltage regulator 40. Although the fourth embodiment shows an example with the resistor 22 inserted, the resistor 22 may be omitted and both ends of the resistor 22 may be short-circuited.

[0055] In the first embodiment, the on / off state of the clamp transistor 30 is controlled by the base current, but in the fourth embodiment, the on / off state of the clamp transistor 30 is controlled by the gate voltage. Almost no current flows through the gate of the clamp transistor 30. Therefore, the current flowing into the first diode circuit 20 flows through the second diode circuit 21 to the reference potential. Although the above effect can be obtained even without inserting the resistive element 22, inserting the resistive element 22 provides the effect of electrostatic discharge (ESD) protection.

[0056] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, as in the first embodiment, the clipping voltage Vclp can be changed by adjusting the reference voltage Vref in accordance with the temperature change. In the first embodiment (Figure 1), the clamp transistor 30, which uses an HBT, is formed on the same compound semiconductor substrate as the power amplifier 10. In contrast, in the fourth embodiment, an NMOSFET is used for the clamp transistor 30, so the clamp transistor 30 is formed on the same silicon substrate as the voltage regulator 40 and the control circuit 50. As a result, the excellent effect of reducing manufacturing costs is obtained.

[0057] [Fifth Embodiment] Next, an active clamp circuit according to the fifth embodiment will be described with reference to Figure 8. The following description will omit the explanation of components common to the active clamp circuit according to the first embodiment, which was described with reference to Figures 1 to 4.

[0058] Figure 8 is an equivalent circuit diagram of the active clamp circuit and the power amplifier 10 to be protected according to the fifth embodiment. The power amplifier 10 protected by the active clamp circuit according to the first embodiment (Figure 1) has a single-stage configuration. In contrast, the power amplifier 10 protected by the active clamp circuit according to the fifth embodiment has a two-stage configuration and includes a first-stage amplification circuit 10A and a final-stage amplification circuit 10B. The basic configurations of the first-stage amplification circuit 10A and the final-stage amplification circuit 10B are the same as the basic configuration of the power amplifier 10 protected by the active clamp circuit according to the first embodiment. The first-stage amplification circuit 10A and the final-stage amplification circuit 10B each include a bias circuit 12. Note that the input signal and output signal power, gain, and other characteristics differ between the first-stage amplification circuit 10A and the final-stage amplification circuit 10B.

[0059] A high-frequency input signal RFin is input to the first-stage amplifier circuit 10A, and the high-frequency signal amplified by the first-stage amplifier circuit 10A is input to the final-stage amplifier circuit 10B. The first diode circuit 20 is connected to the output node Nout of the final-stage amplifier circuit 10B. The clamp transistor 30 is connected to the bias circuit 12 of the first-stage amplifier circuit 10A.

[0060] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, as in the first embodiment, the clipping voltage Vclp can be changed by adjusting the reference voltage Vref in accordance with the temperature change. In the fifth embodiment, when the voltage level of the high-frequency output signal RFout of the final stage amplifier circuit 10B exceeds the clipping voltage Vclp, the bias current of the first stage amplifier circuit 10A is suppressed. As a result, the power of the high-frequency signal input from the first stage amplifier circuit 10A to the final stage amplifier circuit 10B is suppressed. Consequently, the voltage level of the high-frequency output signal RFout of the final stage amplifier circuit 10B decreases. In this way, the final stage amplifier circuit 10B can be protected by suppressing the bias control current of the bias circuit 12 of the first stage amplifier circuit 10A and thereby suppressing the power of the input signal to the final stage amplifier circuit 10B.

[0061] Next, a modified example of the fifth embodiment will be described. In the fifth embodiment, an example in which the power amplifier has a two-stage configuration was described, but the power amplifier may also have a multi-stage configuration of three or more stages. In this case, the first diode circuit 20 is connected to the output node Nout of the final stage amplification circuit 10B, and the clamp transistor 30 is connected to the bias circuit of any one of the amplification circuits other than the final stage amplification circuit 10B.

[0062] The embodiments described above are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects and benefits from similar configurations in multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various modifications, improvements, and combinations are possible.

[0063] 10 Power Amplifier 10A First Stage Amplifier Circuit 10B Final Stage Amplifier Circuit 11 Amplifier Transistor 12 Bias Circuit 12A Emitter Follower Transistor 12B Diode Circuit 12C Resistor Element 13 Resistor Element 14 Choke Coil 18 Impedance Matching Circuit 20 First Diode Circuit 21 Second Diode Circuit 22 Resistor Element 25 Overcurrent Bypass Circuit 30 Clamp Transistor 40 Voltage Regulator 41 Driver Transistor 42 Operational Amplifier 43 Resistor Voltage Divider Circuit 44 Capacitor 50 Control Circuit 51 Reference Voltage Generation Circuit 52 Temperature Characteristic Correction Circuit 52A NMOS Current Mirror Circuit 52B PMOS Current Mirror Circuit 52C Variable Resistor Element 52D Diode 52E PMOS Current Mirror Circuit 52F Variable Resistor Element 52G PMOS Current Mirror Circuit 53 Digital Circuit 54 Bias control current generation circuit 55 Voltage divider ratio adjustment circuit

Claims

1. An active clamp circuit for a power amplifier including a bias circuit, comprising: a first diode circuit including a plurality of diodes connected in multiple stages, the anode end of which is connected to the output node of the power amplifier; a clamp transistor whose base or gate is connected to the cathode end of the first diode circuit and whose collector or drain is connected to the bias circuit and which is configured to suppress the bias current of the power amplifier; a control circuit that generates a variable voltage reference voltage; and a voltage regulator connected to the emitter or source of the clamp transistor, which maintains the voltage at the emitter or source of the clamp transistor at a voltage based on the reference voltage.

2. The active clamp circuit according to claim 1, wherein the voltage regulator includes a driver transistor connected between the emitter or source of the clamp transistor and a reference potential, and an operational amplifier configured to control the on / off state of the driver transistor based on the difference between a feedback voltage based on the drain voltage of the driver transistor and the reference voltage.

3. The active clamp circuit according to claim 2, wherein the voltage regulator includes a resistor voltage divider circuit with a variable voltage division ratio that divides the difference voltage between the drain voltage of the driver transistor and the drain power supply voltage to generate the feedback voltage, and the control circuit can change the voltage division ratio of the resistor voltage divider circuit.

4. The control circuit is an active clamp circuit according to any one of claims 1 to 3, wherein the control circuit changes the reference voltage according to the ambient temperature.

5. The active clamp circuit according to any one of claims 1 to 4, further comprising a second diode circuit connected between the cathode end of the first diode circuit and the reference potential in a direction such that a forward current flows from the first diode circuit to the reference potential.

6. The active clamp circuit according to any one of claims 1 to 5, wherein the clamp transistor is a bipolar transistor.

7. The active clamp circuit according to claim 5, wherein the clamp transistor is a MOSFET.

8. The active clamp circuit according to any one of claims 1 to 7, wherein the power amplifier includes a plurality of amplification circuits, one bias circuit is provided for each of the plurality of amplification circuits, the first diode circuit is connected to the output node of the final stage amplification circuit, and the clamp transistor is connected to the bias circuit of any one of the amplification circuits other than the final stage amplification circuit.

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