Pure hardware double-key power switch circuit

Abstract

The utility model discloses a pure-hardware double-button power switch circuit, and the circuit comprises a first button and a second button which are respectively used for controlling the on and off of the circuit. According to the utility model, the on-off control logic of the power supply is separated through the independent double keys, and the interlocking feedback design of the P-MOS tube and the N-MOS tube is combined, so that the functions of one-key opening self-locking and one-key forced turn-off are realized, and the state disorder caused by mistaken touch is thoroughly avoided; a pure hardware architecture does not need program control or a special chip, so that the cost and the size are greatly reduced, and a surface-mounted device is adapted to meet the miniaturization requirement; the transient suppression network formed by the capacitor and the resistor effectively absorbs transient current conducted by the parasitic diode and power-on interference, prevents self-starting of the power supply, ensures stable operation of the system in a complex scene, and has the advantages of low cost, high reliability and wide applicability.

Description

Technical Field

[0001] This utility model relates to the field of power switch circuit technology, specifically to a pure hardware dual-button power switch circuit. Background Technology

[0002] Currently, power switches in electronic devices are implemented using methods such as self-locking switches, microcontroller program control, and dedicated chips. Self-locking switches are relatively large, occupying valuable space in electronic devices and hindering miniaturization design. Microcontroller program control for power switching is costly and complex, requiring microcontroller pin resources and making it unsuitable for certain scenarios. Dedicated chips are expensive, negatively impacting cost control and market competitiveness. Utility Model Content

[0003] Therefore, the main objective of this utility model is to provide a purely hardware dual-button power switch circuit.

[0004] To achieve the above objectives, the technical solution of this utility model is implemented as follows:

[0005] This utility model embodiment provides a purely hardware dual-button power switch circuit, including:

[0006] The first and second buttons are used to control the circuit to turn on and off, respectively.

[0007] The first resistor and the second resistor, together with the first button, form a voltage divider circuit when the power is off, by pressing the first button, to control the gate voltage of the P-MOS transistor and turn on the P-MOS transistor.

[0008] The third resistor, together with the first and second resistors, forms a voltage divider network. At the same time, when the P-MOS transistor is turned on, it works with the second resistor to form another voltage divider circuit to control the gate voltage of the N-MOS transistor, so that the N-MOS transistor is turned on, thereby forming a circuit self-locking and keeping the power supply on.

[0009] When the second button is pressed while the power is on, the second capacitor, taking advantage of the characteristic that the voltage across the second capacitor cannot change abruptly, instantly pulls down the gate voltage of the N-MOS transistor, turning off the N-MOS transistor and releasing the stored charge through the fourth resistor.

[0010] When both the P-MOS and N-MOS transistors are turned on, the circuit forms a self-locking mechanism, and the first button becomes ineffective; when both the P-MOS and N-MOS transistors are turned off, the power supply remains disconnected, and the second button becomes ineffective.

[0011] In addition, the parasitic diode between the source and drain of the P-MOS transistor works together with the first capacitor to prevent the circuit from self-conducting when the battery is powered on.

[0012] Preferably, in the circuit where the power is off, after pressing the first button, the gate voltage of the P-MOS transistor is pulled down to near 0V through the voltage division effect of the first resistor and the third resistor, thereby turning on the P-MOS transistor.

[0013] In a preferred embodiment of this invention, when the circuit is in the power-on state, pressing the second button causes the second capacitor to charge instantaneously and pull down the gate voltage of the N-MOS transistor, causing the N-MOS transistor to turn off. Subsequently, the gate voltage of the P-MOS transistor is pulled up to the battery voltage by the first resistor, causing the P-MOS transistor to turn off.

[0014] Preferably, in this invention, the first capacitor is used to absorb high-frequency interference and prevent the circuit from self-conducting due to the effect of the parasitic diode at the moment the battery is powered on.

[0015] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0016] This invention utilizes an independent dual-button power on / off control logic, combined with an interlocking feedback design of P-MOS and N-MOS transistors, to achieve one-button self-locking and one-button forced shutdown functions, completely avoiding state disorder caused by accidental touches. The pure hardware architecture requires no program control or dedicated chips, significantly reducing cost and size, and is compatible with surface-mount devices to meet miniaturization requirements. The transient suppression network composed of capacitors and resistors effectively absorbs transient currents from parasitic diode conduction and power-on interference, preventing power supply self-starting and ensuring stable system operation in complex scenarios. It combines low cost, high reliability, and wide applicability. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the present invention and form part of this invention, illustrate exemplary embodiments of the present invention and, together with their description, serve to explain the present invention and do not constitute an undue limitation thereof. In the drawings:

[0018] Figure 1 This is a schematic diagram of a pure hardware dual-button power switch circuit according to an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0020] In the accompanying drawings of this embodiment, the same or similar reference numerals correspond to the same or similar components. In the description of this utility model, it should be understood that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting this patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0021] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes that element.

[0022] This utility model embodiment provides a purely hardware dual-button power switch circuit, such as... Figure 1 As shown, it includes:

[0023] The first button K1 and the second button K2 are used to control the circuit to turn on and off, respectively.

[0024] The first resistor R1 and the second resistor R2, together with the first button K1, form a voltage divider circuit when the power is off, by pressing the first button K1, to control the gate voltage of the P-MOS transistor Q1 and turn on the P-MOS transistor Q1.

[0025] The third resistor R3, together with the first resistor R1 and the second resistor R2, forms a voltage divider network. At the same time, when the P-MOS transistor Q1 is turned on, it works with the second resistor R2 to form another voltage divider circuit to control the gate voltage of the N-MOS transistor Q2, so that the N-MOS transistor Q2 is turned on, thereby forming a circuit self-locking and keeping the power supply on.

[0026] When the second capacitor C2 is in the power-on state, when the second button K2 is pressed, the voltage across the second capacitor C2 cannot change abruptly, so that the gate voltage of the N-MOS transistor Q2 is instantly pulled down, causing the N-MOS transistor Q2 to turn off, and the stored charge is released through the fourth resistor R4.

[0027] Specifically, when both P-MOS transistor Q1 and N-MOS transistor Q2 are turned on, the circuit forms a self-locking mechanism, and the first button K1 becomes ineffective; when both P-MOS transistor Q1 and N-MOS transistor Q2 are turned off, the power supply remains disconnected, and the second button K2 becomes ineffective.

[0028] In addition, the parasitic diode between the source and drain of the P-MOS transistor Q1, together with the first capacitor C1, works to prevent the circuit from self-conducting at the moment the battery is powered on.

[0029] like Figure 1 As shown, when the power is off, pressing the first button K1 will pull the gate voltage of the P-MOS transistor Q1 down to near 0V through the voltage division effect of the first resistor R1 and the third resistor R3, thereby turning on the P-MOS transistor Q1.

[0030] like Figure 1 As shown, when the power is on, pressing the second button K2 causes the second capacitor C2 to charge instantaneously and pull down the gate voltage of the N-MOS transistor Q2, causing the N-MOS transistor Q2 to turn off. Subsequently, the gate voltage of the P-MOS transistor Q1 is pulled up to the battery voltage VBAT by the first resistor R1, causing the P-MOS transistor Q1 to turn off.

[0031] like Figure 1 As shown, the first capacitor C1 is used to absorb high-frequency interference and prevent the circuit from self-conducting due to the effect of the parasitic diode at the moment the battery is powered on.

[0032] The working principle of this utility model is as follows:

[0033] like Figure 1 As shown, when this utility model is in use,

[0034] 1. Power-on process

[0035] Initial state: The circuit is in the power-off state, at which time both P-MOS transistor Q1 and N-MOS transistor Q2 are in the off state.

[0036] Pressing the first activation button K1: When the user presses the first activation button K1, current begins to flow in the circuit. The first resistor R1 and the third resistor R3 form a voltage divider circuit, pulling down the gate voltage of the P-MOS transistor Q1. Due to the characteristics of the P-MOS transistor Q1, when the gate voltage is lower than a certain threshold, the P-MOS transistor Q1 turns on, allowing current to flow from the source to the drain.

[0037] The self-locking mechanism is established as follows: As P-MOS transistor Q1 turns on, the VCC voltage equals VBAT (battery voltage). At this time, the second resistor R2 and the third resistor R3 form a voltage divider circuit again, pulling up the gate voltage of N-MOS transistor Q2, causing N-MOS transistor Q2 to also turn on. The conduction of N-MOS transistor Q2 further pulls down the gate voltage of P-MOS transistor Q1 (through the feedback path of the second resistor R2), ensuring the stable conduction state of P-MOS transistor Q1. At this point, the circuit enters a self-locking state, and the circuit will remain on even if the first button K1 is released.

[0038] 2. Power off process

[0039] Pressing the second off button K2: When the circuit is on, pressing the second off button K2 causes the second capacitor C2 to charge instantaneously. Due to the characteristic that the voltage across the capacitor cannot change abruptly, the gate voltage of the N-MOS transistor Q2 is pulled down instantaneously, causing the N-MOS transistor Q2 to turn off.

[0040] Circuit disconnection: As the N-MOS transistor Q2 is turned off, the gate voltage of the P-MOS transistor Q1 is gradually pulled up to the VBAT level through the first resistor R1, causing the P-MOS transistor Q1 to also turn off. At this time, the current in the circuit is cut off, and the power supply enters the disconnected state.

[0041] Capacitor discharge: The charge stored in the first capacitor C1 and the second capacitor C2 is gradually released and consumed through the third resistor R3 and the fourth resistor R4, respectively, to ensure the stability of the circuit state.

[0042] 3. Prevent the battery from self-conducting upon power-up.

[0043] At the moment the battery is powered on, a parasitic diode exists between the source and drain of the P-MOS transistor Q1. This diode may be close to a short circuit, causing the VCC voltage to rise rapidly and pull the gate of the N-MOS transistor Q2 high through the second resistor R2, potentially causing the circuit to self-conduct. To solve this problem, a first capacitor C1 is added to the circuit. The first capacitor C1 can absorb high-frequency interference signals and prevent circuit malfunctions caused by the parasitic diode at the moment the battery is powered on, thereby ensuring the stability and reliability of the circuit.

[0044] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the scope of protection of the present utility model.

Claims

1. A purely hardware-based dual-button power switch circuit, characterized in that, include: The first and second buttons are used to control the circuit to turn on and off, respectively. The first resistor and the second resistor, together with the first button, form a voltage divider circuit when the power is off, by pressing the first button, to control the gate voltage of the P-MOS transistor and turn on the P-MOS transistor. The third resistor, together with the first and second resistors, forms a voltage divider network. At the same time, when the P-MOS transistor is turned on, it works with the second resistor to form another voltage divider circuit to control the gate voltage of the N-MOS transistor, so that the N-MOS transistor is turned on, thereby forming a circuit self-locking and keeping the power supply on. When the second button is pressed while the power is on, the second capacitor, taking advantage of the characteristic that the voltage across the second capacitor cannot change abruptly, instantly pulls down the gate voltage of the N-MOS transistor, turning off the N-MOS transistor and releasing the stored charge through the fourth resistor. When both the P-MOS and N-MOS transistors are turned on, the circuit forms a self-locking mechanism, and the first button becomes ineffective; when both the P-MOS and N-MOS transistors are turned off, the power supply remains disconnected, and the second button becomes ineffective. Additionally, a parasitic diode and a first capacitor between the source and drain of the P-MOS transistor prevent the circuit from self-conducting at the moment the battery is powered on.

2. The pure hardware dual-button power switch circuit according to claim 1, characterized in that, When the power is off, pressing the first button in the circuit will pull the gate voltage of the P-MOS transistor down to near 0V through the voltage division effect of the first resistor and the third resistor, thereby turning on the P-MOS transistor.

3. The pure hardware dual-button power switch circuit according to claim 2, characterized in that, When the circuit is powered on, pressing the second button causes the second capacitor to charge instantaneously and pull down the gate voltage of the N-MOS transistor, causing the N-MOS transistor to turn off. Subsequently, the gate voltage of the P-MOS transistor is pulled up to the battery voltage by the first resistor, causing the P-MOS transistor to turn off.

4. The pure hardware dual-button power switch circuit according to claim 3, characterized in that, The first capacitor is used to absorb high-frequency interference and prevent the circuit from self-conducting due to the parasitic diode at the moment the battery is powered on.

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